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robfinch |
; ============================================================================
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; __
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; \\__/ o\ (C) 2013-2022 Robert Finch, Waterloo
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; \ __ / All rights reserved.
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; \/_// robfinch@opencores.org
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; ||
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;
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;
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; BSD 3-Clause License
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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;
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; 1. Redistributions of source code must retain the above copyright notice, this
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; list of conditions and the following disclaimer.
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;
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; 2. Redistributions in binary form must reproduce the above copyright notice,
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; this list of conditions and the following disclaimer in the documentation
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; and/or other materials provided with the distribution.
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;
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; 3. Neither the name of the copyright holder nor the names of its
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; contributors may be used to endorse or promote products derived from
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; this software without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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; ============================================================================
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;
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;===============================================================================
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; Generic I2C routines
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;
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; It is assumed there may be more than one I2C controller in the system, so
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; the address of the controller is passed in the X register.
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;===============================================================================
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I2C_PREL EQU $0
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I2C_PREH EQU $1
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I2C_CTRL EQU $2
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I2C_RXR EQU $3
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I2C_TXR EQU $3
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I2C_CMD EQU $4
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I2C_STAT EQU $4
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; i2c initialization, sets the clock prescaler
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;
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; Parameters:
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; x = I2C controller address
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; Returns: none
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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robfinch |
i2c_init:
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robfinch |
pshs b
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ldb #4 ; setup prescale for 400kHz clock
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stb I2C_PREL,x
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clr I2C_PREH,x
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puls b,pc
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; Wait for I2C transfer to complete
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;
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; Parameters
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; x - I2C controller base address
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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i2c_wait_tip:
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pshs b
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i2cw1:
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ldb I2C_STAT,x ; would use lvb, but lb is okay since its the I/O area
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bitb #1 ; wait for tip to clear
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bne i2cw1
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puls b,pc
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; Write command to i2c
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;
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; Parameters
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; accb - data to transmit
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; acca - command value
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; x - I2C controller base address
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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i2c_wr_cmd:
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stb I2C_TXR,x
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sta I2C_CMD,x
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bsr i2c_wait_tip
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ldb I2C_STAT,x
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rts
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; Parameters
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; x - I2C controller base address
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; accb - data to send
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; Returns: none
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; Stack space: 2 words
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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robfinch |
i2c_xmit1:
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robfinch |
pshs d ; save data value
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pshs d ; and save it again
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ldb #1
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stb I2C_CTRL,x ; enable the core
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ldb #$76 ; set slave address = %0111011
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lda #$90 ; set STA, WR
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bsr i2c_wr_cmd
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bsr i2c_wait_rx_nack
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puls d ; get back data value
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lda #$50 ; set STO, WR
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bsr i2c_wr_cmd
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bsr i2c_wait_rx_nack
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puls d,pc
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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i2c_wait_rx_nack:
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pshs b ; save off accb
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i2cwr1:
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ldb I2C_STAT,x ; wait for RXack = 0
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bitb #$80 ; test for nack
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bne i2cwr1
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puls b,pc
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