1 |
13 |
robfinch |
; ============================================================================
|
2 |
|
|
; __
|
3 |
|
|
; \\__/ o\ (C) 2022 Robert Finch, Waterloo
|
4 |
|
|
; \ __ / All rights reserved.
|
5 |
|
|
; \/_// robfinch@opencores.org
|
6 |
|
|
; ||
|
7 |
|
|
;
|
8 |
|
|
;
|
9 |
|
|
; BSD 3-Clause License
|
10 |
|
|
; Redistribution and use in source and binary forms, with or without
|
11 |
|
|
; modification, are permitted provided that the following conditions are met:
|
12 |
|
|
;
|
13 |
|
|
; 1. Redistributions of source code must retain the above copyright notice, this
|
14 |
|
|
; list of conditions and the following disclaimer.
|
15 |
|
|
;
|
16 |
|
|
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
17 |
|
|
; this list of conditions and the following disclaimer in the documentation
|
18 |
|
|
; and/or other materials provided with the distribution.
|
19 |
|
|
;
|
20 |
|
|
; 3. Neither the name of the copyright holder nor the names of its
|
21 |
|
|
; contributors may be used to endorse or promote products derived from
|
22 |
|
|
; this software without specific prior written permission.
|
23 |
|
|
;
|
24 |
|
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
25 |
|
|
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
26 |
|
|
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
27 |
|
|
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
28 |
|
|
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
29 |
|
|
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
30 |
|
|
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
31 |
|
|
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
32 |
|
|
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
33 |
|
|
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
34 |
|
|
;
|
35 |
|
|
; ============================================================================
|
36 |
|
|
|
37 |
|
|
;===============================================================================
|
38 |
|
|
; Realtime clock routines
|
39 |
|
|
;===============================================================================
|
40 |
|
|
|
41 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
42 |
|
|
; Read the real-time-clock chip.
|
43 |
|
|
;
|
44 |
|
|
; The entire contents of the clock registers and sram are read into a buffer
|
45 |
|
|
; in one-shot rather than reading the registers individually.
|
46 |
|
|
;
|
47 |
|
|
; Parameters: none
|
48 |
|
|
; Returns: d = 0 on success, otherwise non-zero
|
49 |
|
|
; Modifies: d and RTCBuf
|
50 |
|
|
; Stack space: 6 words
|
51 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
52 |
|
|
|
53 |
|
|
rtc_read:
|
54 |
|
|
ldx #RTC
|
55 |
|
|
ldy #RTCBuf
|
56 |
|
|
ldb #$80
|
57 |
|
|
stb I2C_CTRL,x ; enable I2C
|
58 |
|
|
ldd #$900DE ; read address, write op, STA + wr bit
|
59 |
|
|
bsr i2c_wr_cmd
|
60 |
|
|
bitb #$80
|
61 |
|
|
bne rtc_rxerr
|
62 |
|
|
ldd #$10000 ; address zero, wr bit
|
63 |
|
|
bsr i2c_wr_cmd
|
64 |
|
|
bitb #$80
|
65 |
|
|
bne rtc_rxerr
|
66 |
|
|
ldd #$900DF ; read address, read op, STA + wr bit
|
67 |
|
|
bsr i2c_wr_cmd
|
68 |
|
|
bitb #$80
|
69 |
|
|
bne rtc_rxerr
|
70 |
|
|
|
71 |
|
|
clrb
|
72 |
|
|
rtcr0001:
|
73 |
|
|
lda #$20
|
74 |
|
|
sta I2C_CMD,x ; rd bit
|
75 |
|
|
bsr i2c_wait_tip
|
76 |
|
|
bsr i2c_wait_rx_nack
|
77 |
|
|
lda I2C_STAT,x
|
78 |
|
|
bita #$80
|
79 |
|
|
bne rtc_rxerr
|
80 |
|
|
lda I2C_RXR,x
|
81 |
|
|
sta b,y
|
82 |
|
|
incb
|
83 |
|
|
cmpb #$5F
|
84 |
|
|
blo rtcr0001
|
85 |
|
|
lda #$68
|
86 |
|
|
sta I2C_CMD,x ; STO, rd bit + nack
|
87 |
|
|
bsr i2c_wait_tip
|
88 |
|
|
lda I2C_STAT,x
|
89 |
|
|
bita #$80
|
90 |
|
|
bne rtc_rxerr
|
91 |
|
|
lda I2C_RXR,x
|
92 |
|
|
sta b,y
|
93 |
|
|
clrd ; return 0
|
94 |
|
|
rtc_rxerr:
|
95 |
|
|
clr I2C_CTRL,x ; disable I2C and return status
|
96 |
|
|
clra
|
97 |
|
|
rts
|
98 |
|
|
|
99 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
100 |
|
|
; Write the real-time-clock chip.
|
101 |
|
|
;
|
102 |
|
|
; The entire contents of the clock registers and sram are written from a
|
103 |
|
|
; buffer (RTCBuf) in one-shot rather than writing the registers individually.
|
104 |
|
|
;
|
105 |
|
|
; Parameters: none
|
106 |
|
|
; Returns: r1 = 0 on success, otherwise non-zero
|
107 |
|
|
; Modifies: r1 and RTCBuf
|
108 |
|
|
; Stack space: 6 words
|
109 |
|
|
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
|
110 |
|
|
|
111 |
|
|
rtc_write:
|
112 |
|
|
ldx #RTC
|
113 |
|
|
ldy #RTCBuf
|
114 |
|
|
|
115 |
|
|
ldb #$80
|
116 |
|
|
stb I2C_CTRL,x ; enable I2C
|
117 |
|
|
ldd #$900DE ; read address, write op, STA + wr bit
|
118 |
|
|
bsr i2c_wr_cmd
|
119 |
|
|
bitb #$80
|
120 |
|
|
bne rtc_rxerr
|
121 |
|
|
ldd #$10000 ; address zero, wr bit
|
122 |
|
|
bsr i2c_wr_cmd
|
123 |
|
|
bitb #$80
|
124 |
|
|
bne rtc_rxerr
|
125 |
|
|
|
126 |
|
|
ldb #0
|
127 |
|
|
rtcw0001:
|
128 |
|
|
pshs b
|
129 |
|
|
ldb b,y
|
130 |
|
|
lda #$10
|
131 |
|
|
bsr i2c_wr_cmd
|
132 |
|
|
bitb #$80
|
133 |
|
|
puls b
|
134 |
|
|
bne rtc_rxerr
|
135 |
|
|
incb
|
136 |
|
|
cmpb #$5F
|
137 |
|
|
blo rtcw0001
|
138 |
|
|
ldb b,y
|
139 |
|
|
lda #$50 ; STO, wr bit
|
140 |
|
|
bsr i2c_wr_cmd
|
141 |
|
|
bitb #$80
|
142 |
|
|
bne rtc_rxerr
|
143 |
|
|
clrd ; return 0
|
144 |
|
|
clr I2C_CTRL,x ; disable I2C and return status
|
145 |
|
|
rts
|