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[/] [rf6809/] [trunk/] [software/] [boot/] [timer.asm] - Blame information for rev 12
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robfinch |
; ============================================================================
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; __
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; \\__/ o\ (C) 2022 Robert Finch, Waterloo
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; \ __ / All rights reserved.
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; \/_// robfinch@opencores.org
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; ||
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;
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;
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; Timer routines for a WDC6522 compatible circuit.
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;
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; This source file is free software: you can redistribute it and/or modify
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; it under the terms of the GNU Lesser General Public License as published
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; by the Free Software Foundation, either version 3 of the License, or
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; (at your option) any later version.
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;
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; This source file is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program. If not, see .
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;
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; ============================================================================
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;
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TimerInit:
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ldd #$61A80 ; compare to 400000 (100 Hz assuming 40MHz clock)
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stb VIA+VIA_T3CMPL
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sta VIA+VIA_T3CMPH
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clr VIA+VIA_T3LL
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clr VIA+VIA_T3LH
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lda VIA+VIA_ACR ; set continuous mode for timer
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ora #$100
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sta VIA+VIA_ACR ; enable timer #3 interrupts
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lda #$810
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sta VIA+VIA_IER
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rts
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TimerIRQ:
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; Reset the edge sense circuit in the PIC
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lda #31 ; Timer is IRQ #31
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sta IrqSource ; stuff a byte indicating the IRQ source for PEEK()
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sta PIC+16 ; register 16 is edge sense reset reg
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lda VIA+VIA_IFR
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bpl notTimerIRQ
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bita #$800
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beq notTimerIRQ
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clr VIA+VIA_T3LL
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clr VIA+VIA_T3LH
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inc $E00037 ; update timer IRQ screen flag
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notTimerIRQ:
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rts
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