| 1 |
9 |
robfinch |
; ============================================================================
|
| 2 |
|
|
; __
|
| 3 |
|
|
; \\__/ o\ (C) 2022 Robert Finch, Waterloo
|
| 4 |
|
|
; \ __ / All rights reserved.
|
| 5 |
|
|
; \/_// robfinch@opencores.org
|
| 6 |
|
|
; ||
|
| 7 |
|
|
;
|
| 8 |
|
|
;
|
| 9 |
|
|
; Timer routines for a WDC6522 compatible circuit.
|
| 10 |
|
|
;
|
| 11 |
|
|
; This source file is free software: you can redistribute it and/or modify
|
| 12 |
|
|
; it under the terms of the GNU Lesser General Public License as published
|
| 13 |
|
|
; by the Free Software Foundation, either version 3 of the License, or
|
| 14 |
|
|
; (at your option) any later version.
|
| 15 |
|
|
;
|
| 16 |
|
|
; This source file is distributed in the hope that it will be useful,
|
| 17 |
|
|
; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 18 |
|
|
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 19 |
|
|
; GNU General Public License for more details.
|
| 20 |
|
|
;
|
| 21 |
|
|
; You should have received a copy of the GNU General Public License
|
| 22 |
|
|
; along with this program. If not, see .
|
| 23 |
|
|
;
|
| 24 |
|
|
; ============================================================================
|
| 25 |
|
|
;
|
| 26 |
|
|
TimerInit:
|
| 27 |
|
|
ldd #$61A80 ; compare to 400000 (100 Hz assuming 40MHz clock)
|
| 28 |
|
|
stb VIA+VIA_T3CMPL
|
| 29 |
|
|
sta VIA+VIA_T3CMPH
|
| 30 |
|
|
clr VIA+VIA_T3LL
|
| 31 |
|
|
clr VIA+VIA_T3LH
|
| 32 |
|
|
lda VIA+VIA_ACR ; set continuous mode for timer
|
| 33 |
|
|
ora #$100
|
| 34 |
21 |
robfinch |
sta VIA+VIA_ACR
|
| 35 |
|
|
lda #$880 ; enable timer #3 interrupts
|
| 36 |
9 |
robfinch |
sta VIA+VIA_IER
|
| 37 |
|
|
rts
|
| 38 |
|
|
|
| 39 |
|
|
TimerIRQ:
|
| 40 |
|
|
; Reset the edge sense circuit in the PIC
|
| 41 |
|
|
lda #31 ; Timer is IRQ #31
|
| 42 |
|
|
sta PIC+16 ; register 16 is edge sense reset reg
|
| 43 |
21 |
robfinch |
lda PIC+$FF ; Timer active interrupt flag
|
| 44 |
9 |
robfinch |
beq notTimerIRQ
|
| 45 |
21 |
robfinch |
clr PIC+$FF ; clear the flag
|
| 46 |
|
|
lda #31 ; Timer is IRQ #31
|
| 47 |
|
|
sta IrqSource ; stuff a byte indicating the IRQ source for PEEK()
|
| 48 |
|
|
clr VIA+VIA_T3LL ; should clear the interrupt
|
| 49 |
9 |
robfinch |
clr VIA+VIA_T3LH
|
| 50 |
21 |
robfinch |
lda #31 ; Timer is IRQ #31
|
| 51 |
|
|
sta PIC+16 ; register 16 is edge sense reset reg
|
| 52 |
|
|
clr PIC+$FF ; clear the flag
|
| 53 |
|
|
inc $E0003F ; update timer IRQ screen flag
|
| 54 |
|
|
ldd milliseconds+2
|
| 55 |
|
|
addd #10
|
| 56 |
|
|
std milliseconds+2
|
| 57 |
|
|
ldd milliseconds
|
| 58 |
|
|
adcb #0
|
| 59 |
|
|
stb milliseconds+1
|
| 60 |
|
|
adca #0
|
| 61 |
|
|
sta milliseconds
|
| 62 |
|
|
|
| 63 |
|
|
; Update XModem timer, we just always do it rather than testing if XModem
|
| 64 |
|
|
; is active. The increment is set to give approximately 3s before the MSB
|
| 65 |
|
|
; gets set.
|
| 66 |
|
|
ldb xm_timer
|
| 67 |
|
|
addb #4
|
| 68 |
|
|
stb xm_timer
|
| 69 |
9 |
robfinch |
notTimerIRQ:
|
| 70 |
|
|
rts
|
| 71 |
|
|
|
