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<div class=Section1>
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<h1>Encryption Block</h1>
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<h2><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;font-family:Arial'>John
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Purba (</span><a href="mailto:john@students.ee.itb.ac.id">john@students.ee.itb.ac.id</a><span
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style='font-size:10.0pt;mso-bidi-font-size:12.0pt;font-family:Arial'>)<o:p></o:p></span></h2>
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<p class=MsoNormal><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>
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<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
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font-family:Arial'>The encryption block comprises 6 blocks:<o:p></o:p></span></p>
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<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
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tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
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mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
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font-family:Arial'>Data &amp; Key Input Register, interface of input data and
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key<o:p></o:p></span></p>
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<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
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tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
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mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
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font-family:Arial'>Key Expander, generator the round key<o:p></o:p></span></p>
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<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
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tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
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mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
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font-family:Arial'>Control, controls each block <o:p></o:p></span></p>
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<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
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tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
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mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
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font-family:Arial'>Rijndael Alg, implements Rijndael algorithm (round
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calculations)<o:p></o:p></span></p>
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<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
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tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
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mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
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font-family:Arial'>Data Output Register, interface of output data<o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
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font-family:Arial'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
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font-family:Arial'>The RTL VHDL code can be downloaded here <a
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href="enkrip_files\enkrip.zip"><span style='font-size:12.0pt;font-family:"Times New Roman"'>enkrip.zip</span></a><o:p></o:p></span></p>
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<p class=MsoNormal style='mso-layout-grid-align:none;text-autospace:none'><span
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style='font-size:10.0pt;mso-bidi-font-size:12.0pt;font-family:Arial'>The
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encryption algorithm has been designed this way that the generation of round
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key and the round calculations can be parallely executed. </span><span
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style='font-size:10.0pt;font-family:Arial'>The advantage of this design is the
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fact that we do not need to store the round key since they are currently
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calculated. Interconnection of each block is depicted in figure 1.<o:p></o:p></span></p>
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absolute;z-index:2;left:0px;margin-left:446px;margin-top:152px;width:120px;
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height:96px'><a href="#Rijndael_alg"><img border=0 width=120 height=96
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height:96px'><a href="#Key_Expander"><img border=0 width=120 height=96
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<p class=MsoNormal align=center style='text-align:center'><span
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style='font-family:Arial'>Figure 1<o:p></o:p></span></p>
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<p class=MsoNormal align=center style='text-align:center'><a
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name="Data_Kunci_Reg"><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></a></p>
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<p class=MsoNormal><span style='mso-bookmark:Data_Kunci_Reg'><span
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style='font-size:16.0pt;mso-bidi-font-size:12.0pt;font-family:Arial'>1. Data
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&amp; Key Input Register</span></span><span style='font-size:16.0pt;mso-bidi-font-size:
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12.0pt;font-family:Arial'><o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
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font-family:Arial'><span style='mso-tab-count:1'>            </span>This block is
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data or key input interface. The length of data or key supported is 128 bits,
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so we can use the same design for data input and key input. This block will
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take 32 bits data and shifts them to next register. Four clock cycle will be
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needed to take a complete 128 bit data. A simple controller is used here to
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identify that a complete of 128 bits data has been accepted. The State Diagram
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of FSMInput and Data or Key Input Register is depicted in figure 2.<o:p></o:p></span></p>
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<p class=MsoNormal align=center style='text-align:center'><!--[if gte vml 1]><v:shape
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</v:shape><![endif]--><![if !vml]><img border=0 width=660 height=449
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<p class=MsoNormal align=center style='text-align:center'><span
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style='font-family:Arial'>Figure 2</span><span style='font-size:10.0pt;
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mso-bidi-font-size:12.0pt;font-family:Arial'><o:p></o:p></span></p>
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<p class=MsoNormal><a name="Data_Reg"><span style='font-size:16.0pt;mso-bidi-font-size:
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12.0pt;font-family:Arial'>2. Data Output Register</span></a><span
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style='font-size:16.0pt;mso-bidi-font-size:12.0pt;font-family:Arial'><o:p></o:p></span></p>
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<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
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font-family:Arial'><span style='mso-tab-count:1'>            </span>This block
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takes 128 bit block data to output. First one block of 128 bits is divided to 4
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blocks of 32 bits. One block of 32 bits data is take to output every one clock cycle.
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Data output register is depicted in figure 3.<o:p></o:p></span></p>
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<p class=MsoNormal align=center style='text-align:center'><!--[if gte vml 1]><v:shape
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</v:shape><![endif]--><![if !vml]><img border=0 width=618 height=252
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<p class=MsoNormal align=center style='text-align:center'><span
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style='font-family:Arial'>Figure 3</span><span style='font-size:10.0pt;
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mso-bidi-font-size:12.0pt;font-family:Arial'><o:p></o:p></span></p>
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<p class=MsoNormal><a name=Control><span style='font-size:16.0pt;mso-bidi-font-size:
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12.0pt;font-family:Arial'>3. Control</span></a><span style='font-size:16.0pt;
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mso-bidi-font-size:12.0pt;font-family:Arial'><o:p></o:p></span></p>
369
 
370
<p class=MsoBodyText><span style='mso-tab-count:1'>            </span>The
371
Control block controls the Key Expander and Rijndael Alg block. The state
372
diagram of Control block is depicted in figure 4.</p>
373
 
374
<p class=MsoNormal align=center style='text-align:center'><!--[if gte vml 1]><v:shape
375
 id="_x0000_i1136" type="#_x0000_t75" style='width:192pt;height:324pt' o:ole="">
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 <v:imagedata src="./enkrip_files/image012.wmz" o:title=""/>
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</v:shape><![endif]--><![if !vml]><img border=0 width=256 height=432
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src="./enkrip_files/image013.gif" v:shapes="_x0000_i1136"><![endif]><!--[if gte mso 9]><xml>
379
 <o:OLEObject Type="Embed" ProgID="Visio.Drawing.5" ShapeID="_x0000_i1136"
380
  DrawAspect="Content" ObjectID="_1086186390">
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 </o:OLEObject>
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</xml><![endif]--><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
383
font-family:Arial'><o:p></o:p></span></p>
384
 
385
<p class=MsoNormal align=center style='text-align:center'><span
386
style='font-family:Arial'>Figure 4<o:p></o:p></span></p>
387
 
388
<p class=MsoNormal><a name="Key_Expander"><span style='font-size:16.0pt;
389
mso-bidi-font-size:12.0pt;font-family:Arial'>4. Key Expander<o:p></o:p></span></a></p>
390
 
391
<p class=MsoBodyText><span style='mso-bookmark:Key_Expander'><span
392
style='mso-tab-count:1'>            </span>Key Expander responsible to generate
393
round key for every round from the initial key. Based on the algorithm
394
specification, if we use 128-bit key, 10 rounds will be needed. Hence the Key
395
Expander will generate 10 round keys. The Key Expander is depicted in figure 5.
396
</span></p>
397
 
398
<span style='mso-bookmark:Key_Expander'></span>
399
 
400
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
401
font-family:Arial'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></span></p>
402
 
403
<p class=MsoNormal align=center style='text-align:center'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>
404
 
405
<p class=MsoNormal align=center style='text-align:center'><!--[if gte vml 1]><v:shape
406
 id="_x0000_i1124" type="#_x0000_t75" style='width:307.5pt;height:252pt' o:ole="">
407
 <v:imagedata src="./enkrip_files/image014.wmz" o:title=""/>
408
</v:shape><![endif]--><![if !vml]><img border=0 width=410 height=336
409
src="./enkrip_files/image015.gif" v:shapes="_x0000_i1124"><![endif]><!--[if gte mso 9]><xml>
410
 <o:OLEObject Type="Embed" ProgID="Visio.Drawing.5" ShapeID="_x0000_i1124"
411
  DrawAspect="Content" ObjectID="_1086186391">
412
 </o:OLEObject>
413
</xml><![endif]--></p>
414
 
415
<p class=MsoNormal align=center style='text-align:center'><span
416
style='font-family:Arial'>Figure 5<o:p></o:p></span></p>
417
 
418
<p class=MsoNormal align=center style='text-align:center'><span
419
style='font-family:Arial'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></span></p>
420
 
421
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
422
font-family:Arial'>The Blok Alg implements the XOR operations and RotByte function.
423
Kontroler Internal controls the Key Expander and its state diagram illustrated
424
in figure 6. The ByteSub block is the same as ByteSub for Rijndael Alg Block.<o:p></o:p></span></p>
425
 
426
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
427
font-family:Arial'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></span></p>
428
 
429
<h3>State Diagram of Kontroler Internal</h3>
430
 
431
<p class=MsoNormal align=center style='text-align:center'><!--[if gte vml 1]><v:shape
432
 id="_x0000_i1113" type="#_x0000_t75" style='width:399pt;height:228pt' o:ole="">
433
 <v:imagedata src="./enkrip_files/image016.wmz" o:title=""/>
434
</v:shape><![endif]--><![if !vml]><img border=0 width=532 height=304
435
src="./enkrip_files/image017.gif" v:shapes="_x0000_i1113"><![endif]><!--[if gte mso 9]><xml>
436
 <o:OLEObject Type="Embed" ProgID="Visio.Drawing.5" ShapeID="_x0000_i1113"
437
  DrawAspect="Content" ObjectID="_1086186392">
438
 </o:OLEObject>
439
</xml><![endif]--></p>
440
 
441
<p class=MsoNormal align=center style='text-align:center'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></p>
442
 
443
<p class=MsoNormal align=center style='text-align:center'><span
444
style='font-family:Arial'>Figure 6</span><span style='font-size:10.0pt;
445
mso-bidi-font-size:12.0pt;font-family:Arial'><o:p></o:p></span></p>
446
 
447
<p class=MsoNormal><a name="Rijndael_alg"><span style='font-size:16.0pt;
448
mso-bidi-font-size:12.0pt;font-family:Arial'>5. Rijndael Alg</span></a><span
449
style='font-size:16.0pt;mso-bidi-font-size:12.0pt;font-family:Arial'><o:p></o:p></span></p>
450
 
451
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
452
font-family:Arial'><span style='mso-tab-count:1'>            </span>The
453
implementation of Rijndael Alg has been designed this way that it can work as
454
the initial round, standard round, and final round. The Rijndael Alg module is
455
depicted in figure 7. <o:p></o:p></span></p>
456
 
457
<p class=MsoNormal align=center style='text-align:center'><!--[if gte vml 1]><v:shape
458
 id="_x0000_i1046" type="#_x0000_t75" style='width:508.5pt;height:176.25pt'
459
 o:ole="">
460
 <v:imagedata src="./enkrip_files/image018.wmz" o:title=""/>
461
</v:shape><![endif]--><![if !vml]><img border=0 width=678 height=235
462
src="./enkrip_files/image019.gif" v:shapes="_x0000_i1046"><![endif]><!--[if gte mso 9]><xml>
463
 <o:OLEObject Type="Embed" ProgID="Visio.Drawing.5" ShapeID="_x0000_i1046"
464
  DrawAspect="Content" ObjectID="_1086186393">
465
 </o:OLEObject>
466
</xml><![endif]--></p>
467
 
468
<p class=MsoNormal align=center style='text-align:center'><span
469
style='font-family:Arial'>Figure 7<o:p></o:p></span></p>
470
 
471
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
472
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
473
mso-bidi-font-size:12.0pt;mso-bidi-font-weight:bold'>-<span style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
474
</span></span><![endif]><b><span style='font-size:10.0pt;mso-bidi-font-size:
475
12.0pt;font-family:Arial'>Mux21<o:p></o:p></span></b></p>
476
 
477
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
478
mso-bidi-font-size:12.0pt;font-family:Arial'>Mux21 is a simple multiplexer 2 to
479
1. The format of data (din_i) is changed in this block, a block 128 bits sequence
480
to matrix 4x4 called State, as it is easier to design another blocks
481
(AddRoundKey, ByteSub, ShiftRow. MixColumn) <o:p></o:p></span></p>
482
 
483
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
484
mso-bidi-font-size:12.0pt;font-family:Arial'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></span></p>
485
 
486
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
487
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
488
mso-bidi-font-size:12.0pt;mso-bidi-font-weight:bold'>-<span style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
489
</span></span><![endif]><b><span style='font-size:10.0pt;mso-bidi-font-size:
490
12.0pt;font-family:Arial'>AddRoundKey<o:p></o:p></span></b></p>
491
 
492
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
493
mso-bidi-font-size:12.0pt;font-family:Arial'>Implements AddRoundKey transformation,
494
a simple XOR between State and round key. <o:p></o:p></span></p>
495
 
496
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
497
mso-bidi-font-size:12.0pt;font-family:Arial'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></span></p>
498
 
499
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
500
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
501
mso-bidi-font-size:12.0pt;mso-bidi-font-weight:bold'>-<span style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
502
</span></span><![endif]><b><span style='font-size:10.0pt;mso-bidi-font-size:
503
12.0pt;font-family:Arial'>ByteSub<o:p></o:p></span></b></p>
504
 
505
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
506
mso-bidi-font-size:12.0pt;font-family:Arial'>Implements ByteSub transformation,
507
contains 16 S-Box working in parallel. Dual Port Block RAM will be used to implements
508
2 S-Box, which emulate the ROM memory with configuration of 256x8 bits.<o:p></o:p></span></p>
509
 
510
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
511
mso-bidi-font-size:12.0pt;font-family:Arial'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></span></p>
512
 
513
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
514
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
515
mso-bidi-font-size:12.0pt;mso-bidi-font-weight:bold'>-<span style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
516
</span></span><![endif]><b><span style='font-size:10.0pt;mso-bidi-font-size:
517
12.0pt;font-family:Arial'>ShiftRow<o:p></o:p></span></b></p>
518
 
519
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
520
mso-bidi-font-size:12.0pt;font-family:Arial'>Implements ShiftRow transformation.
521
The position of bytes in State will shifted cyclical by offsets. The first row
522
is shifted by zero, the second row is shifter by one, the third row is shifted
523
by two, and the fourth row is shifted by three. The implementation is realized
524
by hardwiring and do not need gate resource.<o:p></o:p></span></p>
525
 
526
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
527
mso-bidi-font-size:12.0pt;font-family:Arial'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></span></p>
528
 
529
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
530
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
531
mso-bidi-font-size:12.0pt;mso-bidi-font-weight:bold'>-<span style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
532
</span></span><![endif]><b><span style='font-size:10.0pt;mso-bidi-font-size:
533
12.0pt;font-family:Arial'>MixColumn<o:p></o:p></span></b></p>
534
 
535
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
536
mso-bidi-font-size:12.0pt;font-family:Arial'>Implements MixColumn transformation.
537
The columns of State are viewed as the coefficients of polynomial over GF (2<sup>8</sup>)
538
of degree smaller than three. This polynomial is multiplied by four terms fixed
539
polynomial a(x), {03)x<sup>3</sup> + {01}x<sup>2</sup> + {01}x + {02}, modulo
540
the polynomial x<sup>4</sup> + 1.The multiplication with four terms fixed
541
polynomial can be simplified by using the matrix form. The implementation of
542
this transformation can be realized as shift and XOR operations.<o:p></o:p></span></p>
543
 
544
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
545
font-family:Arial'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></span></p>
546
 
547
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
548
font-family:Arial'><![if !supportEmptyParas]>&nbsp;<![endif]><o:p></o:p></span></p>
549
 
550
<h4><b>Implementation Result<o:p></o:p></b></h4>
551
 
552
<p class=MsoNormal><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
553
font-family:Arial'><span style='mso-tab-count:1'>            </span>The
554
encryption algorithm has been implemented to FPGA Xilinx Virtex V300PQ240. It
555
has 20 Dual Port Block RAM to implement to ByteSub transformation. The
556
implementation parameters are:<o:p></o:p></span></p>
557
 
558
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
559
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
560
mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
561
</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
562
font-family:Arial'>Speed<o:p></o:p></span></p>
563
 
564
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
565
mso-bidi-font-size:12.0pt;font-family:Arial'>The maximum frequency is 51 MHz
566
corresponds to throughput 298,899 Mbps.<o:p></o:p></span></p>
567
 
568
<p class=MsoNormal style='margin-left:.5in;text-indent:-.25in;mso-list:l0 level1 lfo1;
569
tab-stops:list .5in'><![if !supportLists]><span style='font-size:10.0pt;
570
mso-bidi-font-size:12.0pt'>-<span style='font:7.0pt "Times New Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
571
</span></span><![endif]><span style='font-size:10.0pt;mso-bidi-font-size:12.0pt;
572
font-family:Arial'>Area<o:p></o:p></span></p>
573
 
574
<p class=MsoNormal style='margin-left:.5in'><span style='font-size:10.0pt;
575
mso-bidi-font-size:12.0pt;font-family:Arial'>The design required 666 slices<o:p></o:p></span></p>
576
 
577
</div>
578
 
579
</body>
580
 
581
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