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-------------------------------------------------------------------------------
-- 
-- RapidIO IP Library Core
-- 
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
-- 
-- Description
-- Contains automatic test code to verify a RioWbBridge implementation.
-- 
-- To Do:
-- - Add testcases to NWRITE to cover all possible access lengths, not just the
--   maximum as presently.
-- 
-- Author(s): 
-- - Magnus Rosenius, magro732@opencores.org 
-- 
-------------------------------------------------------------------------------
-- 
-- Copyright (C) 2013 Authors and OPENCORES.ORG 
-- 
-- This source file may be used and distributed without 
-- restriction provided that this copyright statement is not 
-- removed from the file and that any derivative work contains 
-- the original copyright notice and the associated disclaimer. 
-- 
-- This source file is free software; you can redistribute it 
-- and/or modify it under the terms of the GNU Lesser General 
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any 
-- later version. 
-- 
-- This source is distributed in the hope that it will be 
-- useful, but WITHOUT ANY WARRANTY; without even the implied 
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
-- PURPOSE. See the GNU Lesser General Public License for more 
-- details. 
-- 
-- You should have received a copy of the GNU Lesser General 
-- Public License along with this source; if not, download it 
-- from http://www.opencores.org/lgpl.shtml 
-- 
-------------------------------------------------------------------------------
 
 
-------------------------------------------------------------------------------
-- TestRioWbBridge.
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
use work.rio_common.all;
use work.TestPortPackage.all;
 
 
-------------------------------------------------------------------------------
-- Entity for TestRioWbBridge.
-------------------------------------------------------------------------------
entity TestRioWbBridge is
end entity;
 
 
-------------------------------------------------------------------------------
-- Architecture for TestRioWbBridge.
-------------------------------------------------------------------------------
architecture TestRioWbBridgeImpl of TestRioWbBridge is
 
  component RioWbBridge is
    generic(
      EXTENDED_ADDRESS : natural range 0 to 2 := 0;
      DEVICE_IDENTITY : std_logic_vector(15 downto 0);
      DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
      DEVICE_REV : std_logic_vector(31 downto 0);
      ASSY_IDENTITY : std_logic_vector(15 downto 0);
      ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
      ASSY_REV : std_logic_vector(15 downto 0));
    port(
      clk : in std_logic;
      areset_n : in std_logic;
      enable : in std_logic;
 
      readFrameEmpty_i : in std_logic;
      readFrame_o : out std_logic;
      readContent_o : out std_logic;
      readContentEnd_i : in std_logic;
      readContentData_i : in std_logic_vector(31 downto 0);
      writeFrameFull_i : in std_logic;
      writeFrame_o : out std_logic;
      writeFrameAbort_o : out std_logic;
      writeContent_o : out std_logic;
      writeContentData_o : out std_logic_vector(31 downto 0);
 
      cyc_o : out std_logic;
      stb_o : out std_logic;
      we_o : out std_logic;
      adr_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);
      sel_o : out std_logic_vector(7 downto 0);
      dat_o : out std_logic_vector(63 downto 0);
      dat_i : in std_logic_vector(63 downto 0);
      err_i : in std_logic;
      ack_i : in std_logic);
  end component;
 
  -----------------------------------------------------------------------------
  -- 
  -----------------------------------------------------------------------------
 
  signal clk : std_logic;
  signal areset_n : std_logic;
  signal enable : std_logic;
 
  signal writeFrameFull : std_logic;
  signal writeFrame : std_logic;
  signal writeFrameAbort : std_logic;
  signal writeContent : std_logic;
  signal writeContentData : std_logic_vector(31 downto 0);
 
  signal readFrameEmpty : std_logic;
  signal readFrame : std_logic;
  signal readFrameRestart : std_logic;
  signal readFrameAborted : std_logic;
  signal readContentEmpty : std_logic;
  signal readContent : std_logic;
  signal readContentEnd : std_logic;
  signal readContentData : std_logic_vector(31 downto 0);
 
  signal wbCyc : std_logic;
  signal wbStb : std_logic;
  signal wbWe : std_logic;
  signal wbAdr : std_logic_vector(30 downto 0);
  signal wbSel : std_logic_vector(7 downto 0);
  signal wbDatWrite : std_logic_vector(63 downto 0);
  signal wbDatRead : std_logic_vector(63 downto 0);
  signal wbAck : std_logic;
  signal wbErr : std_logic;
 
  signal outboundEmpty : std_logic;
  signal outboundWrite : std_logic;
  signal outboundMessage : TestPortMessagePacketBuffer;
  signal outboundAck : std_logic;
 
  signal inboundEmpty : std_logic;
  signal inboundWrite : std_logic;
  signal inboundMessage : TestPortMessagePacketBuffer;
  signal inboundAck : std_logic;
 
  signal wbMessageEmpty : std_logic;
  signal wbMessageWrite : std_logic;
  signal wbMessage : TestPortMessageWishbone;
  signal wbMessageAck : std_logic;
 
begin
 
  -----------------------------------------------------------------------------
  -- Clock generation.
  -----------------------------------------------------------------------------
  ClockGenerator: process
  begin
    clk <= '0';
    wait for 20 ns;
    clk <= '1';
    wait for 20 ns;
  end process;
 
 
  -----------------------------------------------------------------------------
  -- Serial port emulator.
  -----------------------------------------------------------------------------
  TestDriver: process
 
    -----------------------------------------------------------------------------
    -- Procedures to handle outbound and inbound packets.
    -----------------------------------------------------------------------------
    procedure OutboundFrame(constant frame : in RioFrame) is
    begin
      TestPortPacketBufferWrite(outboundWrite, outboundMessage, outboundAck,
                                frame, false);
    end procedure;
 
    procedure InboundFrame(constant frame : in RioFrame) is
    begin
      TestPortPacketBufferWrite(inboundWrite, inboundMessage, inboundAck,
                                frame, false);
    end procedure;
 
    ---------------------------------------------------------------------------
    -- Procedure to handle wishbone accesses.
    ---------------------------------------------------------------------------
    procedure SetSlaveAccess(constant writeAccess : in boolean;
                             constant addressIn : in std_logic_vector(30 downto 0);
                             constant byteSelect : in std_logic_vector(7 downto 0);
                             constant length : in natural range 1 to 32;
                             constant dataIn : in DoublewordArray(0 to 31);
                             constant latency : natural := 1) is
      variable address : std_logic_vector(ADDRESS_WIDTH_MAX-1 downto 0);
    begin
      address := x"00000000" & '0' & addressIn;
      for i in 0 to length-1 loop
        if (i = (length-1)) then
          TestPortWishboneWrite(wbMessageWrite, wbMessage, wbMessageAck,
                                writeAccess, address, byteSelect, dataIn(i), false, latency);
        else
          TestPortWishboneWrite(wbMessageWrite, wbMessage, wbMessageAck,
                                writeAccess, address, byteSelect, dataIn(i), true, latency);
          address := std_logic_vector(unsigned(address)+1);
        end if;
      end loop;
    end procedure;
 
    ---------------------------------------------------------------------------
    -- 
    ---------------------------------------------------------------------------
    function getReadSize(constant rdsize : in std_logic_vector(3 downto 0);
                         constant wdptr : in std_logic) return natural is
    begin
      case rdsize is
        when "0000" | "0001" | "0010" | "0011" =>
          return 1;
        when "0100" | "0110" =>
          return 1;
        when "0101" =>
          return 1;
        when "1000" =>
          return 1;
        when "0111" =>
          return 1;
        when "1001" =>
          return 1;
        when "1010" =>
          return 1;
        when "1011" =>
          if (wdptr = '0') then
            return 1;
          else
            return 2;
          end if;
        when "1100" =>
          if (wdptr = '0') then
            return 4;
          else
            return 8;
          end if;
        when "1101" =>
          if (wdptr = '0') then
            return 12;
          else
            return 16;
          end if;
        when "1110" =>
          if (wdptr = '0') then
            return 20;
          else
            return 24;
          end if;
        when "1111" =>
          if (wdptr = '0') then
            return 28;
          else
            return 32;
          end if;
        when others =>
          return 0;
      end case;
    end function;
 
    function getReadMask(constant rdsize : in std_logic_vector(3 downto 0);
                         constant wdptr : in std_logic) return std_logic_vector is
    begin
      case rdsize is
        when "0000" =>
          if (wdptr = '0') then
            return "10000000";
          else
            return "00001000";
          end if;
        when "0001" =>
          if (wdptr = '0') then
            return "01000000";
          else
            return "00000100";
          end if;
        when "0010" =>
          if (wdptr = '0') then
            return "00100000";
          else
            return "00000010";
          end if;
        when "0011" =>
          if (wdptr = '0') then
            return "00010000";
          else
            return "00000001";
          end if;
        when "0100" =>
          if (wdptr = '0') then
            return "11000000";
          else
            return "00001100";
          end if;
        when "0110" =>
          if (wdptr = '0') then
            return "00110000";
          else
            return "00000011";
          end if;
        when "0101" =>
          if (wdptr = '0') then
            return "11100000";
          else
            return "00000111";
          end if;
        when "1000" =>
          if (wdptr = '0') then
            return "11110000";
          else
            return "00001111";
          end if;
        when "0111" =>
          if (wdptr = '0') then
            return "11111000";
          else
            return "00011111";
          end if;
        when "1001" =>
          if (wdptr = '0') then
            return "11111100";
          else
            return "00111111";
          end if;
        when "1010" =>
          if (wdptr = '0') then
            return "11111110";
          else
            return "01111111";
          end if;
        when others =>
          return "11111111";
      end case;
    end function;
 
    ---------------------------------------------------------------------------
    -- Local variables.
    ---------------------------------------------------------------------------
    variable seed1 : positive := 1;
    variable seed2: positive := 1;
 
    variable rdsize : std_logic_vector(3 downto 0);
    variable wrsize : std_logic_vector(3 downto 0);
    variable wdptr : std_logic;
    variable maintData : DoubleWordArray(0 to 7);
    variable ioData : DoubleWordArray(0 to 31);
    variable frame : RioFrame;
 
  begin
    areset_n <= '0';
    enable <= '1';
 
    inboundWrite <= '0';
    outboundWrite <= '0';
    wbMessageWrite <= '0';
 
    writeFrameFull <= '0';
 
    wait until clk'event and clk = '1';
    wait until clk'event and clk = '1';
    areset_n <= '1';
    wait until clk'event and clk = '1';
    wait until clk'event and clk = '1';
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge");
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC1");
    PrintS("Description: Test maintenance requests.");
    PrintS("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 1:");
    PrintS("Action: Send maintenance read request for one word on even offset.");
    PrintS("Result: Check the accesses on the external configuration port.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC1-Step1");
    ---------------------------------------------------------------------------
 
    InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
                                sourceId=>x"dead", destId=>x"beef",
                                payload=>RioMaintenance(transaction=>"0000",
                                                        size=>"1000",
                                                        tid=>x"aa",
                                                        hopCount=>x"ff",
                                                        configOffset=>"000000000000000000000",
                                                        wdptr=>'0',
                                                        dataLength=>0,
                                                        data=>maintData)));
 
    maintData(0) := x"deadbeef00000000";
    OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                 tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
                                 sourceId=>x"beef", destId=>x"dead",
                                 payload=>RioMaintenance(transaction=>"0010",
                                                         size=>"0000",
                                                         tid=>x"aa",
                                                         hopCount=>x"ff",
                                                         configOffset=>"000000000000000000000",
                                                         wdptr=>'0',
                                                         dataLength=>1,
                                                         data=>maintData)));
 
    TestWait(inboundEmpty, '1', "inbound frame");
    TestWait(outboundEmpty, '1', "outbound frame");
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC2");
    PrintS("Description: Test request class packets.");
    PrintS("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 1:");
    PrintS("Action: Send request class NREAD packets for all sizes.");
    PrintS("Result: The Wishbone access should match the inbound packet.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC2-Step1");
    ---------------------------------------------------------------------------
    -- REMARK: Change the address and tid also...
    for i in 0 to 15 loop
      for j in 0 to 1 loop
        rdsize := std_logic_vector(to_unsigned(i, 4));
        if (j = 0) then
          wdptr := '0';
        else
          wdptr := '1';
        end if;
 
        ioData(0) := x"0001020304050607";
        ioData(1) := x"08090a0b0c0d0e0f";
        ioData(2) := x"1011121314151617";
        ioData(3) := x"18191a1b1c1d1e1f";
        ioData(4) := x"2021222324252627";
        ioData(5) := x"28292a2b2c2d2e2f";
        ioData(6) := x"3031323334353637";
        ioData(7) := x"38393a3b3c3d3e3f";
        ioData(8) := x"4041424344454647";
        ioData(9) := x"48494a4b4c4d4e4f";
        ioData(10) := x"5051525354555657";
        ioData(11) := x"58595a5b5c5d5e5f";
 
        InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                    tt=>"01", ftype=>FTYPE_REQUEST_CLASS,
                                    sourceId=>x"dead", destId=>x"beef",
                                    payload=>RioNread(rdsize=>rdsize,
                                                      tid=>x"aa",
                                                      address=>"00000000000000000000000000000",
                                                      wdptr=>wdptr,
                                                      xamsbs=>"00")));
 
        OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                     tt=>"01", ftype=>FTYPE_RESPONSE_CLASS,
                                     sourceId=>x"beef", destId=>x"dead",
                                     payload=>RioResponse(status=>"0000",
                                                          tid=>x"aa",
                                                          dataLength=>getReadSize(rdsize, wdptr),
                                                          data=>ioData)));
 
        SetSlaveAccess(false, "0000000000000000000000000000000",
                       getReadMask(rdsize, wdptr),
                       getReadSize(rdsize, wdptr),
                       ioData);
 
        TestWait(inboundEmpty, '1', "inbound frame");
        TestWait(outboundEmpty, '1', "outbound frame");
        TestWait(wbMessageEmpty, '1', "wishbone access");
      end loop;
    end loop;
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("TG_RioWbBridge-TC3");
    PrintS("Description: Test write class packets.");
    PrintS("Requirement: XXXXX");
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 1:");
    PrintS("Action: Send write class NWRITER packets for all sizes.");
    PrintS("Result: The Wishbone access should match the inbound packet and a ");
    PrintS("        response should be sent.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC3-Step1");
    ---------------------------------------------------------------------------
    -- REMARK: Change the address and tid also...
    -- REMARK: Not really all sizes, add sizes in between the fixed as well.
    for i in 0 to 15 loop
      for j in 0 to 1 loop
        wrsize := std_logic_vector(to_unsigned(i, 4));
        if (j = 0) then
          wdptr := '0';
        else
          wdptr := '1';
        end if;
 
        CreateRandomPayload(ioData, seed1, seed2);
 
        InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                    tt=>"01", ftype=>FTYPE_WRITE_CLASS,
                                    sourceId=>x"dead", destId=>x"beef",
                                    payload=>RioNwriteR(wrsize=>wrsize,
                                                        tid=>x"aa",
                                                        address=>"00000000000000000000000000000",
                                                        wdptr=>wdptr,
                                                        xamsbs=>"00",
                                                        dataLength=>getReadSize(wrsize, wdptr),
                                                        data=>ioData)));
 
        OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                     tt=>"01", ftype=>FTYPE_RESPONSE_CLASS,
                                     sourceId=>x"beef", destId=>x"dead",
                                     payload=>RioResponse(status=>"0000",
                                                          tid=>x"aa",
                                                          dataLength=>0,
                                                          data=>ioData)));
 
        SetSlaveAccess(true, "0000000000000000000000000000000",
                       getReadMask(wrsize, wdptr),
                       getReadSize(wrsize, wdptr),
                       ioData);
 
        TestWait(inboundEmpty, '1', "inbound frame");
        TestWait(outboundEmpty, '1', "outbound frame");
        TestWait(wbMessageEmpty, '1', "wishbone access");
      end loop;
    end loop;
 
    ---------------------------------------------------------------------------
    PrintS("-----------------------------------------------------------------");
    PrintS("Step 2:");
    PrintS("Action: Send write class NWRITE packets for all sizes.");
    PrintS("Result: The Wishbone access should match the inbound packet.");
    PrintS("-----------------------------------------------------------------");
    ---------------------------------------------------------------------------
    PrintR("TG_RioWbBridge-TC3-Step2");
    ---------------------------------------------------------------------------
    -- REMARK: Change the address and tid also...
    for i in 0 to 15 loop
      for j in 0 to 1 loop
        wrsize := std_logic_vector(to_unsigned(i, 4));
        if (j = 0) then
          wdptr := '0';
        else
          wdptr:= '1';
        end if;
 
        CreateRandomPayload(ioData, seed1, seed2);
 
        InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
                                    tt=>"01", ftype=>FTYPE_WRITE_CLASS,
                                    sourceId=>x"dead", destId=>x"beef",
                                    payload=>RioNwrite(wrsize=>wrsize,
                                                       address=>"00000000000000000000000000000",
                                                       wdptr=>wdptr,
                                                       xamsbs=>"00",
                                                       dataLength=>getReadSize(wrsize, wdptr),
                                                       data=>ioData)));
 
        SetSlaveAccess(true, "0000000000000000000000000000000",
                       getReadMask(wrsize, wdptr),
                       getReadSize(wrsize, wdptr),
                       ioData);
 
        TestWait(inboundEmpty, '1', "inbound frame");
        TestWait(outboundEmpty, '1', "outbound frame");
        TestWait(wbMessageEmpty, '1', "wishbone access");
      end loop;
    end loop;
 
    ---------------------------------------------------------------------------
    -- Test completed.
    ---------------------------------------------------------------------------
 
    TestEnd;
  end process;
 
  -----------------------------------------------------------------------------
  -- Instantiate the test object.
  -----------------------------------------------------------------------------
  TestObject: RioWbBridge
    generic map(
      EXTENDED_ADDRESS=>0,
      DEVICE_IDENTITY=>x"dead",
      DEVICE_VENDOR_IDENTITY=>x"beef",
      DEVICE_REV=>x"c0debabe",
      ASSY_IDENTITY=>x"1111",
      ASSY_VENDOR_IDENTITY=>x"2222",
      ASSY_REV=>x"3333")
    port map(
      clk=>clk,
      areset_n=>areset_n,
      enable=>enable,
      readFrameEmpty_i=>readFrameEmpty,
      readFrame_o=>readFrame,
      readContent_o=>readContent,
      readContentEnd_i=>readContentEnd,
      readContentData_i=>readContentData,
      writeFrameFull_i=>writeFrameFull,
      writeFrame_o=>writeFrame,
      writeFrameAbort_o=>writeFrameAbort,
      writeContent_o=>writeContent,
      writeContentData_o=>writeContentData,
      cyc_o=>wbCyc,
      stb_o=>wbStb,
      we_o=>wbWe,
      adr_o=>wbAdr,
      sel_o=>wbSel,
      dat_o=>wbDatWrite,
      dat_i=>wbDatRead,
      err_i=>wbErr,
      ack_i=>wbAck);
 
  -----------------------------------------------------------------------------
  -- Instantiate the test ports.
  -----------------------------------------------------------------------------
 
  TestPortPacketBufferInst: TestPortPacketBuffer
    generic map(READ_CONTENT_END_DATA_VALID=>false)
    port map(
      clk=>clk, areset_n=>areset_n,
      readEmpty_o=>inboundEmpty,
      readWrite_i=>inboundWrite,
      readMessage_i=>inboundMessage,
      readAck_o=>inboundAck,
      writeEmpty_o=>outboundEmpty,
      writeWrite_i=>outboundWrite,
      writeMessage_i=>outboundMessage,
      writeAck_o=>outboundAck,
      readFrameEmpty_o=>readFrameEmpty,
      readFrame_i=>readFrame,
      readFrameRestart_i=>'0',
      readFrameAborted_o=>readFrameAborted,
      readWindowEmpty_o=>open,
      readWindowReset_i=>'0',
      readWindowNext_i=>readFrame,
      readContentEmpty_o=>readContentEmpty,
      readContent_i=>readContent,
      readContentEnd_o=>readContentEnd,
      readContentData_o=>readContentData,
      writeFrame_i=>writeFrame,
      writeFrameAbort_i=>writeFrameAbort,
      writeContent_i=>writeContent,
      writeContentData_i=>writeContentData);
 
  TestPortWishboneInst: TestPortWishbone
    port map(
      clk=>clk,
      areset_n=>areset_n,
      messageEmpty_o=>wbMessageEmpty,
      messageWrite_i=>wbMessageWrite,
      message_i=>wbMessage,
      messageAck_o=>wbMessageAck,
      cyc_i=>wbCyc,
      stb_i=>wbStb,
      we_i=>wbWe,
      adr_i=>wbAdr,
      sel_i=>wbSel,
      dat_i=>wbDatWrite,
      dat_o=>wbDatRead,
      err_o=>wbErr,
      ack_o=>wbAck);
 
end architecture;

Line No.	Rev	Author	Line
1	42	magro732	`-------------------------------------------------------------------------------`
2			`--`
3			`-- RapidIO IP Library Core`
4			`--`
5			`-- This file is part of the RapidIO IP library project`
6			`-- http://www.opencores.org/cores/rio/`
7			`--`
8			`-- Description`
9			`-- Contains automatic test code to verify a RioWbBridge implementation.`
10			`--`
11			`-- To Do:`
12	47	magro732	`-- - Add testcases to NWRITE to cover all possible access lengths, not just the`
13			`-- maximum as presently.`
14	42	magro732	`--`
15			`-- Author(s):`
16			`-- - Magnus Rosenius, magro732@opencores.org`
17			`--`
18			`-------------------------------------------------------------------------------`
19			`--`
20			`-- Copyright (C) 2013 Authors and OPENCORES.ORG`
21			`--`
22			`-- This source file may be used and distributed without`
23			`-- restriction provided that this copyright statement is not`
24			`-- removed from the file and that any derivative work contains`
25			`-- the original copyright notice and the associated disclaimer.`
26			`--`
27			`-- This source file is free software; you can redistribute it`
28			`-- and/or modify it under the terms of the GNU Lesser General`
29			`-- Public License as published by the Free Software Foundation;`
30			`-- either version 2.1 of the License, or (at your option) any`
31			`-- later version.`
32			`--`
33			`-- This source is distributed in the hope that it will be`
34			`-- useful, but WITHOUT ANY WARRANTY; without even the implied`
35			`-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
36			`-- PURPOSE. See the GNU Lesser General Public License for more`
37			`-- details.`
38			`--`
39			`-- You should have received a copy of the GNU Lesser General`
40			`-- Public License along with this source; if not, download it`
41			`-- from http://www.opencores.org/lgpl.shtml`
42			`--`
43			`-------------------------------------------------------------------------------`
44
45
46			`-------------------------------------------------------------------------------`
47			`-- TestRioWbBridge.`
48			`-------------------------------------------------------------------------------`
49
50			`library ieee;`
51			`use ieee.std_logic_1164.all;`
52			`use ieee.numeric_std.all;`
53			`use ieee.math_real.all;`
54			`library std;`
55			`use std.textio.all;`
56			`use work.rio_common.all;`
57			`use work.TestPortPackage.all;`
58
59
60			`-------------------------------------------------------------------------------`
61			`-- Entity for TestRioWbBridge.`
62			`-------------------------------------------------------------------------------`
63			`entity TestRioWbBridge is`
64			`end entity;`
65
66
67			`-------------------------------------------------------------------------------`
68			`-- Architecture for TestRioWbBridge.`
69			`-------------------------------------------------------------------------------`
70			`architecture TestRioWbBridgeImpl of TestRioWbBridge is`
71
72			`component RioWbBridge is`
73			`generic(`
74			`EXTENDED_ADDRESS : natural range 0 to 2 := 0;`
75			`DEVICE_IDENTITY : std_logic_vector(15 downto 0);`
76			`DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);`
77			`DEVICE_REV : std_logic_vector(31 downto 0);`
78			`ASSY_IDENTITY : std_logic_vector(15 downto 0);`
79			`ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);`
80			`ASSY_REV : std_logic_vector(15 downto 0));`
81			`port(`
82			`clk : in std_logic;`
83			`areset_n : in std_logic;`
84	44	magro732	`enable : in std_logic;`
85	42	magro732
86			`readFrameEmpty_i : in std_logic;`
87			`readFrame_o : out std_logic;`
88			`readContent_o : out std_logic;`
89			`readContentEnd_i : in std_logic;`
90			`readContentData_i : in std_logic_vector(31 downto 0);`
91			`writeFrameFull_i : in std_logic;`
92			`writeFrame_o : out std_logic;`
93			`writeFrameAbort_o : out std_logic;`
94			`writeContent_o : out std_logic;`
95			`writeContentData_o : out std_logic_vector(31 downto 0);`
96
97			`cyc_o : out std_logic;`
98			`stb_o : out std_logic;`
99			`we_o : out std_logic;`
100			`adr_o : out std_logic_vector(16*EXTENDED_ADDRESS+30 downto 0);`
101			`sel_o : out std_logic_vector(7 downto 0);`
102			`dat_o : out std_logic_vector(63 downto 0);`
103			`dat_i : in std_logic_vector(63 downto 0);`
104			`err_i : in std_logic;`
105			`ack_i : in std_logic);`
106			`end component;`
107
108			`-----------------------------------------------------------------------------`
109			`--`
110			`-----------------------------------------------------------------------------`
111
112			`signal clk : std_logic;`
113			`signal areset_n : std_logic;`
114			`signal enable : std_logic;`
115
116			`signal writeFrameFull : std_logic;`
117			`signal writeFrame : std_logic;`
118			`signal writeFrameAbort : std_logic;`
119			`signal writeContent : std_logic;`
120			`signal writeContentData : std_logic_vector(31 downto 0);`
121
122			`signal readFrameEmpty : std_logic;`
123			`signal readFrame : std_logic;`
124			`signal readFrameRestart : std_logic;`
125			`signal readFrameAborted : std_logic;`
126			`signal readContentEmpty : std_logic;`
127			`signal readContent : std_logic;`
128			`signal readContentEnd : std_logic;`
129			`signal readContentData : std_logic_vector(31 downto 0);`
130
131			`signal wbCyc : std_logic;`
132			`signal wbStb : std_logic;`
133			`signal wbWe : std_logic;`
134			`signal wbAdr : std_logic_vector(30 downto 0);`
135			`signal wbSel : std_logic_vector(7 downto 0);`
136			`signal wbDatWrite : std_logic_vector(63 downto 0);`
137			`signal wbDatRead : std_logic_vector(63 downto 0);`
138			`signal wbAck : std_logic;`
139			`signal wbErr : std_logic;`
140
141			`signal outboundEmpty : std_logic;`
142			`signal outboundWrite : std_logic;`
143			`signal outboundMessage : TestPortMessagePacketBuffer;`
144			`signal outboundAck : std_logic;`
145
146			`signal inboundEmpty : std_logic;`
147			`signal inboundWrite : std_logic;`
148			`signal inboundMessage : TestPortMessagePacketBuffer;`
149			`signal inboundAck : std_logic;`
150
151			`signal wbMessageEmpty : std_logic;`
152			`signal wbMessageWrite : std_logic;`
153			`signal wbMessage : TestPortMessageWishbone;`
154			`signal wbMessageAck : std_logic;`
155
156			`begin`
157
158			`-----------------------------------------------------------------------------`
159			`-- Clock generation.`
160			`-----------------------------------------------------------------------------`
161			`ClockGenerator: process`
162			`begin`
163			`clk <= '0';`
164			`wait for 20 ns;`
165			`clk <= '1';`
166			`wait for 20 ns;`
167			`end process;`
168
169
170			`-----------------------------------------------------------------------------`
171			`-- Serial port emulator.`
172			`-----------------------------------------------------------------------------`
173			`TestDriver: process`
174
175			`-----------------------------------------------------------------------------`
176			`-- Procedures to handle outbound and inbound packets.`
177			`-----------------------------------------------------------------------------`
178			`procedure OutboundFrame(constant frame : in RioFrame) is`
179			`begin`
180			`TestPortPacketBufferWrite(outboundWrite, outboundMessage, outboundAck,`
181			`frame, false);`
182			`end procedure;`
183
184			`procedure InboundFrame(constant frame : in RioFrame) is`
185			`begin`
186			`TestPortPacketBufferWrite(inboundWrite, inboundMessage, inboundAck,`
187			`frame, false);`
188			`end procedure;`
189
190			`---------------------------------------------------------------------------`
191			`-- Procedure to handle wishbone accesses.`
192			`---------------------------------------------------------------------------`
193			`procedure SetSlaveAccess(constant writeAccess : in boolean;`
194	47	magro732	`constant addressIn : in std_logic_vector(30 downto 0);`
195	42	magro732	`constant byteSelect : in std_logic_vector(7 downto 0);`
196	47	magro732	`constant length : in natural range 1 to 32;`
197			`constant dataIn : in DoublewordArray(0 to 31);`
198	44	magro732	`constant latency : natural := 1) is`
199	47	magro732	`variable address : std_logic_vector(ADDRESS_WIDTH_MAX-1 downto 0);`
200	42	magro732	`begin`
201	47	magro732	`address := x"00000000" & '0' & addressIn;`
202			`for i in 0 to length-1 loop`
203			`if (i = (length-1)) then`
204			`TestPortWishboneWrite(wbMessageWrite, wbMessage, wbMessageAck,`
205			`writeAccess, address, byteSelect, dataIn(i), false, latency);`
206			`else`
207			`TestPortWishboneWrite(wbMessageWrite, wbMessage, wbMessageAck,`
208			`writeAccess, address, byteSelect, dataIn(i), true, latency);`
209			`address := std_logic_vector(unsigned(address)+1);`
210			`end if;`
211			`end loop;`
212	42	magro732	`end procedure;`
213	44	magro732
214			`---------------------------------------------------------------------------`
215			`--`
216			`---------------------------------------------------------------------------`
217			`function getReadSize(constant rdsize : in std_logic_vector(3 downto 0);`
218			`constant wdptr : in std_logic) return natural is`
219			`begin`
220			`case rdsize is`
221			`when "0000" \| "0001" \| "0010" \| "0011" =>`
222			`return 1;`
223			`when "0100" \| "0110" =>`
224			`return 1;`
225			`when "0101" =>`
226			`return 1;`
227			`when "1000" =>`
228			`return 1;`
229			`when "0111" =>`
230			`return 1;`
231			`when "1001" =>`
232			`return 1;`
233			`when "1010" =>`
234			`return 1;`
235			`when "1011" =>`
236			`if (wdptr = '0') then`
237			`return 1;`
238			`else`
239			`return 2;`
240			`end if;`
241			`when "1100" =>`
242			`if (wdptr = '0') then`
243			`return 4;`
244			`else`
245			`return 8;`
246			`end if;`
247			`when "1101" =>`
248			`if (wdptr = '0') then`
249			`return 12;`
250			`else`
251			`return 16;`
252			`end if;`
253			`when "1110" =>`
254			`if (wdptr = '0') then`
255			`return 20;`
256			`else`
257			`return 24;`
258			`end if;`
259			`when "1111" =>`
260			`if (wdptr = '0') then`
261			`return 28;`
262			`else`
263			`return 32;`
264			`end if;`
265			`when others =>`
266			`return 0;`
267			`end case;`
268			`end function;`
269	42	magro732
270	44	magro732	`function getReadMask(constant rdsize : in std_logic_vector(3 downto 0);`
271			`constant wdptr : in std_logic) return std_logic_vector is`
272			`begin`
273			`case rdsize is`
274			`when "0000" =>`
275			`if (wdptr = '0') then`
276			`return "10000000";`
277			`else`
278			`return "00001000";`
279			`end if;`
280			`when "0001" =>`
281			`if (wdptr = '0') then`
282			`return "01000000";`
283			`else`
284			`return "00000100";`
285			`end if;`
286			`when "0010" =>`
287			`if (wdptr = '0') then`
288			`return "00100000";`
289			`else`
290			`return "00000010";`
291			`end if;`
292			`when "0011" =>`
293			`if (wdptr = '0') then`
294			`return "00010000";`
295			`else`
296			`return "00000001";`
297			`end if;`
298			`when "0100" =>`
299			`if (wdptr = '0') then`
300			`return "11000000";`
301			`else`
302			`return "00001100";`
303			`end if;`
304			`when "0110" =>`
305			`if (wdptr = '0') then`
306			`return "00110000";`
307			`else`
308			`return "00000011";`
309			`end if;`
310			`when "0101" =>`
311			`if (wdptr = '0') then`
312			`return "11100000";`
313			`else`
314			`return "00000111";`
315			`end if;`
316			`when "1000" =>`
317			`if (wdptr = '0') then`
318			`return "11110000";`
319			`else`
320			`return "00001111";`
321			`end if;`
322			`when "0111" =>`
323			`if (wdptr = '0') then`
324			`return "11111000";`
325			`else`
326			`return "00011111";`
327			`end if;`
328			`when "1001" =>`
329			`if (wdptr = '0') then`
330			`return "11111100";`
331			`else`
332			`return "00111111";`
333			`end if;`
334			`when "1010" =>`
335			`if (wdptr = '0') then`
336			`return "11111110";`
337			`else`
338			`return "01111111";`
339			`end if;`
340			`when others =>`
341			`return "11111111";`
342			`end case;`
343			`end function;`
344	42	magro732
345			`---------------------------------------------------------------------------`
346	45	magro732	`-- Local variables.`
347	42	magro732	`---------------------------------------------------------------------------`
348			`variable seed1 : positive := 1;`
349			`variable seed2: positive := 1;`
350
351	44	magro732	`variable rdsize : std_logic_vector(3 downto 0);`
352	45	magro732	`variable wrsize : std_logic_vector(3 downto 0);`
353	44	magro732	`variable wdptr : std_logic;`
354	45	magro732	`variable maintData : DoubleWordArray(0 to 7);`
355	42	magro732	`variable ioData : DoubleWordArray(0 to 31);`
356			`variable frame : RioFrame;`
357
358			`begin`
359			`areset_n <= '0';`
360	44	magro732	`enable <= '1';`
361	42	magro732
362	44	magro732	`inboundWrite <= '0';`
363			`outboundWrite <= '0';`
364			`wbMessageWrite <= '0';`
365
366	42	magro732	`writeFrameFull <= '0';`
367
368			`wait until clk'event and clk = '1';`
369			`wait until clk'event and clk = '1';`
370			`areset_n <= '1';`
371			`wait until clk'event and clk = '1';`
372			`wait until clk'event and clk = '1';`
373
374			`---------------------------------------------------------------------------`
375			`PrintS("-----------------------------------------------------------------");`
376	44	magro732	`PrintS("TG_RioWbBridge");`
377	42	magro732	`PrintS("-----------------------------------------------------------------");`
378	44	magro732	`PrintS("TG_RioWbBridge-TC1");`
379			`PrintS("Description: Test maintenance requests.");`
380	42	magro732	`PrintS("Requirement: XXXXX");`
381			`PrintS("-----------------------------------------------------------------");`
382			`PrintS("Step 1:");`
383			`PrintS("Action: Send maintenance read request for one word on even offset.");`
384			`PrintS("Result: Check the accesses on the external configuration port.");`
385			`PrintS("-----------------------------------------------------------------");`
386			`---------------------------------------------------------------------------`
387	44	magro732	`PrintR("TG_RioWbBridge-TC1-Step1");`
388	42	magro732	`---------------------------------------------------------------------------`
389	45	magro732
390			`InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",`
391			`tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,`
392			`sourceId=>x"dead", destId=>x"beef",`
393			`payload=>RioMaintenance(transaction=>"0000",`
394			`size=>"1000",`
395			`tid=>x"aa",`
396			`hopCount=>x"ff",`
397			`configOffset=>"000000000000000000000",`
398			`wdptr=>'0',`
399			`dataLength=>0,`
400			`data=>maintData)));`
401
402			`maintData(0) := x"deadbeef00000000";`
403			`OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",`
404			`tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,`
405			`sourceId=>x"beef", destId=>x"dead",`
406			`payload=>RioMaintenance(transaction=>"0010",`
407			`size=>"0000",`
408			`tid=>x"aa",`
409			`hopCount=>x"ff",`
410			`configOffset=>"000000000000000000000",`
411			`wdptr=>'0',`
412			`dataLength=>1,`
413			`data=>maintData)));`
414	42	magro732
415	45	magro732	`TestWait(inboundEmpty, '1', "inbound frame");`
416			`TestWait(outboundEmpty, '1', "outbound frame");`
417
418	44	magro732	`---------------------------------------------------------------------------`
419			`PrintS("-----------------------------------------------------------------");`
420			`PrintS("TG_RioWbBridge-TC2");`
421			`PrintS("Description: Test request class packets.");`
422			`PrintS("Requirement: XXXXX");`
423			`PrintS("-----------------------------------------------------------------");`
424			`PrintS("Step 1:");`
425	45	magro732	`PrintS("Action: Send request class NREAD packets for all sizes.");`
426			`PrintS("Result: The Wishbone access should match the inbound packet.");`
427	44	magro732	`PrintS("-----------------------------------------------------------------");`
428			`---------------------------------------------------------------------------`
429			`PrintR("TG_RioWbBridge-TC2-Step1");`
430			`---------------------------------------------------------------------------`
431	45	magro732	`-- REMARK: Change the address and tid also...`
432	44	magro732	`for i in 0 to 15 loop`
433			`for j in 0 to 1 loop`
434			`rdsize := std_logic_vector(to_unsigned(i, 4));`
435			`if (j = 0) then`
436			`wdptr := '0';`
437			`else`
438	47	magro732	`wdptr := '1';`
439	44	magro732	`end if;`
440
441	48	magro732	`ioData(0) := x"0001020304050607";`
442			`ioData(1) := x"08090a0b0c0d0e0f";`
443			`ioData(2) := x"1011121314151617";`
444			`ioData(3) := x"18191a1b1c1d1e1f";`
445			`ioData(4) := x"2021222324252627";`
446			`ioData(5) := x"28292a2b2c2d2e2f";`
447			`ioData(6) := x"3031323334353637";`
448			`ioData(7) := x"38393a3b3c3d3e3f";`
449			`ioData(8) := x"4041424344454647";`
450			`ioData(9) := x"48494a4b4c4d4e4f";`
451			`ioData(10) := x"5051525354555657";`
452			`ioData(11) := x"58595a5b5c5d5e5f";`
453	42	magro732
454	44	magro732	`InboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",`
455			`tt=>"01", ftype=>FTYPE_REQUEST_CLASS,`
456			`sourceId=>x"dead", destId=>x"beef",`
457			`payload=>RioNread(rdsize=>rdsize,`
458	42	magro732	`tid=>x"aa",`
459	44	magro732	`address=>"00000000000000000000000000000",`
460			`wdptr=>wdptr,`
461			`xamsbs=>"00")));`
462	42	magro732
463	44	magro732	`OutboundFrame(RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",`
464			`tt=>"01", ftype=>FTYPE_RESPONSE_CLASS,`
465			`sourceId=>x"beef", destId=>x"dead",`
466			`payload=>RioResponse(status=>"0000",`
467			`tid=>x"aa",`
468			`dataLength=>getReadSize(rdsize, wdptr),`
469			`data=>ioData)));`
470	42	magro732
471	44	magro732	`SetSlaveAccess(false, "0000000000000000000000000000000",`
472			`getReadMask(rdsize, wdptr),`
473			`getReadSize(rdsize, wdptr),`
474			`ioData);`
475
476			`TestWait(inboundEmpty, '1', "inbound frame");`
477			`TestWait(outboundEmpty, '1', "outbound frame");`
478			`TestWait(wbMessageEmpty, '1', "wishbone access");`
479			`end loop;`
480			`end loop;`
481	42	magro732
482			`---------------------------------------------------------------------------`
483	45	magro732	`PrintS("-----------------------------------------------------------------");`
484			`PrintS("TG_RioWbBridge-TC3");`
485			`PrintS("Description: Test write class packets.");`
486			`PrintS("Requirement: XXXXX");`
487			`PrintS("-----------------------------------------------------------------");`
488			`PrintS("Step 1:");`
489			`PrintS("Action: Send write class NWRITER packets for all sizes.");`
490			`PrintS("Result: The Wishbone access should match the inbound packet and a ");`
491			`PrintS(" response should be sent.");`
492			`PrintS("-----------------------------------------------------------------");`
493			`---------------------------------------------------------------------------`
494			`PrintR("TG_RioWbBridge-TC3-Step1");`
495			`---------------------------------------------------------------------------`
496			`-- REMARK: Change the address and tid also...`
497	47	magro732	`-- REMARK: Not really all sizes, add sizes in between the fixed as well.`
498	45	magro732	`for i in 0 to 15 loop`
499			`for j in 0 to 1 loop`
500			`wrsize := std_logic_vector(to_unsigned(i, 4));`

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