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1 2 magro732 
-------------------------------------------------------------------------------
2 
--
3 
-- RapidIO IP Library Core
4 
--
5 
-- This file is part of the RapidIO IP library project
6 
-- http://www.opencores.org/cores/rio/
7 
--
8 
-- Description
9 
-- Contains commonly used types, functions, procedures and entities used in
10 
-- the RapidIO IP library project.
11 
--
12 
-- To Do:
13 
-- -
14 
--
15 
-- Author(s):
16 
-- - Magnus Rosenius, magro732@opencores.org
17 
--
18 
-------------------------------------------------------------------------------
19 
--
20 
-- Copyright (C) 2013 Authors and OPENCORES.ORG
21 
--
22 
-- This source file may be used and distributed without
23 
-- restriction provided that this copyright statement is not
24 
-- removed from the file and that any derivative work contains
25 
-- the original copyright notice and the associated disclaimer.
26 
--
27 
-- This source file is free software; you can redistribute it
28 
-- and/or modify it under the terms of the GNU Lesser General
29 
-- Public License as published by the Free Software Foundation;
30 
-- either version 2.1 of the License, or (at your option) any
31 
-- later version.
32 
--
33 
-- This source is distributed in the hope that it will be
34 
-- useful, but WITHOUT ANY WARRANTY; without even the implied
35 
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
36 
-- PURPOSE. See the GNU Lesser General Public License for more
37 
-- details.
38 
--
39 
-- You should have received a copy of the GNU Lesser General
40 
-- Public License along with this source; if not, download it
41 
-- from http://www.opencores.org/lgpl.shtml
42 
--
43 
-------------------------------------------------------------------------------
44 
 
45 
 
46 
-------------------------------------------------------------------------------
47 
-- RioCommon library.
48 
-------------------------------------------------------------------------------
49 
library ieee;
50 
use ieee.std_logic_1164.all;
51 
use ieee.numeric_std.all;
52 
use ieee.math_real.all;
53 
use std.textio.all;
54 
 
55 
 
56 
-------------------------------------------------------------------------------
57 
-- RioCommon package description.
58 
-------------------------------------------------------------------------------
59 
package rio_common is
60 46 magro732 
 
61 2 magro732 
  -----------------------------------------------------------------------------
62 46 magro732 
  -- Primitive memory component declarations.
63 
  -----------------------------------------------------------------------------
64 
 
65 
  component MemorySimpleDualPort
66 
    generic(
67 
      ADDRESS_WIDTH : natural := 1;
68 
      DATA_WIDTH : natural := 1);
69 
    port(
70 
      clkA_i : in std_logic;
71 
      enableA_i : in std_logic;
72 
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
73 
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
74 
 
75 
      clkB_i : in std_logic;
76 
      enableB_i : in std_logic;
77 
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
78 
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
79 
  end component;
80 
 
81 
  component MemoryDualPort is
82 
    generic(
83 
      ADDRESS_WIDTH : natural := 1;
84 
      DATA_WIDTH : natural := 1);
85 
    port(
86 
      clkA_i : in std_logic;
87 
      enableA_i : in std_logic;
88 
      writeEnableA_i : in std_logic;
89 
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
90 
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
91 
      dataA_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
92 
 
93 
      clkB_i : in std_logic;
94 
      enableB_i : in std_logic;
95 
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
96 
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
97 
  end component;
98 
 
99 
  -----------------------------------------------------------------------------
100 
  -- Logical layer component declarations.
101 
  -----------------------------------------------------------------------------
102 
 
103 
  component RioLogicalCommon is
104 
    generic(
105 
      PORTS : natural);
106 
    port(
107 
      clk : in std_logic;
108 
      areset_n : in std_logic;
109 
      enable : in std_logic;
110 
 
111 
      readFrameEmpty_i : in std_logic;
112 
      readFrame_o : out std_logic;
113 
      readContent_o : out std_logic;
114 
      readContentEnd_i : in std_logic;
115 
      readContentData_i : in std_logic_vector(31 downto 0);
116 
 
117 
      writeFrameFull_i : in std_logic;
118 
      writeFrame_o : out std_logic;
119 
      writeFrameAbort_o : out std_logic;
120 
      writeContent_o : out std_logic;
121 
      writeContentData_o : out std_logic_vector(31 downto 0);
122 
 
123 
      inboundCyc_o : out std_logic;
124 
      inboundStb_o : out std_logic;
125 
      inboundAdr_o : out std_logic_vector(7 downto 0);
126 
      inboundDat_o : out std_logic_vector(31 downto 0);
127 
      inboundAck_i : in std_logic;
128 
 
129 
      outboundCyc_i : in std_logic_vector(PORTS-1 downto 0);
130 
      outboundStb_i : in std_logic_vector(PORTS-1 downto 0);
131 
      outboundDat_i : in std_logic_vector(32*PORTS-1 downto 0);
132 
      outboundAck_o : out std_logic_vector(PORTS-1 downto 0));
133 
  end component;
134 
 
135 
  component RioLogicalMaintenance is
136 
    port(
137 
      clk : in std_logic;
138 
      areset_n : in std_logic;
139 
      enable : in std_logic;
140 
 
141 
      readRequestReady_i : in std_logic;
142 
      writeRequestReady_i : in std_logic;
143 47 magro732 
      size_i : in std_logic_vector(3 downto 0);
144 46 magro732 
      offset_i : in std_logic_vector(20 downto 0);
145 
      wdptr_i : in std_logic;
146 47 magro732 
      payloadLength_i : in std_logic_vector(2 downto 0);
147 
      payloadIndex_o : out std_logic_vector(2 downto 0);
148 
      payload_i : in std_logic_vector(63 downto 0);
149 46 magro732 
      done_o : out std_logic;
150 
 
151 
      readResponseReady_o : out std_logic;
152 
      writeResponseReady_o : out std_logic;
153 47 magro732 
      status_o : out std_logic_vector(3 downto 0);
154 
      payloadLength_o : out std_logic_vector(2 downto 0);
155 
      payloadIndex_i : in std_logic_vector(2 downto 0);
156 
      payload_o : out std_logic_vector(63 downto 0);
157 46 magro732 
      done_i : in std_logic;
158 
 
159 
      configStb_o : out std_logic;
160 
      configWe_o : out std_logic;
161 
      configAdr_o : out std_logic_vector(21 downto 0);
162 
      configDat_o : out std_logic_vector(31 downto 0);
163 
      configDat_i : in std_logic_vector(31 downto 0);
164 
      configAck_i : in std_logic);
165 
  end component;
166 
 
167 
  component MaintenanceInbound is
168 
    port(
169 
      clk : in std_logic;
170 
      areset_n : in std_logic;
171 
      enable : in std_logic;
172 
 
173 
      readRequestReady_o : out std_logic;
174 
      writeRequestReady_o : out std_logic;
175 
      readResponseReady_o : out std_logic;
176 
      writeResponseReady_o : out std_logic;
177 
      portWriteReady_o : out std_logic;
178 
      vc_o : out std_logic;
179 
      crf_o : out std_logic;
180 
      prio_o : out std_logic_vector(1 downto 0);
181 
      tt_o : out std_logic_vector(1 downto 0);
182 
      dstid_o : out std_logic_vector(31 downto 0);
183 
      srcid_o : out std_logic_vector(31 downto 0);
184 47 magro732 
      size_o : out std_logic_vector(3 downto 0);
185 
      status_o : out std_logic_vector(3 downto 0);
186 46 magro732 
      tid_o : out std_logic_vector(7 downto 0);
187 
      hop_o : out std_logic_vector(7 downto 0);
188 
      offset_o : out std_logic_vector(20 downto 0);
189 
      wdptr_o : out std_logic;
190 47 magro732 
      payloadLength_o : out std_logic_vector(2 downto 0);
191 
      payloadIndex_i : in std_logic_vector(2 downto 0);
192 
      payload_o : out std_logic_vector(63 downto 0);
193 46 magro732 
      done_i : in std_logic;
194 
 
195 
      inboundCyc_i : in std_logic;
196 
      inboundStb_i : in std_logic;
197 
      inboundAdr_i : in std_logic_vector(7 downto 0);
198 
      inboundDat_i : in std_logic_vector(31 downto 0);
199 
      inboundAck_o : out std_logic);
200 
  end component;
201 
 
202 
  component MaintenanceOutbound is
203 
    port(
204 
      clk : in std_logic;
205 
      areset_n : in std_logic;
206 
      enable : in std_logic;
207 
 
208 
      readRequestReady_i : in std_logic;
209 
      writeRequestReady_i : in std_logic;
210 
      readResponseReady_i : in std_logic;
211 
      writeResponseReady_i : in std_logic;
212 
      portWriteReady_i : in std_logic;
213 
      vc_i : in std_logic;
214 
      crf_i : in std_logic;
215 
      prio_i : in std_logic_vector(1 downto 0);
216 
      tt_i : in std_logic_vector(1 downto 0);
217 
      dstid_i : in std_logic_vector(31 downto 0);
218 
      srcid_i : in std_logic_vector(31 downto 0);
219 47 magro732 
      size_i : in std_logic_vector(3 downto 0);
220 46 magro732 
      status_i : in std_logic_vector(3 downto 0);
221 
      tid_i : in std_logic_vector(7 downto 0);
222 
      hop_i : in std_logic_vector(7 downto 0);
223 
      offset_i : in std_logic_vector(20 downto 0);
224 
      wdptr_i : in std_logic;
225 47 magro732 
      payloadLength_i : in std_logic_vector(2 downto 0);
226 
      payloadIndex_o : out std_logic_vector(2 downto 0);
227 
      payload_i : in std_logic_vector(63 downto 0);
228 46 magro732 
      done_o : out std_logic;
229 
 
230 
      outboundCyc_o : out std_logic;
231 
      outboundStb_o : out std_logic;
232 
      outboundDat_o : out std_logic_vector(31 downto 0);
233 
      outboundAck_i : in std_logic);
234 
  end component;
235 
 
236 
  component RioPacketBuffer is
237 
    generic(
238 
      SIZE_ADDRESS_WIDTH : natural := 6;
239 
      CONTENT_ADDRESS_WIDTH : natural := 8);
240 
    port(
241 
      clk : in std_logic;
242 
      areset_n : in std_logic;
243 
 
244 
      inboundWriteFrameFull_o : out std_logic;
245 
      inboundWriteFrame_i : in std_logic;
246 
      inboundWriteFrameAbort_i : in std_logic;
247 
      inboundWriteContent_i : in std_logic;
248 
      inboundWriteContentData_i : in std_logic_vector(31 downto 0);
249 
      inboundReadFrameEmpty_o : out std_logic;
250 
      inboundReadFrame_i : in std_logic;
251 
      inboundReadFrameRestart_i : in std_logic;
252 
      inboundReadFrameAborted_o : out std_logic;
253 
      inboundReadContentEmpty_o : out std_logic;
254 
      inboundReadContent_i : in std_logic;
255 
      inboundReadContentEnd_o : out std_logic;
256 
      inboundReadContentData_o : out std_logic_vector(31 downto 0);
257 
 
258 
      outboundWriteFrameFull_o : out std_logic;
259 
      outboundWriteFrame_i : in std_logic;
260 
      outboundWriteFrameAbort_i : in std_logic;
261 
      outboundWriteContent_i : in std_logic;
262 
      outboundWriteContentData_i : in std_logic_vector(31 downto 0);
263 
      outboundReadFrameEmpty_o : out std_logic;
264 
      outboundReadFrame_i : in std_logic;
265 
      outboundReadFrameRestart_i : in std_logic;
266 
      outboundReadFrameAborted_o : out std_logic;
267 
      outboundReadContentEmpty_o : out std_logic;
268 
      outboundReadContent_i : in std_logic;
269 
      outboundReadContentEnd_o : out std_logic;
270 
      outboundReadContentData_o : out std_logic_vector(31 downto 0));
271 
  end component;
272 
 
273 
  -----------------------------------------------------------------------------
274 2 magro732 
  -- Commonly used types.
275 
  -----------------------------------------------------------------------------
276 
  type Array1 is array (natural range <>) of
277 
    std_logic;
278 
  type Array2 is array (natural range <>) of
279 
    std_logic_vector(1 downto 0);
280 
  type Array3 is array (natural range <>) of
281 
    std_logic_vector(2 downto 0);
282 
  type Array4 is array (natural range <>) of
283 
    std_logic_vector(3 downto 0);
284 
  type Array5 is array (natural range <>) of
285 
    std_logic_vector(4 downto 0);
286 
  type Array8 is array (natural range <>) of
287 
    std_logic_vector(7 downto 0);
288 
  type Array9 is array (natural range <>) of
289 
    std_logic_vector(8 downto 0);
290 
  type Array10 is array (natural range <>) of
291 
    std_logic_vector(9 downto 0);
292 
  type Array16 is array (natural range <>) of
293 
    std_logic_vector(15 downto 0);
294 
  type Array32 is array (natural range <>) of
295 
    std_logic_vector(31 downto 0);
296 
  type Array34 is array (natural range <>) of
297 
    std_logic_vector(33 downto 0);
298 
 
299 
  -----------------------------------------------------------------------------
300 
  -- Commonly used constants.
301 
  -----------------------------------------------------------------------------
302 
 
303 
  -- STYPE0 constants.
304 
  constant STYPE0_PACKET_ACCEPTED : std_logic_vector(2 downto 0) := "000";
305 
  constant STYPE0_PACKET_RETRY : std_logic_vector(2 downto 0) := "001";
306 
  constant STYPE0_PACKET_NOT_ACCEPTED : std_logic_vector(2 downto 0) := "010";
307 
  constant STYPE0_RESERVED : std_logic_vector(2 downto 0) := "011";
308 
  constant STYPE0_STATUS : std_logic_vector(2 downto 0) := "100";
309 
  constant STYPE0_VC_STATUS : std_logic_vector(2 downto 0) := "101";
310 
  constant STYPE0_LINK_RESPONSE : std_logic_vector(2 downto 0) := "110";
311 
  constant STYPE0_IMPLEMENTATION_DEFINED : std_logic_vector(2 downto 0) := "111";
312 
 
313 
  -- STYPE1 constants.
314 
  constant STYPE1_START_OF_PACKET : std_logic_vector(2 downto 0) := "000";
315 
  constant STYPE1_STOMP : std_logic_vector(2 downto 0) := "001";
316 
  constant STYPE1_END_OF_PACKET : std_logic_vector(2 downto 0) := "010";
317 
  constant STYPE1_RESTART_FROM_RETRY : std_logic_vector(2 downto 0) := "011";
318 
  constant STYPE1_LINK_REQUEST : std_logic_vector(2 downto 0) := "100";
319 
  constant STYPE1_MULTICAST_EVENT : std_logic_vector(2 downto 0) := "101";
320 
  constant STYPE1_RESERVED : std_logic_vector(2 downto 0) := "110";
321 
  constant STYPE1_NOP : std_logic_vector(2 downto 0) := "111";
322 
 
323 
  -- FTYPE constants.
324 
  constant FTYPE_REQUEST_CLASS : std_logic_vector(3 downto 0) := "0010";
325 
  constant FTYPE_WRITE_CLASS : std_logic_vector(3 downto 0) := "0101";
326 
  constant FTYPE_STREAMING_WRITE_CLASS : std_logic_vector(3 downto 0) := "0110";
327 
  constant FTYPE_MAINTENANCE_CLASS : std_logic_vector(3 downto 0) := "1000";
328 
  constant FTYPE_RESPONSE_CLASS : std_logic_vector(3 downto 0) := "1101";
329 
  constant FTYPE_DOORBELL_CLASS : std_logic_vector(3 downto 0) := "1010";
330 
  constant FTYPE_MESSAGE_CLASS : std_logic_vector(3 downto 0) := "0010";
331 
 
332 
  -- TTYPE Constants
333 
  constant TTYPE_MAINTENANCE_READ_REQUEST : std_logic_vector(3 downto 0) := "0000";
334 
  constant TTYPE_MAINTENANCE_WRITE_REQUEST : std_logic_vector(3 downto 0) := "0001";
335 
  constant TTYPE_MAINTENANCE_READ_RESPONSE : std_logic_vector(3 downto 0) := "0010";
336 
  constant TTYPE_MAINTENANCE_WRITE_RESPONSE : std_logic_vector(3 downto 0) := "0011";
337 
  constant TTYPE_NREAD_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
338 
  constant TTYPE_NWRITE_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
339 
 
340 
  constant LINK_REQUEST_CMD_RESET_DEVICE : std_logic_vector(2 downto 0) := "011";
341 
  constant LINK_REQUEST_CMD_INPUT_STATUS : std_logic_vector(2 downto 0) := "100";
342 
 
343 
  constant PACKET_NOT_ACCEPTED_CAUSE_UNEXPECTED_ACKID : std_logic_vector(4 downto 0) := "00001";
344 
  constant PACKET_NOT_ACCEPTED_CAUSE_CONTROL_CRC : std_logic_vector(4 downto 0) := "00010";
345 
  constant PACKET_NOT_ACCEPTED_CAUSE_NON_MAINTENANCE_STOPPED : std_logic_vector(4 downto 0) := "00011";
346 
  constant PACKET_NOT_ACCEPTED_CAUSE_PACKET_CRC : std_logic_vector(4 downto 0) := "00100";
347 
  constant PACKET_NOT_ACCEPTED_CAUSE_INVALID_CHARACTER : std_logic_vector(4 downto 0) := "00101";
348 
  constant PACKET_NOT_ACCEPTED_CAUSE_NO_RESOURCES : std_logic_vector(4 downto 0) := "00110";
349 
  constant PACKET_NOT_ACCEPTED_CAUSE_LOSS_DESCRAMBLER : std_logic_vector(4 downto 0) := "00111";
350 
  constant PACKET_NOT_ACCEPTED_CAUSE_GENERAL_ERROR : std_logic_vector(4 downto 0) := "11111";
351 
 
352 
  -----------------------------------------------------------------------------
353 
  -- Types used in simulations.
354 
  -----------------------------------------------------------------------------
355 
  type ByteArray is array (natural range <>) of
356 
    std_logic_vector(7 downto 0);
357 
  type HalfwordArray is array (natural range <>) of
358 
    std_logic_vector(15 downto 0);
359 
  type WordArray is array (natural range <>) of
360 
    std_logic_vector(31 downto 0);
361 
  type DoublewordArray is array (natural range <>) of
362 
    std_logic_vector(63 downto 0);
363 
 
364 
  -- Type defining a RapidIO frame.
365 
  type RioFrame is record
366 
    length : natural range 0 to 69;
367 
    payload : WordArray(0 to 68);
368 
  end record;
369 
  type RioFrameArray is array (natural range <>) of RioFrame;
370 
 
371 
  -- Type defining a RapidIO payload.
372 
  type RioPayload is record
373 
    length : natural range 0 to 133;
374 
    data : HalfwordArray(0 to 132);
375 
  end record;
376 
 
377 
  -----------------------------------------------------------------------------
378 
  -- Crc5 calculation function.
379 
  -- ITU, polynom=0x15.
380 
  -----------------------------------------------------------------------------
381 
  function Crc5(constant data : in std_logic_vector(18 downto 0);
382 
                constant crc : in std_logic_vector(4 downto 0))
383 
    return std_logic_vector;
384 
 
385 
  ---------------------------------------------------------------------------
386 
  -- Create a RapidIO physical layer control symbol.
387 
  ---------------------------------------------------------------------------
388 
  function RioControlSymbolCreate(
389 
    constant stype0 : in std_logic_vector(2 downto 0);
390 
    constant parameter0 : in std_logic_vector(4 downto 0);
391 
    constant parameter1 : in std_logic_vector(4 downto 0);
392 
    constant stype1 : in std_logic_vector(2 downto 0);
393 
    constant cmd : in std_logic_vector(2 downto 0))
394 
    return std_logic_vector;
395 
 
396 
  -----------------------------------------------------------------------------
397 
  -- Crc16 calculation function.
398 
  -- CITT, polynom=0x1021.
399 
  -----------------------------------------------------------------------------
400 
  function Crc16(constant data : in std_logic_vector(15 downto 0);
401 
                 constant crc : in std_logic_vector(15 downto 0))
402 
    return std_logic_vector;
403 
 
404 
  ---------------------------------------------------------------------------
405 
  -- Create a randomly initialized data array.
406 
  ---------------------------------------------------------------------------
407 
  procedure CreateRandomPayload(
408 47 magro732 
    variable payload : out HalfwordArray;
409 2 magro732 
    variable seed1 : inout positive;
410 
    variable seed2 : inout positive);
411 
  procedure CreateRandomPayload(
412 47 magro732 
    variable payload : out DoublewordArray;
413 2 magro732 
    variable seed1 : inout positive;
414 
    variable seed2 : inout positive);
415 
 
416 
  ---------------------------------------------------------------------------
417 
  -- Create a generic RapidIO frame.
418 
  ---------------------------------------------------------------------------
419 
  function RioFrameCreate(
420 
    constant ackId : in std_logic_vector(4 downto 0);
421 
    constant vc : in std_logic;
422 
    constant crf : in std_logic;
423 
    constant prio : in std_logic_vector(1 downto 0);
424 
    constant tt : in std_logic_vector(1 downto 0);
425 
    constant ftype : in std_logic_vector(3 downto 0);
426 
    constant sourceId : in std_logic_vector(15 downto 0);
427 
    constant destId : in std_logic_vector(15 downto 0);
428 
    constant payload : in RioPayload)
429 
    return RioFrame;
430 
 
431 
  ---------------------------------------------------------------------------
432 
  -- Create a NWRITE RapidIO frame.
433 
  ---------------------------------------------------------------------------
434 
  function RioNwrite(
435 
    constant wrsize : in std_logic_vector(3 downto 0);
436 45 magro732 
    constant address : in std_logic_vector(28 downto 0);
437 
    constant wdptr : in std_logic;
438 
    constant xamsbs : in std_logic_vector(1 downto 0);
439 
    constant dataLength : in natural range 1 to 32;
440 
    constant data : in DoublewordArray(0 to 31))
441 
    return RioPayload;
442 
 
443 
  ---------------------------------------------------------------------------
444 
  -- Create a NWRITER RapidIO frame.
445 
  ---------------------------------------------------------------------------
446 
  function RioNwriteR(
447 
    constant wrsize : in std_logic_vector(3 downto 0);
448 2 magro732 
    constant tid : in std_logic_vector(7 downto 0);
449 
    constant address : in std_logic_vector(28 downto 0);
450 
    constant wdptr : in std_logic;
451 
    constant xamsbs : in std_logic_vector(1 downto 0);
452 
    constant dataLength : in natural range 1 to 32;
453 
    constant data : in DoublewordArray(0 to 31))
454 
    return RioPayload;
455 
 
456 
  ---------------------------------------------------------------------------
457 
  -- Create a NREAD RapidIO frame.
458 
  ---------------------------------------------------------------------------
459 
  function RioNread(
460 
    constant rdsize : in std_logic_vector(3 downto 0);
461 
    constant tid : in std_logic_vector(7 downto 0);
462 
    constant address : in std_logic_vector(28 downto 0);
463 
    constant wdptr : in std_logic;
464 
    constant xamsbs : in std_logic_vector(1 downto 0))
465 
    return RioPayload;
466 
 
467 
  ---------------------------------------------------------------------------
468 
  -- Create a RESPONSE RapidIO frame.
469 
  ---------------------------------------------------------------------------
470 
  function RioResponse(
471 
    constant status : in std_logic_vector(3 downto 0);
472 
    constant tid : in std_logic_vector(7 downto 0);
473 
    constant dataLength : in natural range 0 to 32;
474 
    constant data : in DoublewordArray(0 to 31))
475 
    return RioPayload;
476 
 
477 
  ---------------------------------------------------------------------------
478 
  -- Create a Maintenance RapidIO frame.
479 
  ---------------------------------------------------------------------------
480 
  function RioMaintenance(
481 
    constant transaction : in std_logic_vector(3 downto 0);
482 
    constant size : in std_logic_vector(3 downto 0);
483 
    constant tid : in std_logic_vector(7 downto 0);
484 
    constant hopCount : in std_logic_vector(7 downto 0);
485 
    constant configOffset : in std_logic_vector(20 downto 0);
486 
    constant wdptr : in std_logic;
487 
    constant dataLength : in natural range 0 to 8;
488 
    constant data : in DoublewordArray(0 to 7))
489 
    return RioPayload;
490 
 
491 
  -----------------------------------------------------------------------------
492 
  -- Function to convert a std_logic_vector to a string.
493 
  -----------------------------------------------------------------------------
494 
  function byteToString(constant byte : std_logic_vector(7 downto 0))
495 
    return string;
496 
 
497 40 magro732 
  -----------------------------------------------------------------------------
498 
  -- Function to print a std_logic_vector.
499 
  -----------------------------------------------------------------------------
500 
  function to_string(constant value : std_logic_vector)
501 
    return string;
502 
 
503 2 magro732 
  ---------------------------------------------------------------------------
504 
  -- Procedure to print to report file and output
505 
  ---------------------------------------------------------------------------
506 
  procedure PrintR( constant str : string );
507 
 
508 
  ---------------------------------------------------------------------------
509 
  -- Procedure to print to spec file
510 
  ---------------------------------------------------------------------------
511 
  procedure PrintS( constant str : string );
512 
 
513 
  ---------------------------------------------------------------------------
514 
  -- Procedure to Assert Expression
515 
  ---------------------------------------------------------------------------
516 
  procedure AssertE( constant exp: boolean; constant str : string );
517 
 
518 
  ---------------------------------------------------------------------------
519 
  -- Procedure to Print Error
520 
  ---------------------------------------------------------------------------
521 
  procedure PrintE( constant str : string );
522 
 
523 
  ---------------------------------------------------------------------------
524 40 magro732 
  -- Procedures for test control.
525 2 magro732 
  ---------------------------------------------------------------------------
526 40 magro732 
 
527 
  procedure TestWarning(constant tag : in string);
528 
  procedure TestError(constant tag : in string;
529 
                      constant stopAtError : in boolean := true);
530 
  procedure TestCompare(constant expression : in boolean;
531 
                        constant tag : in string := "";
532 
                        constant stopAtError : in boolean := true);
533 
  procedure TestCompare(constant got : in std_logic;
534 
                        constant expected : in std_logic;
535 
                        constant tag : in string := "";
536 
                        constant stopAtError : in boolean := true);
537 
  procedure TestCompare(constant got : in std_logic_vector;
538 
                        constant expected : in std_logic_vector;
539 
                        constant tag : in string := "";
540 
                        constant stopAtError : in boolean := true);
541 
  procedure TestCompare(constant got : in natural;
542 
                        constant expected : in natural;
543 
                        constant tag : in string := "";
544 
                        constant stopAtError : in boolean := true);
545 
  procedure TestCompare(constant got : in time;
546 
                        constant expected : in time;
547 
                        constant tag : in string := "";
548 
                        constant stopAtError : in boolean := true);
549 
 
550 
  procedure TestWait(signal waitSignal : in std_logic;
551 
                     constant waitValue : in std_logic;
552 
                     constant tag : in string := "";
553 
                     constant waitTime : in time := 1 ms;
554 
                     constant stopAtError : in boolean := true);
555 
  procedure TestWait(signal waitSignal : in std_logic;
556 
                     constant waitValue : in std_logic;
557 
                     signal ackSignal : inout std_logic;
558 
                     constant tag : in string := "";
559 
                     constant waitTime : in time := 1 ms;
560 
                     constant stopAtError : in boolean := true);
561 
 
562 2 magro732 
  procedure TestEnd;
563 
 
564 
end package;
565 
 
566 
-------------------------------------------------------------------------------
567 
-- RioCommon package body description.
568 
-------------------------------------------------------------------------------
569 
package body rio_common is
570 
  -----------------------------------------------------------------------------
571 
  -- Crc5 calculation function.
572 
  -- ITU, polynom=0x15.
573 
  -----------------------------------------------------------------------------
574 
  function Crc5(constant data : in std_logic_vector(18 downto 0);
575 
                constant crc : in std_logic_vector(4 downto 0))
576 
    return std_logic_vector is
577 
    type crcTableType is array (0 to 31) of std_logic_vector(7 downto 0);
578 
    constant crcTable : crcTableType := (
579 
      x"00", x"15", x"1f", x"0a", x"0b", x"1e", x"14", x"01",
580 
      x"16", x"03", x"09", x"1c", x"1d", x"08", x"02", x"17",
581 
      x"19", x"0c", x"06", x"13", x"12", x"07", x"0d", x"18",
582 
      x"0f", x"1a", x"10", x"05", x"04", x"11", x"1b", x"0e" );
583 
    variable index : natural range 0 to 31;
584 
    variable result : std_logic_vector(4 downto 0);
585 
  begin
586 
    result := crc;
587 
    index := to_integer(unsigned(data(18 downto 14) xor result));
588 
    result := crcTable(index)(4 downto 0);
589 
    index := to_integer(unsigned(data(13 downto 9) xor result));
590 
    result := crcTable(index)(4 downto 0);
591 
    index := to_integer(unsigned(data(8 downto 4) xor result));
592 
    result := crcTable(index)(4 downto 0);
593 
    index := to_integer(unsigned((data(3 downto 0) & '0') xor result));
594 
    return crcTable(index)(4 downto 0);
595 
  end Crc5;
596 
 
597 
  ---------------------------------------------------------------------------
598 
  -- Create a RapidIO physical layer control symbol.
599 
  ---------------------------------------------------------------------------
600 
  function RioControlSymbolCreate(
601 
    constant stype0 : in std_logic_vector(2 downto 0);
602 
    constant parameter0 : in std_logic_vector(4 downto 0);
603 
    constant parameter1 : in std_logic_vector(4 downto 0);
604 
    constant stype1 : in std_logic_vector(2 downto 0);
605 
    constant cmd : in std_logic_vector(2 downto 0))
606 
    return std_logic_vector is
607 37 magro732 
    variable returnValue : std_logic_vector(23 downto 0);
608 2 magro732 
    variable symbolData : std_logic_vector(18 downto 0);
609 
  begin
610 
    symbolData(18 downto 16) := stype0;
611 
    symbolData(15 downto 11) := parameter0;
612 
    symbolData(10 downto 6) := parameter1;
613 
    symbolData(5 downto 3) := stype1;
614 
    symbolData(2 downto 0) := cmd;
615 
 
616 37 magro732 
    returnValue(23 downto 5) := symbolData;
617 
    returnValue(4 downto 0) := Crc5(symbolData, "11111");
618 2 magro732 
 
619 
    return returnValue;
620 
  end function;
621 
 
622 
  -----------------------------------------------------------------------------
623 
  -- Crc16 calculation function.
624 
  -- CITT, polynom=0x1021.
625 
  -----------------------------------------------------------------------------
626 
  function Crc16(constant data : in std_logic_vector(15 downto 0);
627 
                 constant crc : in std_logic_vector(15 downto 0))
628 
    return std_logic_vector is
629 
    type crcTableType is array (0 to 255) of std_logic_vector(15 downto 0);
630 
    constant crcTable : crcTableType := (
631 
      x"0000", x"1021", x"2042", x"3063", x"4084", x"50a5", x"60c6", x"70e7",
632 
      x"8108", x"9129", x"a14a", x"b16b", x"c18c", x"d1ad", x"e1ce", x"f1ef",
633 
      x"1231", x"0210", x"3273", x"2252", x"52b5", x"4294", x"72f7", x"62d6",
634 
      x"9339", x"8318", x"b37b", x"a35a", x"d3bd", x"c39c", x"f3ff", x"e3de",
635 
      x"2462", x"3443", x"0420", x"1401", x"64e6", x"74c7", x"44a4", x"5485",
636 
      x"a56a", x"b54b", x"8528", x"9509", x"e5ee", x"f5cf", x"c5ac", x"d58d",
637 
      x"3653", x"2672", x"1611", x"0630", x"76d7", x"66f6", x"5695", x"46b4",
638 
      x"b75b", x"a77a", x"9719", x"8738", x"f7df", x"e7fe", x"d79d", x"c7bc",
639 
      x"48c4", x"58e5", x"6886", x"78a7", x"0840", x"1861", x"2802", x"3823",
640 
      x"c9cc", x"d9ed", x"e98e", x"f9af", x"8948", x"9969", x"a90a", x"b92b",
641 
      x"5af5", x"4ad4", x"7ab7", x"6a96", x"1a71", x"0a50", x"3a33", x"2a12",
642 
      x"dbfd", x"cbdc", x"fbbf", x"eb9e", x"9b79", x"8b58", x"bb3b", x"ab1a",
643 
      x"6ca6", x"7c87", x"4ce4", x"5cc5", x"2c22", x"3c03", x"0c60", x"1c41",
644 
      x"edae", x"fd8f", x"cdec", x"ddcd", x"ad2a", x"bd0b", x"8d68", x"9d49",
645 
      x"7e97", x"6eb6", x"5ed5", x"4ef4", x"3e13", x"2e32", x"1e51", x"0e70",
646 
      x"ff9f", x"efbe", x"dfdd", x"cffc", x"bf1b", x"af3a", x"9f59", x"8f78",
647 
      x"9188", x"81a9", x"b1ca", x"a1eb", x"d10c", x"c12d", x"f14e", x"e16f",
648 
      x"1080", x"00a1", x"30c2", x"20e3", x"5004", x"4025", x"7046", x"6067",
649 
      x"83b9", x"9398", x"a3fb", x"b3da", x"c33d", x"d31c", x"e37f", x"f35e",
650 
      x"02b1", x"1290", x"22f3", x"32d2", x"4235", x"5214", x"6277", x"7256",
651 
      x"b5ea", x"a5cb", x"95a8", x"8589", x"f56e", x"e54f", x"d52c", x"c50d",
652 
      x"34e2", x"24c3", x"14a0", x"0481", x"7466", x"6447", x"5424", x"4405",
653 
      x"a7db", x"b7fa", x"8799", x"97b8", x"e75f", x"f77e", x"c71d", x"d73c",
654 
      x"26d3", x"36f2", x"0691", x"16b0", x"6657", x"7676", x"4615", x"5634",
655 
      x"d94c", x"c96d", x"f90e", x"e92f", x"99c8", x"89e9", x"b98a", x"a9ab",
656 
      x"5844", x"4865", x"7806", x"6827", x"18c0", x"08e1", x"3882", x"28a3",
657 
      x"cb7d", x"db5c", x"eb3f", x"fb1e", x"8bf9", x"9bd8", x"abbb", x"bb9a",
658 
      x"4a75", x"5a54", x"6a37", x"7a16", x"0af1", x"1ad0", x"2ab3", x"3a92",
659 
      x"fd2e", x"ed0f", x"dd6c", x"cd4d", x"bdaa", x"ad8b", x"9de8", x"8dc9",
660 
      x"7c26", x"6c07", x"5c64", x"4c45", x"3ca2", x"2c83", x"1ce0", x"0cc1",
661 
      x"ef1f", x"ff3e", x"cf5d", x"df7c", x"af9b", x"bfba", x"8fd9", x"9ff8",
662 
      x"6e17", x"7e36", x"4e55", x"5e74", x"2e93", x"3eb2", x"0ed1", x"1ef0" );
663 
    variable index : natural range 0 to 255;
664 
    variable result : std_logic_vector(15 downto 0);
665 
  begin
666 
    result := crc;
667 
    index := to_integer(unsigned(data(15 downto 8) xor result(15 downto 8)));
668 
    result := crcTable(index) xor (result(7 downto 0) & x"00");
669 
    index := to_integer(unsigned(data(7 downto 0) xor result(15 downto 8)));
670 
    result := crcTable(index) xor (result(7 downto 0) & x"00");
671 
    return result;
672 
  end Crc16;
673 
 
674 
  ---------------------------------------------------------------------------
675 
  -- Create a randomly initialized data array.
676 
  ---------------------------------------------------------------------------
677 
  procedure CreateRandomPayload(
678 47 magro732 
    variable payload : out HalfwordArray;
679 2 magro732 
    variable seed1 : inout positive;
680 
    variable seed2 : inout positive) is
681 
    variable rand: real;
682 
    variable int_rand: integer;
683 
    variable stim: std_logic_vector(7 downto 0);
684 
  begin
685 
    for i in payload'range loop
686 
      uniform(seed1, seed2, rand);
687 
      int_rand := integer(trunc(rand*256.0));
688 
      payload(i)(7 downto 0) := std_logic_vector(to_unsigned(int_rand, 8));
689 
      uniform(seed1, seed2, rand);
690 
      int_rand := integer(trunc(rand*256.0));
691 
      payload(i)(15 downto 8) := std_logic_vector(to_unsigned(int_rand, 8));
692 
    end loop;
693 
  end procedure;
694 
 
695 
  procedure CreateRandomPayload(
696 47 magro732 
    variable payload : out DoublewordArray;
697 2 magro732 
    variable seed1 : inout positive;
698 
    variable seed2 : inout positive) is
699 
    variable rand: real;
700 
    variable int_rand: integer;
701 
    variable stim: std_logic_vector(7 downto 0);
702 
  begin
703 
    for i in payload'range loop
704 
      uniform(seed1, seed2, rand);
705 
      int_rand := integer(trunc(rand*256.0));
706 
      payload(i)(7 downto 0) := std_logic_vector(to_unsigned(int_rand, 8));
707 
      uniform(seed1, seed2, rand);
708 
      int_rand := integer(trunc(rand*256.0));
709 
      payload(i)(15 downto 8) := std_logic_vector(to_unsigned(int_rand, 8));
710 
      uniform(seed1, seed2, rand);
711 
      int_rand := integer(trunc(rand*256.0));
712 
      payload(i)(23 downto 16) := std_logic_vector(to_unsigned(int_rand, 8));
713 
      uniform(seed1, seed2, rand);
714 
      int_rand := integer(trunc(rand*256.0));
715 
      payload(i)(31 downto 24) := std_logic_vector(to_unsigned(int_rand, 8));
716 
      uniform(seed1, seed2, rand);
717 
      int_rand := integer(trunc(rand*256.0));
718 
      payload(i)(39 downto 32) := std_logic_vector(to_unsigned(int_rand, 8));
719 
      uniform(seed1, seed2, rand);
720 
      int_rand := integer(trunc(rand*256.0));
721 
      payload(i)(47 downto 40) := std_logic_vector(to_unsigned(int_rand, 8));
722 
      uniform(seed1, seed2, rand);
723 
      int_rand := integer(trunc(rand*256.0));
724 
      payload(i)(55 downto 48) := std_logic_vector(to_unsigned(int_rand, 8));
725 
      uniform(seed1, seed2, rand);
726 
      int_rand := integer(trunc(rand*256.0));
727 
      payload(i)(63 downto 56) := std_logic_vector(to_unsigned(int_rand, 8));
728 
    end loop;
729 
  end procedure;
730 
  ---------------------------------------------------------------------------
731 
  -- Create a generic RapidIO frame.
732 
  ---------------------------------------------------------------------------
733 
  function RioFrameCreate(
734 
    constant ackId : in std_logic_vector(4 downto 0);
735 
    constant vc : in std_logic;
736 
    constant crf : in std_logic;
737 
    constant prio : in std_logic_vector(1 downto 0);
738 
    constant tt : in std_logic_vector(1 downto 0);
739 
    constant ftype : in std_logic_vector(3 downto 0);
740 
    constant sourceId : in std_logic_vector(15 downto 0);
741 
    constant destId : in std_logic_vector(15 downto 0);
742 
    constant payload : in RioPayload) return RioFrame is
743 
    variable frame : RioFrame;
744 
    variable result : HalfwordArray(0 to 137);
745 
    variable crc : std_logic_vector(15 downto 0) := x"ffff";
746 
  begin
747 
    -- Add the header and addresses.
748 
    result(0) := ackId & "0" & vc & crf & prio & tt & ftype;
749 
    result(1) := destId;
750 
    result(2) := sourceId;
751 
 
752 
    -- Update the calculated CRC with the header contents.
753 
    crc := Crc16("00000" & result(0)(10 downto 0), crc);
754 
    crc := Crc16(result(1), crc);
755 
    crc := Crc16(result(2), crc);
756 
 
757 
    -- Check if a single CRC should be added or two.
758 
    if (payload.length <= 37) then
759 
      -- Single CRC.
760 
      for i in 0 to payload.length-1 loop
761 
        result(i+3) := payload.data(i);
762 
        crc := Crc16(payload.data(i), crc);
763 
      end loop;
764 
      result(payload.length+3) := crc;
765 
 
766 
      -- Check if paddning is needed to make the payload even 32-bit.
767 
      if ((payload.length mod 2) = 1) then
768 
        result(payload.length+4) := x"0000";
769 
        frame.length := (payload.length+5) / 2;
770 
      else
771 
        frame.length := (payload.length+4) / 2;
772 
      end if;
773 
    else
774 
      -- Double CRC.
775 
      for i in 0 to 36 loop
776 
        result(i+3) := payload.data(i);
777 
        crc := Crc16(payload.data(i), crc);
778 
      end loop;
779 
 
780 
      -- Add in-the-middle crc.
781 
      result(40) := crc;
782 
      crc := Crc16(crc, crc);
783 
 
784 
      for i in 37 to payload.length-1 loop
785 
        result(i+4) := payload.data(i);
786 
        crc := Crc16(payload.data(i), crc);
787 
      end loop;
788 
      result(payload.length+4) := crc;
789 
 
790 
      -- Check if paddning is needed to make the payload even 32-bit.
791 
      if ((payload.length mod 2) = 0) then
792 
        result(payload.length+5) := x"0000";
793 
        frame.length := (payload.length+6) / 2;
794 
      else
795 
        frame.length := (payload.length+5) / 2;
796 
      end if;
797 
    end if;
798 
 
799 
    -- Update the result length.
800 
    for i in 0 to frame.length-1 loop
801 
      frame.payload(i) := result(2*i) & result(2*i+1);
802 
    end loop;
803 
 
804 
    return frame;
805 
  end function;
806 
 
807 
  -----------------------------------------------------------------------------
808 
  --
809 
  -----------------------------------------------------------------------------
810 
  function RioNwrite(
811 
    constant wrsize : in std_logic_vector(3 downto 0);
812 
    constant address : in std_logic_vector(28 downto 0);
813 
    constant wdptr : in std_logic;
814 
    constant xamsbs : in std_logic_vector(1 downto 0);
815 
    constant dataLength : in natural range 1 to 32;
816 
    constant data : in DoublewordArray(0 to 31))
817 
    return RioPayload is
818 
    variable payload : RioPayload;
819 
  begin
820 
    payload.data(0)(15 downto 12) := "0100";
821 
    payload.data(0)(11 downto 8) := wrsize;
822 45 magro732 
    payload.data(0)(7 downto 0) := (others=>'0');
823 
 
824 
    payload.data(1) := address(28 downto 13);
825 
 
826 
    payload.data(2)(15 downto 3) := address(12 downto 0);
827 
    payload.data(2)(2) := wdptr;
828 
    payload.data(2)(1 downto 0) := xamsbs;
829 
 
830 
    for i in 0 to dataLength-1 loop
831 
      payload.data(3+4*i) := data(i)(63 downto 48);
832 
      payload.data(4+4*i) := data(i)(47 downto 32);
833 
      payload.data(5+4*i) := data(i)(31 downto 16);
834 
      payload.data(6+4*i) := data(i)(15 downto 0);
835 
    end loop;
836 
 
837 
    payload.length := 3 + 4*dataLength;
838 
 
839 
    return payload;
840 
  end function;
841 
 
842 
  -----------------------------------------------------------------------------
843 
  --
844 
  -----------------------------------------------------------------------------
845 
  function RioNwriteR(
846 
    constant wrsize : in std_logic_vector(3 downto 0);
847 
    constant tid : in std_logic_vector(7 downto 0);
848 
    constant address : in std_logic_vector(28 downto 0);
849 
    constant wdptr : in std_logic;
850 
    constant xamsbs : in std_logic_vector(1 downto 0);
851 
    constant dataLength : in natural range 1 to 32;
852 
    constant data : in DoublewordArray(0 to 31))
853 
    return RioPayload is
854 
    variable payload : RioPayload;
855 
  begin
856 
    payload.data(0)(15 downto 12) := "0101";
857 
    payload.data(0)(11 downto 8) := wrsize;
858 2 magro732 
    payload.data(0)(7 downto 0) := tid;
859 
 
860 
    payload.data(1) := address(28 downto 13);
861 
 
862 
    payload.data(2)(15 downto 3) := address(12 downto 0);
863 
    payload.data(2)(2) := wdptr;
864 
    payload.data(2)(1 downto 0) := xamsbs;
865 
 
866 
    for i in 0 to dataLength-1 loop
867 
      payload.data(3+4*i) := data(i)(63 downto 48);
868 
      payload.data(4+4*i) := data(i)(47 downto 32);
869 
      payload.data(5+4*i) := data(i)(31 downto 16);
870 
      payload.data(6+4*i) := data(i)(15 downto 0);
871 
    end loop;
872 
 
873 
    payload.length := 3 + 4*dataLength;
874 
 
875 
    return payload;
876 
  end function;
877 
 
878 
  -----------------------------------------------------------------------------
879 
  --
880 
  -----------------------------------------------------------------------------
881 
  function RioNread(
882 
    constant rdsize : in std_logic_vector(3 downto 0);
883 
    constant tid : in std_logic_vector(7 downto 0);
884 
    constant address : in std_logic_vector(28 downto 0);
885 
    constant wdptr : in std_logic;
886 
    constant xamsbs : in std_logic_vector(1 downto 0))
887 
    return RioPayload is
888 
    variable payload : RioPayload;
889 
  begin
890 
    payload.data(0)(15 downto 12) := "0100";
891 
    payload.data(0)(11 downto 8) := rdsize;
892 
    payload.data(0)(7 downto 0) := tid;
893 
 
894 
    payload.data(1) := address(28 downto 13);
895 
 
896 
    payload.data(2)(15 downto 3) := address(12 downto 0);
897 
    payload.data(2)(2) := wdptr;
898 
    payload.data(2)(1 downto 0) := xamsbs;
899 
 
900 
    payload.length := 3;
901 
 
902 
    return payload;
903 
  end function;
904 
 
905 
  ---------------------------------------------------------------------------
906 
  -- Create a RESPONSE RapidIO frame.
907 
  ---------------------------------------------------------------------------
908 
  function RioResponse(
909 
    constant status : in std_logic_vector(3 downto 0);
910 
    constant tid : in std_logic_vector(7 downto 0);
911 
    constant dataLength : in natural range 0 to 32;
912 
    constant data : in DoublewordArray(0 to 31))
913 
    return RioPayload is
914 
    variable payload : RioPayload;
915 
  begin
916 
    payload.data(0)(11 downto 8) := status;
917 
    payload.data(0)(7 downto 0) := tid;
918 
 
919 
    if (dataLength = 0) then
920 
      payload.data(0)(15 downto 12) := "0000";
921 
      payload.length := 1;
922 
    else
923 
      payload.data(0)(15 downto 12) := "1000";
924 
 
925 
      for i in 0 to dataLength-1 loop
926 
        payload.data(1+4*i) := data(i)(63 downto 48);
927 
        payload.data(2+4*i) := data(i)(47 downto 32);
928 
        payload.data(3+4*i) := data(i)(31 downto 16);
929 
        payload.data(4+4*i) := data(i)(15 downto 0);
930 
      end loop;
931 
 
932 
      payload.length := 1 + 4*dataLength;
933 
    end if;
934 
 
935 
    return payload;
936 
  end function;
937 
 
938 
  ---------------------------------------------------------------------------
939 
  -- Create a Maintenance RapidIO frame.
940 
  ---------------------------------------------------------------------------
941 
  function RioMaintenance(
942 
    constant transaction : in std_logic_vector(3 downto 0);
943 
    constant size : in std_logic_vector(3 downto 0);
944 
    constant tid : in std_logic_vector(7 downto 0);
945 
    constant hopCount : in std_logic_vector(7 downto 0);
946 
    constant configOffset : in std_logic_vector(20 downto 0);
947 
    constant wdptr : in std_logic;
948 
    constant dataLength : in natural range 0 to 8;
949 
    constant data : in DoublewordArray(0 to 7))
950 
    return RioPayload is
951 
    variable payload : RioPayload;
952 
  begin
953 
    payload.data(0)(15 downto 12) := transaction;
954 
    payload.data(0)(11 downto 8) := size;
955 
    payload.data(0)(7 downto 0) := tid;
956 
 
957 
    payload.data(1)(15 downto 8) := hopCount;
958 
    payload.data(1)(7 downto 0) := configOffset(20 downto 13);
959 
 
960 
    payload.data(2)(15 downto 3) := configOffset(12 downto 0);
961 
    payload.data(2)(2) := wdptr;
962 
    payload.data(2)(1 downto 0) := "00";
963 
 
964 
    if (dataLength = 0) then
965 
      payload.length := 3;
966 
    else
967 
      for i in 0 to dataLength-1 loop
968 
        payload.data(3+4*i) := data(i)(63 downto 48);
969 
        payload.data(4+4*i) := data(i)(47 downto 32);
970 
        payload.data(5+4*i) := data(i)(31 downto 16);
971 
        payload.data(6+4*i) := data(i)(15 downto 0);
972 
      end loop;
973 
 
974 
      payload.length := 3 + 4*dataLength;
975 
    end if;
976 
 
977 
    return payload;
978 
  end function;
979 
 
980 
  -----------------------------------------------------------------------------
981 
  -- Function to convert a std_logic_vector to a string.
982 
  -----------------------------------------------------------------------------
983 
  function byteToString(constant byte : std_logic_vector(7 downto 0))
984 
    return string is
985 
    constant table : string(1 to 16) := "0123456789abcdef";
986 
    variable returnValue : string(1 to 2);
987 
  begin
988 
    returnValue(1) := table(to_integer(unsigned(byte(7 downto 4))) + 1);
989 
    returnValue(2) := table(to_integer(unsigned(byte(3 downto 0))) + 1);
990 
    return returnValue;
991 
  end function;
992 
 
993 40 magro732 
  -----------------------------------------------------------------------------
994 
  -- Function to print std_logic_vector.
995 
  -----------------------------------------------------------------------------
996 
  function to_string(constant value : std_logic) return string is
997 
    variable s : string(1 to 1);
998 
  begin
999 
    if (value = '0') then
1000 
      s(1) := '0';
1001 
    elsif (value = '1') then
1002 
      s(1) := '1';
1003 
    elsif (value = 'U') then
1004 
      s(1) := 'U';
1005 
    elsif (value = 'X') then
1006 
      s(1) := 'X';
1007 
    else
1008 
      s(1) := '?';
1009 
    end if;
1010 
    return s;
1011 
  end function;
1012 
  function to_string(constant value : std_logic_vector) return string is
1013 
    variable s : string(1 to value'length);
1014 
    variable index : positive;
1015 
    variable i : natural;
1016 
  begin
1017 
    index := 1;
1018 
    for i in value'range loop
1019 
      if (value(i) = '0') then
1020 
        s(index) := '0';
1021 
      elsif (value(i) = '1') then
1022 
        s(index) := '1';
1023 
      elsif (value(i) = 'U') then
1024 
        s(index) := 'U';
1025 
      elsif (value(i) = 'X') then
1026 
        s(index) := 'X';
1027 
      else
1028 
        s(index) := '?';
1029 
      end if;
1030 
      index := index + 1;
1031 
    end loop;
1032 
    return s;
1033 
  end function;
1034 
 
1035 2 magro732 
  ---------------------------------------------------------------------------
1036 
  -- Procedure to print test report
1037 
  ---------------------------------------------------------------------------
1038 
  procedure PrintR( constant str : string ) is
1039 
    file reportFile  : text;
1040 
    variable reportLine, outputLine : line;
1041 
    variable fStatus: FILE_OPEN_STATUS;
1042 
  begin
1043 
    --Write report note to wave/transcript window
1044 
    report str severity NOTE;
1045 
  end PrintR;
1046 
 
1047 
  ---------------------------------------------------------------------------
1048 
  -- Procedure to print test spec
1049 
  ---------------------------------------------------------------------------
1050 
  procedure PrintS( constant str : string ) is
1051 
    file specFile  : text;
1052 
    variable specLine, outputLine : line;
1053 
    variable fStatus: FILE_OPEN_STATUS;
1054 
  begin
1055 
    --Write to spec file
1056 
    file_open(fStatus, specFile, "testspec.txt", append_mode);
1057 
    write(specLine, string'(str));
1058 
    writeline (specFile, specLine);
1059 
    file_close(specFile);
1060 
  end PrintS;
1061 
 
1062 
  ---------------------------------------------------------------------------
1063 
  -- Procedure to Assert Expression
1064 
  ---------------------------------------------------------------------------
1065 
  procedure AssertE( constant exp: boolean; constant str : string ) is
1066 
    file reportFile  : text;
1067 
    variable reportLine, outputLine : line;
1068 
    variable fStatus: FILE_OPEN_STATUS;
1069 
  begin
1070 
    if (not exp) then
1071 
      --Write to STD_OUTPUT
1072 
      report(str) severity error;
1073 
    else
1074 
      PrintR("Status: Passed");
1075 
      PrintS("Status: Passed");
1076 
    end if;
1077 
  end AssertE;
1078 
 
1079 
  ---------------------------------------------------------------------------
1080 
  -- Procedure to Print Error
1081 
  ---------------------------------------------------------------------------
1082 
  procedure PrintE( constant str : string ) is
1083 
    file reportFile  : text;
1084 
    variable reportLine, outputLine : line;
1085 
    variable fStatus: FILE_OPEN_STATUS;
1086 
  begin
1087 
    --Write to STD_OUTPUT
1088 
    report str severity error;
1089 
  end PrintE;
1090 
 
1091 
  ---------------------------------------------------------------------------
1092 40 magro732 
  -- Procedures to handle tests.
1093 2 magro732 
  ---------------------------------------------------------------------------
1094 40 magro732 
 
1095 
  procedure TestWarning(constant tag : in string) is
1096 
    variable writeBuffer : line;
1097 
  begin
1098 
    write(writeBuffer, now);
1099 
    write(writeBuffer, string'(":WARNING:"));
1100 
    write(writeBuffer, tag);
1101 
    writeline(OUTPUT, writeBuffer);
1102 
  end procedure;
1103 
 
1104 
  procedure TestError(constant tag : in string;
1105 
                      constant stopAtError : in boolean := true) is
1106 
    variable writeBuffer : line;
1107 
  begin
1108 
    write(writeBuffer, now);
1109 
    write(writeBuffer, string'(":FAILED:"));
1110 
    write(writeBuffer, tag);
1111 
    writeline(OUTPUT, writeBuffer);
1112 
 
1113 
    if (stopAtError) then
1114 
      std.env.stop(0);
1115 
    end if;
1116 
  end procedure;
1117 
 
1118 
  procedure TestCompare(constant expression : in boolean;
1119 
                        constant tag : in string := "";
1120 
                        constant stopAtError : in boolean := true) is
1121 
    variable writeBuffer : line;
1122 
  begin
1123 
    write(writeBuffer, now);
1124 
    if (not expression) then
1125 
      write(writeBuffer, string'(":FAILED:"));
1126 
    else
1127 
      write(writeBuffer, string'(":PASSED:"));
1128 
    end if;
1129 
    write(writeBuffer, tag);
1130 
    writeline(OUTPUT, writeBuffer);
1131 
 
1132 
    if (stopAtError) and (not expression) then
1133 
      std.env.stop(0);
1134 
    end if;
1135 
  end procedure;
1136 
 
1137 
  procedure TestCompare(constant got : in std_logic;
1138 
                        constant expected : in std_logic;
1139 
                        constant tag : in string := "";
1140 
                        constant stopAtError : in boolean := true) is
1141 
    variable writeBuffer : line;
1142 
  begin
1143 
    write(writeBuffer, now);
1144 
    if (expected /= got) then
1145 
      write(writeBuffer, string'(":FAILED:"));
1146 
      write(writeBuffer, tag);
1147 
      write(writeBuffer, ":got=" & to_string(got));
1148 
      write(writeBuffer, ":expected=" & to_string(expected));
1149 
    else
1150 
      write(writeBuffer, string'(":PASSED:"));
1151 
      write(writeBuffer, tag);
1152 
    end if;
1153 
    writeline(OUTPUT, writeBuffer);
1154 
 
1155 
    if (stopAtError) and (expected /= got) then
1156 
      std.env.stop(0);
1157 
    end if;
1158 
  end procedure;
1159 
 
1160 
  procedure TestCompare(constant got : in std_logic_vector;
1161 
                        constant expected : in std_logic_vector;
1162 
                        constant tag : in string := "";
1163 
                        constant stopAtError : in boolean := true) is
1164 
    variable writeBuffer : line;
1165 
  begin
1166 
    write(writeBuffer, now);
1167 
    if (expected /= got) then
1168 
      write(writeBuffer, string'(":FAILED:"));
1169 
      write(writeBuffer, tag);
1170 
      write(writeBuffer, ":got=" & to_string(got));
1171 
      write(writeBuffer, ":expected=" & to_string(expected));
1172 
    else
1173 
      write(writeBuffer, string'(":PASSED:"));
1174 
      write(writeBuffer, tag);
1175 
    end if;
1176 
    writeline(OUTPUT, writeBuffer);
1177 
 
1178 
    if (stopAtError) and (expected /= got) then
1179 
      std.env.stop(0);
1180 
    end if;
1181 
  end procedure;
1182 
 
1183 
  procedure TestCompare(constant got : in natural;
1184 
                        constant expected : in natural;
1185 
                        constant tag : in string := "";
1186 
                        constant stopAtError : in boolean := true) is
1187 
    variable writeBuffer : line;
1188 
  begin
1189 
    write(writeBuffer, now);
1190 
    if (expected /= got) then
1191 
      write(writeBuffer, string'(":FAILED:"));
1192 
      write(writeBuffer, tag);
1193 
      write(writeBuffer, ":got=" & integer'image(got));
1194 
      write(writeBuffer, ":expected=" & integer'image(expected));
1195 
    else
1196 
      write(writeBuffer, string'(":PASSED:"));
1197 
      write(writeBuffer, tag);
1198 
    end if;
1199 
    writeline(OUTPUT, writeBuffer);
1200 
 
1201 
    if (stopAtError) and (expected /= got) then
1202 
      std.env.stop(0);
1203 
    end if;
1204 
  end procedure;
1205 
 
1206 
  procedure TestCompare(constant got : in time;
1207 
                        constant expected : in time;
1208 
                        constant tag : in string := "";
1209 
                        constant stopAtError : in boolean := true) is
1210 
    variable writeBuffer : line;
1211 
  begin
1212 
    write(writeBuffer, now);
1213 
    if (expected /= got) then
1214 
      write(writeBuffer, string'(":FAILED:"));
1215 
      write(writeBuffer, tag);
1216 
      write(writeBuffer, string'(":got="));
1217 
      write(writeBuffer, got);
1218 
      write(writeBuffer, string'(":expected="));
1219 
      write(writeBuffer, expected);
1220 
    else
1221 
      write(writeBuffer, string'(":PASSED:"));
1222 
      write(writeBuffer, tag);
1223 
    end if;
1224 
    writeline(OUTPUT, writeBuffer);
1225 
 
1226 
    if (stopAtError) and (expected /= got) then
1227 
      std.env.stop(0);
1228 
    end if;
1229 
  end procedure;
1230 
 
1231 
  procedure TestWait(signal waitSignal : in std_logic;
1232 
                     constant waitValue : in std_logic;
1233 
                     constant tag : in string := "";
1234 
                     constant waitTime : in time := 1 ms;
1235 
                     constant stopAtError : in boolean := true) is
1236 
    variable writeBuffer : line;
1237 
  begin
1238 
    if (waitSignal /= waitValue) then
1239 
      wait until waitSignal = waitValue for waitTime;
1240 
      if (waitSignal /= waitValue) then
1241 
        write(writeBuffer, now);
1242 
        write(writeBuffer, string'(":FAILED:"));
1243 
        write(writeBuffer, tag);
1244 
        writeline(OUTPUT, writeBuffer);
1245 
 
1246 
        if (stopAtError) then
1247 
          std.env.stop(0);
1248 
        end if;
1249 
      end if;
1250 
    end if;
1251 
  end procedure;
1252 
 
1253 
  procedure TestWait(signal waitSignal : in std_logic;
1254 
                     constant waitValue : in std_logic;
1255 
                     signal ackSignal : inout std_logic;
1256 
                     constant tag : in string := "";
1257 
                     constant waitTime : in time := 1 ms;
1258 
                     constant stopAtError : in boolean := true) is
1259 
    variable writeBuffer : line;
1260 
  begin
1261 
    if (waitSignal /= waitValue) then
1262 
 
1263 
      wait until waitSignal = waitValue for waitTime;
1264 
 
1265 
      if (waitSignal /= waitValue) then
1266 
        write(writeBuffer, now);
1267 
        write(writeBuffer, string'(":FAILED:"));
1268 
        write(writeBuffer, tag);
1269 
        writeline(OUTPUT, writeBuffer);
1270 
 
1271 
        if (stopAtError) then
1272 
          std.env.stop(0);
1273 
        end if;
1274 
      end if;
1275 
    end if;
1276 
 
1277 
    ackSignal <= not ackSignal;
1278 
 
1279 
    wait until waitSignal /= waitValue for waitTime;
1280 
 
1281 
    if (waitSignal = waitValue) then
1282 
      write(writeBuffer, now);
1283 
      write(writeBuffer, string'(":FAILED:"));
1284 
      write(writeBuffer, tag);
1285 
      writeline(OUTPUT, writeBuffer);
1286 
 
1287 
      if (stopAtError) then
1288 
        std.env.stop(0);
1289 
      end if;
1290 
    end if;
1291 
  end procedure;
1292 
 
1293 2 magro732 
  procedure TestEnd is
1294 40 magro732 
    variable writeBuffer : line;
1295 2 magro732 
  begin
1296 40 magro732 
    write(writeBuffer, now);
1297 
    write(writeBuffer, string'(":COMPLETED"));
1298 
    writeline(OUTPUT, writeBuffer);
1299 
    std.env.stop(0);
1300 2 magro732 
  end TestEnd;
1301 40 magro732 
 
1302 2 magro732 
end rio_common;
1303 
 
1304 
 
1305 
 
1306 
-------------------------------------------------------------------------------
1307 
-- Crc16CITT
1308 
-- A CRC-16 calculator following the implementation proposed in the 2.2
1309 
-- standard.
1310 
-------------------------------------------------------------------------------
1311 
library ieee;
1312 
use ieee.std_logic_1164.all;
1313 
 
1314 
 
1315 
-------------------------------------------------------------------------------
1316 
-- Entity for Crc16CITT.
1317 
-------------------------------------------------------------------------------
1318 
entity Crc16CITT is
1319 
  port(
1320 
    d_i : in  std_logic_vector(15 downto 0);
1321 
    crc_i : in std_logic_vector(15 downto 0);
1322 
    crc_o : out std_logic_vector(15 downto 0));
1323 
end entity;
1324 
 
1325 
 
1326 
-------------------------------------------------------------------------------
1327 
-- Architecture for Crc16CITT.
1328 
-------------------------------------------------------------------------------
1329 
architecture Crc16Impl of Crc16CITT is
1330 
  signal d : std_logic_vector(0 to 15);
1331 
  signal c : std_logic_vector(0 to 15);
1332 
  signal e : std_logic_vector(0 to 15);
1333 
  signal cc : std_logic_vector(0 to 15);
1334 
begin
1335 
 
1336 
  -- Reverse the bit vector indexes to make them the same as in the standard.
1337 
  d(15) <= d_i(0); d(14) <= d_i(1); d(13) <= d_i(2); d(12) <= d_i(3);
1338 
  d(11) <= d_i(4); d(10) <= d_i(5); d(9) <= d_i(6); d(8) <= d_i(7);
1339 
  d(7) <= d_i(8); d(6) <= d_i(9); d(5) <= d_i(10); d(4) <= d_i(11);
1340 
  d(3) <= d_i(12); d(2) <= d_i(13); d(1) <= d_i(14); d(0) <= d_i(15);
1341 
 
1342 
  -- Reverse the bit vector indexes to make them the same as in the standard.
1343 
  c(15) <= crc_i(0); c(14) <= crc_i(1); c(13) <= crc_i(2); c(12) <= crc_i(3);
1344 
  c(11) <= crc_i(4); c(10) <= crc_i(5); c(9) <= crc_i(6); c(8) <= crc_i(7);
1345 
  c(7) <= crc_i(8); c(6) <= crc_i(9); c(5) <= crc_i(10); c(4) <= crc_i(11);
1346 
  c(3) <= crc_i(12); c(2) <= crc_i(13); c(1) <= crc_i(14); c(0) <= crc_i(15);
1347 
 
1348 
  -- Calculate the resulting crc.
1349 
  e <= c xor d;
1350 
  cc(0) <= e(4) xor e(5) xor e(8) xor e(12);
1351 
  cc(1) <= e(5) xor e(6) xor e(9) xor e(13);
1352 
  cc(2) <= e(6) xor e(7) xor e(10) xor e(14);
1353 
  cc(3) <= e(0) xor e(7) xor e(8) xor e(11) xor e(15);
1354 
  cc(4) <= e(0) xor e(1) xor e(4) xor e(5) xor e(9);
1355 
  cc(5) <= e(1) xor e(2) xor e(5) xor e(6) xor e(10);
1356 
  cc(6) <= e(0) xor e(2) xor e(3) xor e(6) xor e(7) xor e(11);
1357 
  cc(7) <= e(0) xor e(1) xor e(3) xor e(4) xor e(7) xor e(8) xor e(12);
1358 
  cc(8) <= e(0) xor e(1) xor e(2) xor e(4) xor e(5) xor e(8) xor e(9) xor e(13);
1359 
  cc(9) <= e(1) xor e(2) xor e(3) xor e(5) xor e(6) xor e(9) xor e(10) xor e(14);
1360 
  cc(10) <= e(2) xor e(3) xor e(4) xor e(6) xor e(7) xor e(10) xor e(11) xor e(15);
1361 
  cc(11) <= e(0) xor e(3) xor e(7) xor e(11);
1362 
  cc(12) <= e(0) xor e(1) xor e(4) xor e(8) xor e(12);
1363 
  cc(13) <= e(1) xor e(2) xor e(5) xor e(9) xor e(13);
1364 
  cc(14) <= e(2) xor e(3) xor e(6) xor e(10) xor e(14);
1365 
  cc(15) <= e(3) xor e(4) xor e(7) xor e(11) xor e(15);
1366 
 
1367 
  -- Reverse the bit vector indexes to make them the same as in the standard.
1368 
  crc_o(15) <= cc(0); crc_o(14) <= cc(1); crc_o(13) <= cc(2); crc_o(12) <= cc(3);
1369 
  crc_o(11) <= cc(4); crc_o(10) <= cc(5); crc_o(9) <= cc(6); crc_o(8) <= cc(7);
1370 
  crc_o(7) <= cc(8); crc_o(6) <= cc(9); crc_o(5) <= cc(10); crc_o(4) <= cc(11);
1371 
  crc_o(3) <= cc(12); crc_o(2) <= cc(13); crc_o(1) <= cc(14); crc_o(0) <= cc(15);
1372 
 
1373 
end architecture;
1374 
 
1375 
 
1376 
 
1377 
-------------------------------------------------------------------------------
1378 
-- MemoryDualPort
1379 
-- Generic synchronous memory with one read/write port and one read port.
1380 
-------------------------------------------------------------------------------
1381 
 
1382 
library ieee;
1383 
use ieee.std_logic_1164.all;
1384 
use ieee.numeric_std.all;
1385 
 
1386 
 
1387 
-------------------------------------------------------------------------------
1388 
-- Entity for MemoryDualPort.
1389 
-------------------------------------------------------------------------------
1390 
entity MemoryDualPort is
1391 
  generic(
1392 
    ADDRESS_WIDTH : natural := 1;
1393 
    DATA_WIDTH : natural := 1);
1394 
  port(
1395 
    clkA_i : in std_logic;
1396 
    enableA_i : in std_logic;
1397 
    writeEnableA_i : in std_logic;
1398 
    addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1399 
    dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1400 
    dataA_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
1401 
 
1402 
    clkB_i : in std_logic;
1403 
    enableB_i : in std_logic;
1404 
    addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1405 
    dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1406 
end entity;
1407 
 
1408 
 
1409 
-------------------------------------------------------------------------------
1410 
-- Architecture for MemoryDualPort.
1411 
-------------------------------------------------------------------------------
1412 
architecture MemoryDualPortImpl of MemoryDualPort is
1413 
  type MemoryType is array (natural range <>) of
1414 
    std_logic_vector(DATA_WIDTH-1 downto 0);
1415 
 
1416 
  signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
1417 
 
1418 
begin
1419 
  process(clkA_i)
1420 
  begin
1421 
    if (clkA_i'event and clkA_i = '1') then
1422 
      if (enableA_i = '1') then
1423 
        if (writeEnableA_i = '1') then
1424 
          memory(to_integer(unsigned(addressA_i))) <= dataA_i;
1425 
        end if;
1426 
 
1427 
        dataA_o <= memory(to_integer(unsigned(addressA_i)));
1428 
      end if;
1429 
    end if;
1430 
  end process;
1431 
 
1432 
  process(clkB_i)
1433 
  begin
1434 
    if (clkB_i'event and clkB_i = '1') then
1435 
      if (enableB_i = '1') then
1436 
        dataB_o <= memory(to_integer(unsigned(addressB_i)));
1437 
      end if;
1438 
    end if;
1439 
  end process;
1440 
 
1441 
end architecture;
1442 
 
1443 
 
1444 
 
1445 
-------------------------------------------------------------------------------
1446 
-- MemorySimpleDualPort
1447 
-- Generic synchronous memory with one write port and one read port.
1448 
-------------------------------------------------------------------------------
1449 
 
1450 
library ieee;
1451 
use ieee.std_logic_1164.all;
1452 
use ieee.numeric_std.all;
1453 
 
1454 
 
1455 
-------------------------------------------------------------------------------
1456 
-- Entity for MemorySimpleDualPort.
1457 
-------------------------------------------------------------------------------
1458 
entity MemorySimpleDualPort is
1459 
  generic(
1460 
    ADDRESS_WIDTH : natural := 1;
1461 
    DATA_WIDTH : natural := 1);
1462 
  port(
1463 
    clkA_i : in std_logic;
1464 
    enableA_i : in std_logic;
1465 
    addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1466 
    dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1467 
 
1468 
    clkB_i : in std_logic;
1469 
    enableB_i : in std_logic;
1470 
    addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1471 
    dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1472 
end entity;
1473 
 
1474 
 
1475 
-------------------------------------------------------------------------------
1476 
-- Architecture for MemorySimpleDualPort.
1477 
-------------------------------------------------------------------------------
1478 
architecture MemorySimpleDualPortImpl of MemorySimpleDualPort is
1479 
  type MemoryType is array (natural range <>) of
1480 
    std_logic_vector(DATA_WIDTH-1 downto 0);
1481 
 
1482 
  signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
1483 
 
1484 
begin
1485 
  process(clkA_i)
1486 
  begin
1487 
    if (clkA_i'event and clkA_i = '1') then
1488 
      if (enableA_i = '1') then
1489 
        memory(to_integer(unsigned(addressA_i))) <= dataA_i;
1490 
      end if;
1491 
    end if;
1492 
  end process;
1493 
 
1494 
  process(clkB_i)
1495 
  begin
1496 
    if (clkB_i'event and clkB_i = '1') then
1497 
      if (enableB_i = '1') then
1498 
        dataB_o <= memory(to_integer(unsigned(addressB_i)));
1499 
      end if;
1500 
    end if;
1501 
  end process;
1502 
 
1503 
end architecture;
1504 
 
1505 
 
1506 
 
1507 
-------------------------------------------------------------------------------
1508 
-- MemorySinglePort
1509 
-- Generic synchronous memory with one read/write port.
1510 
-------------------------------------------------------------------------------
1511 
 
1512 
library ieee;
1513 
use ieee.std_logic_1164.all;
1514 
use ieee.numeric_std.all;
1515 
 
1516 
 
1517 
-------------------------------------------------------------------------------
1518 
-- Entity for MemorySinglePort.
1519 
-------------------------------------------------------------------------------
1520 
entity MemorySinglePort is
1521 
  generic(
1522 
    ADDRESS_WIDTH : natural := 1;
1523 
    DATA_WIDTH : natural := 1);
1524 
  port(
1525 
    clk_i : in std_logic;
1526 
    enable_i : in std_logic;
1527 
    writeEnable_i : in std_logic;
1528 
    address_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1529 
    data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1530 
    data_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1531 
end entity;
1532 
 
1533 
 
1534 
-------------------------------------------------------------------------------
1535 
-- Architecture for MemorySinglePort.
1536 
-------------------------------------------------------------------------------
1537 
architecture MemorySinglePortImpl of MemorySinglePort is
1538 
  type MemoryType is array (natural range <>) of
1539 
    std_logic_vector(DATA_WIDTH-1 downto 0);
1540 
 
1541 
  signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
1542 
 
1543 
begin
1544 
  process(clk_i)
1545 
  begin
1546 
    if (clk_i'event and clk_i = '1') then
1547 
      if (enable_i = '1') then
1548 
        if (writeEnable_i = '1') then
1549 
          memory(to_integer(unsigned(address_i))) <= data_i;
1550 
        end if;
1551 
 
1552 
        data_o <= memory(to_integer(unsigned(address_i)));
1553 
      end if;
1554 
    end if;
1555 
  end process;
1556 
 
1557 
end architecture;
1558 
 
1559 
 
1560 
 
1561 
 
1562 
-------------------------------------------------------------------------------
1563 
-- MemorySimpleDualPortAsync
1564 
-- Generic memory with one synchronous write port and one asynchronous read port.
1565 
-------------------------------------------------------------------------------
1566 
 
1567 
library ieee;
1568 
use ieee.std_logic_1164.all;
1569 
use ieee.numeric_std.all;
1570 
 
1571 
 
1572 
-------------------------------------------------------------------------------
1573 
-- Entity for MemorySimpleDualPortAsync.
1574 
-------------------------------------------------------------------------------
1575 
entity MemorySimpleDualPortAsync is
1576 
  generic(
1577 
    ADDRESS_WIDTH : natural := 1;
1578 
    DATA_WIDTH : natural := 1;
1579 
    INIT_VALUE : std_logic := 'U');
1580 
  port(
1581 
    clkA_i : in std_logic;
1582 
    enableA_i : in std_logic;
1583 
    addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1584 
    dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
1585 
 
1586 
    addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
1587 
    dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
1588 
end entity;
1589 
 
1590 
 
1591 
-------------------------------------------------------------------------------
1592 
-- Architecture for MemorySimpleDualPortAsync.
1593 
-------------------------------------------------------------------------------
1594 
architecture MemorySimpleDualPortAsyncImpl of MemorySimpleDualPortAsync is
1595 
  type MemoryType is array (natural range <>) of
1596 
    std_logic_vector(DATA_WIDTH-1 downto 0);
1597 
 
1598 
  signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1) := (others=>(others=>INIT_VALUE));
1599 
 
1600 
begin
1601 
  process(clkA_i)
1602 
  begin
1603 
    if (clkA_i'event and clkA_i = '1') then
1604 
      if (enableA_i = '1') then
1605 
        memory(to_integer(unsigned(addressA_i))) <= dataA_i;
1606 
      end if;
1607 
    end if;
1608 
  end process;
1609 
 
1610 
  dataB_o <= memory(to_integer(unsigned(addressB_i)));
1611 
 
1612 
end architecture;
1613 
 
1614 
 
1615 
 
1616 
 
1617 
 

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