Subversion Repositories rio

-------------------------------------------------------------------------------

-- 

-- RapidIO IP Library Core

-- 

-- This file is part of the RapidIO IP library project

-- http://www.opencores.org/cores/rio/

-- 

-- Description

-- Contains a platform to build endpoints on.

-- 

-- To Do:

-- -

-- 

-- Author(s): 

-- - Magnus Rosenius, magro732@opencores.org 

-- 

-------------------------------------------------------------------------------

-- 

-- Copyright (C) 2013 Authors and OPENCORES.ORG 

-- 

-- This source file may be used and distributed without 

-- restriction provided that this copyright statement is not 

-- removed from the file and that any derivative work contains 

-- the original copyright notice and the associated disclaimer. 

-- 

-- This source file is free software; you can redistribute it 

-- and/or modify it under the terms of the GNU Lesser General 

-- Public License as published by the Free Software Foundation; 

-- either version 2.1 of the License, or (at your option) any 

-- later version. 

-- 

-- This source is distributed in the hope that it will be 

-- useful, but WITHOUT ANY WARRANTY; without even the implied 

-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 

-- PURPOSE. See the GNU Lesser General Public License for more 

-- details. 

-- 

-- You should have received a copy of the GNU Lesser General 

-- Public License along with this source; if not, download it 

-- from http://www.opencores.org/lgpl.shtml 

-- 

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

-- RioLogicalCommon.

-------------------------------------------------------------------------------

-- Ingress:

-- * Removes in-the-middle and trailing CRC.

-- * Forwards packets to logical-layer handlers depending on ftype and

--   transaction (output as address).

-- * Outputs header and deviceIDs in seperate accesses to facilitate 8- and

--   16-bit deviceAddress support. All fields are right-justified.

-- Egress:

-- * Adds in-the-middle and trailing CRC.

-- * Receives packets from logical-layer handlers.

-- * Receives header and deviceIDs in seperate accesses to facilitate 8- and

--   16-bit deviceAddress support. All fields are right-justified.

-------------------------------------------------------------------------------

-- REMARK: Egress; Places packets in different queues depending on the packet priority?

-- REMARK: Use inputOutput/message/maintenance/gsm/...-strobes instead?

-- REMARK: If the deviceId:s are removed, it will work for both 8/16-bit deviceIds.

--          case (ftype) is

--            when x"1" =>

--              -- Intervention-request class.

--              gsmStb_o <= '1';

--            when x"2" =>

--              -- Request-class.

--              if ((transaction = "0100") or

--                  (transaction = "1100") or (transaction = "1101") or

--                  (transaction = "1110") or (transaction = "1111")) then

--                inputOutputStb_o <= '1';

--              else

--                gsmStb_o <= '1';

--              end if;

--            when x"5" =>

--              -- Write-class.

--              if ((transaction = "0100") or (transaction = "0101") or 

--                  (transaction = "1100") or (transaction = "1101") or

--                  (transaction = "1110")) then

--                inputOutputStb_o <= '1';

--              elsif ((transaction = "0000") or (transaction = "0001")) then

--                gsmStb_o <= '1';

--              end if;

--            when x"6" =>

--              -- Streaming-Write class.

--              inputOutputStb_o <= '1';

--            when x"7" =>

--              -- Flow-control class.

--              flowControlStb_o <= '1';

--            when x"8" =>

--              -- Maintenance class.

--              maintenanceStb_o <= '1';

--            when x"9" =>

--              -- Data-Streaming class.

--              dataStreamingStb_o <= '1';

--            when x"a" =>

--              -- Doorbell class.

--              -- REMARK: Make this belong to input/output since the packets

--              -- and their responses look the same?

--              messagePassingStb_o <= '1';

--            when x"b" =>

--              -- Message class.

--              messagePassingStb_o <= '1';

--            when x"d" =>

--              -- Response class.

--              -- REMARK: Seperate strobe for this???

--              if ((transaction = "0000") or (transaction = "1000")) then

--                -- REMARK: Doorbell-response going in here as well... *sigh*

--                -- REMARK: GSM-responses going in here as well...

--                responseStb_o <= '1';

--              elsif (transaction = "0001") then

--                messagePassing <= '1';

--              end if;

--            when others =>

--              -- Unsupported ftype.

--              -- REMARK: Discard this packet.

--          end case;

-- tt=00

-- 0: header(15:0);dest(7:0);src(7:0);

-- 1: transaction(3:0)

-- shifter: 32 (32 empty)

-- tt=01

-- 0: header(15:0);dest(15:0);

-- 1: src(15:0);transaction(3:0)

-- shifter: 16 (48 empty)

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.rio_common.all;

entity RioLogicalCommon is

  port(

    clk : in std_logic;

    areset_n : in std_logic;

    enable : in std_logic;

    readFrameEmpty_i : in std_logic;

    readFrame_o : out std_logic;

    readContent_o : out std_logic;

    readContentEnd_i : in std_logic;

    readContentData_i : in std_logic_vector(31 downto 0);

    writeFrameFull_i : in std_logic;

    writeFrame_o : out std_logic;

    writeFrameAbort_o : out std_logic;

    writeContent_o : out std_logic;

    writeContentData_o : out std_logic_vector(31 downto 0);

    masterCyc_o : out std_logic;

    masterStb_o : out std_logic;

    masterAdr_o : out std_logic_vector(7 downto 0);

    masterDat_o : out std_logic_vector(31 downto 0);

    masterAck_i : in std_logic;

    slaveCyc_i : in std_logic;

    slaveStb_i : in std_logic;

    slaveDat_i : in std_logic_vector(31 downto 0);

    slaveAck_o : out std_logic;

    configStb_o : out std_logic;

    configWe_o : out std_logic;

    configAdr_o : out std_logic_vector(23 downto 0);

    configSel_o : out std_logic_vector(7 downto 0);

    configDat_o : out std_logic_vector(63 downto 0);

    configDat_i : in std_logic_vector(63 downto 0);

    configAck_i : in std_logic);

end entity;

architecture RioLogicalCommon of RioLogicalCommon is

  component RioLogicalCommonIngress is

    port(

      clk : in std_logic;

      areset_n : in std_logic;

      readFrameEmpty_i : in std_logic;

      readFrame_o : out std_logic;

      readContent_o : out std_logic;

      readContentEnd_i : in std_logic;

      readContentData_i : in std_logic_vector(31 downto 0);

      masterCyc_o : out std_logic;

      masterStb_o : out std_logic;

      masterAdr_o : out std_logic_vector(7 downto 0);

      masterDat_o : out std_logic_vector(31 downto 0);

      masterAck_i : in std_logic);

  end component;

  component RioLogicalCommonEgress is

    port(

      clk : in std_logic;

      areset_n : in std_logic;

      writeFrameFull_i : in std_logic;

      writeFrame_o : out std_logic;

      writeFrameAbort_o : out std_logic;

      writeContent_o : out std_logic;

      writeContentData_o : out std_logic_vector(31 downto 0);

      slaveCyc_i : in std_logic;

      slaveStb_i : in std_logic;

      slaveDat_i : in std_logic_vector(31 downto 0);

      slaveAck_o : out std_logic);

  end component;

  component RioLogicalMaintenance is

    port(

      clk : in std_logic;

      areset_n : in std_logic;

      enable : in std_logic;

      configStb_o : out std_logic;

      configWe_o : out std_logic;

      configAdr_o : out std_logic_vector(23 downto 0);

      configDat_o : out std_logic_vector(63 downto 0);

      configSel_o : out std_logic_vector(7 downto 0);

      configDat_i : in std_logic_vector(63 downto 0);

      configAck_i : in std_logic;

      slaveCyc_i : in std_logic;

      slaveStb_i : in std_logic;

      slaveAdr_i : in std_logic_vector(7 downto 0);

      slaveDat_i : in std_logic_vector(31 downto 0);

      slaveAck_o : out std_logic;

      masterCyc_o : out std_logic;

      masterStb_o : out std_logic;

      masterDat_o : out std_logic_vector(31 downto 0);

      masterAck_i : in std_logic);

  end component;

begin

  masterCyc_o <= masterCyc;

  masterStb_o <= masterStb;

  masterDat_o <= masterDat;

  masterAck_i <= masterAck;

  slaveCyc_i <= slaveCyc;

  slaveStb_i <= slaveStb;

  slaveAdr_i <= slaveAdr;

  slaveDat_i <= slaveDat;

  slaveAck_o <= slaveAck or maintenanceAck;

  LogicalMaintenance: RioLogicalMaintenance

    port map(

      clk=>clk, areset_n=>areset_n, enable=>enable,

      configStb_o=>configStb_o,

      configWe_o=>configWe_o,

      configAdr_o=>configAdr_o,

      configDat_o=>configDat_o,

      configSel_o=>configSel_o,

      configDat_i=>configDat_i,

      configAck_i=>configAck_i,

      slaveCyc_i=>slaveCyc,

      slaveStb_i=>slaveStb,

      slaveAdr_i=>slaveAdr,

      slaveDat_i=>slaveDat,

      slaveAck_o=>maintenanceAck,

      masterCyc_o=>masterCyc,

      masterStb_o=>masterStb,

      masterDat_o=>masterDat,

      masterAck_i=>masterAck);

  -- REMARK: Add interconnect for master signals...

  Ingress: RioLogicalCommonIngress

    port map(

      clk=>clk, areset_n=>areset_n,

      readFrameEmpty_i=>readFrameEmpty_i,

      readFrame_o=>readFrame_o,

      readContent_o=>readContent_o,

      readContentEnd_i=>readContentEnd_i,

      readContentData_i=>readContentData_i,

      masterCyc_o=>masterCyc,

      masterStb_o=>masterStb,

      masterAdr_o=>masterAdr,

      masterDat_o=>masterDat,

      masterAck_i=>masterAck);

  Egress: RioLogicalCommonEgress

    port map(

      clk=>clk, areset_n=>areset_n,

      writeFrameFull_i=>writeFrameFull_i,

      writeFrame_o=>writeFrame_o,

      writeFrameAbort_o=>writeFrameAbort_o,

      writeContent_o=>writeContent_o,

      writeContentData_o=>writeContentData_o,

      slaveCyc_i=>slaveCyc,

      slaveStb_i=>slaveStb,

      slaveDat_i=>slaveDat,

      slaveAck_o=>slaveAck);

end architecture;

-------------------------------------------------------------------------------

-- RioLogicalCommonIngress.

-------------------------------------------------------------------------------

-- REMARK: Check the destination address to see if it matches the one configured???

-- REMARK: Remove the acknowledge on all accesses on the master bus.

-- REMARK: Add component declarations to riocommon.vhd.

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.rio_common.all;

-------------------------------------------------------------------------------

-- Entity for RioLogicalCommonIngress.

-------------------------------------------------------------------------------

entity RioLogicalCommonIngress is

  port(

    clk : in std_logic;

    areset_n : in std_logic;

    readFrameEmpty_i : in std_logic;

    readFrame_o : out std_logic;

    readContent_o : out std_logic;

    readContentEnd_i : in std_logic;

    readContentData_i : in std_logic_vector(31 downto 0);

    masterCyc_o : out std_logic;

    masterStb_o : out std_logic;

    masterAdr_o : out std_logic_vector(7 downto 0);

    masterDat_o : out std_logic_vector(31 downto 0);

    masterAck_i : in std_logic);

end entity;

-------------------------------------------------------------------------------

-- 

-------------------------------------------------------------------------------

architecture RioLogicalCommonIngress of RioLogicalCommonIngress is

  type StateType is (IDLE,

                     WAIT_HEADER_0, HEADER_0, HEADER_1,

                     SEND_HEADER, SEND_DESTINATION, SEND_SOURCE,

                     FORWARD_SHORT, FORWARD_CRC, FORWARD_LONG, FORWARD_LAST,

                     END_PACKET);

  signal state : StateType;

  signal packetPosition : natural range 0 to 32;

  signal packetContent : std_logic_vector(63 downto 0);

  signal tt : std_logic_vector(1 downto 0);

  signal ftype : std_logic_vector(3 downto 0);

  signal transaction : std_logic_vector(3 downto 0);

begin

  process(clk, areset_n)

  begin

    if (areset_n = '0') then

      state <= IDLE;

      packetPosition <= 0;

      packetContent <= (others=>'0');

      tt <= "00";

      ftype <= "0000";

      transaction <= "0000";

    elsif (clk'event and clk = '1') then

      readContent_o <= '0';

      case state is

        when IDLE =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          packetPosition <= 0;

          if (readFrameEmpty_i = '0') then

            readContent_o <= '1';

            state <= WAIT_HEADER_0;

          end if;

        when WAIT_HEADER_0 =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          readContent_o <= '1';

          state <= HEADER_0;

        when HEADER_0 =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          packetContent <= packetContent(31 downto 0) & readContentData_i;

          packetPosition <= packetPosition + 1;

          readContent_o <= '1';

          tt <= readContentData_i(21 downto 20);

          ftype <= readContentData_i(19 downto 16);

          state <= HEADER_1;

        when HEADER_1 =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          packetContent <= packetContent(31 downto 0) & readContentData_i;

          packetPosition <= packetPosition + 1;

          if (tt = "00") then

            transaction <= readContentData_i(31 downto 28);

          elsif (tt = "01") then

            transaction <= readContentData_i(15 downto 12);

          end if;

          state <= SEND_HEADER;

        when SEND_HEADER =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          masterStb_o <= '1';

          masterAdr_o <= ftype & transaction;

          masterDat_o <= x"0000" & packetContent(63 downto 48);

          packetContent <= packetContent(47 downto 0) & x"0000";

          state <= SEND_DESTINATION;

        when SEND_DESTINATION =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          if (masterAck_i = '1') then

            if (tt = "00") then

              masterDat_o <= x"000000" & packetContent(63 downto 56);

              packetContent <= packetContent(55 downto 0) & x"00";

            elsif (tt = "01") then

              masterDat_o <= x"0000" & packetContent(63 downto 48);

              packetContent <= packetContent(31 downto 0) & readContentData_i;

              readContent_o <= '1';

            end if;

            state <= SEND_SOURCE;

          end if;

        when SEND_SOURCE =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          if (masterAck_i = '1') then

            if (tt = "00") then

              masterDat_o <= x"000000" & packetContent(63 downto 56);

              packetContent <= packetContent(55 downto 0) & x"00";

            elsif (tt = "01") then

              masterDat_o <= x"0000" & packetContent(63 downto 48);

              packetContent <= packetContent(47 downto 0) & x"0000";

            end if;

            state <= FORWARD_SHORT;

          end if;

        when FORWARD_SHORT =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          if (masterAck_i = '1') then

            masterDat_o <= packetContent(63 downto 32);

            packetPosition <= packetPosition + 1;

            packetContent <=

              packetContent(31 downto 0) & readContentData_i;

            if (readContentEnd_i = '0') then

              if (packetPosition = 20) then

                state <= FORWARD_CRC;

              end if;

              readContent_o <= '1';

            else

              readFrame_o <= '1';

              state <= FORWARD_LAST;

            end if;

          end if;

        when FORWARD_CRC =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          if (masterAck_i = '1') then

            masterDat_o <= packetContent(63 downto 32);

            packetPosition <= packetPosition + 1;

            packetContent <=

              packetContent(31 downto 0) & readContentData_i(15 downto 0) & x"0000";

            if (readContentEnd_i = '0') then

              readContent_o <= '1';

              state <= FORWARD_LONG;

            else

              readFrame_o <= '1';

              state <= FORWARD_LAST;

            end if;

          end if;

        when FORWARD_LONG =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          if (masterAck_i = '1') then

            masterDat_o <= packetContent(63 downto 32);

            packetPosition <= packetPosition + 1;

            packetContent <=

              packetContent(15 downto 0) & readContentData_i & x"0000";

            if (readContentEnd_i = '0') then

              readContent_o <= '1';

            else

              readFrame_o <= '1';

              state <= FORWARD_LAST;

            end if;

          end if;

        when FORWARD_LAST =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          -- REMARK: The last always contain the CRC?

          if (masterAck_i = '1') then

            masterDat_o <= packetContent(63 downto 32);

            state <= END_PACKET;

          end if;

        when END_PACKET =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          if (masterAck_i = '1') then

            state <= IDLE;

          end if;

        when others =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          state <= IDLE;

      end case;

    end if;

  end process;

end architecture;

-------------------------------------------------------------------------------

-- RioLogicalCommonEgress.

-- Only 8-bit and 16-bit deviceId are supported. The first write must contain

-- the 16-bit header, the second write must contain the destination address and

-- the third must contain the source address.

-- CRC is calculated during the transfer and is inserted at byte 81 and 82 and

-- appended to the packet when it ends.

-------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.rio_common.all;

-------------------------------------------------------------------------------

-- Entity for RioLogicalCommonEgress.

-------------------------------------------------------------------------------

entity RioLogicalCommonEgress is

  port(

    clk : in std_logic;

    areset_n : in std_logic;

    writeFrameFull_i : in std_logic;

    writeFrame_o : out std_logic;

    writeFrameAbort_o : out std_logic;

    writeContent_o : out std_logic;

    writeContentData_o : out std_logic_vector(31 downto 0);

    slaveCyc_i : in std_logic;

    slaveStb_i : in std_logic;

    slaveDat_i : in std_logic_vector(31 downto 0);

    slaveAck_o : out std_logic);

end entity;

-------------------------------------------------------------------------------

-- Architecture for RioLogicalCommonEgress.

-------------------------------------------------------------------------------

architecture RioLogicalCommonEgress of RioLogicalCommonEgress is

  component Crc16CITT is

    port(

      d_i : in  std_logic_vector(15 downto 0);

      crc_i : in  std_logic_vector(15 downto 0);

      crc_o : out std_logic_vector(15 downto 0));

  end component;

  type StateType is (IDLE,

                     HEADER_GET, HEADER_ACK,

                     DESTINATION_GET, DESTINATION_ACK,

                     SOURCE_GET, SOURCE_ACK,

                     CONTENT_GET, CONTENT_ACK,

                     CRC_APPEND, SEND_FRAME,

                     RESTART_FRAME, WAIT_UPDATE);

  signal state : StateType;

  signal packetPosition : natural range 0 to 31;

  signal halfWordPending : std_logic;

  signal halfWord : std_logic_vector(15 downto 0);

  signal header : std_logic_vector(15 downto 0);

  signal tt : std_logic_vector(1 downto 0);

  signal dstAddr : std_logic_vector(31 downto 0);

  signal srcAddr : std_logic_vector(31 downto 0);

  signal crc16Current, crc16Temp, crc16Next: std_logic_vector(15 downto 0);

begin

  process(clk, areset_n)

  begin

    if (areset_n = '0') then

      state <= IDLE;

      crc16Current <= x"0000";

      writeContentData <= (others=>'0');

    elsif (clk'event and clk = '1') then

      writeContent_o <= '0';

      writeFrame_o <= '0';

      case state is

        when IDLE =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          packetPosition <= 0;

          if (writeFrameFull_i = '0') then

            state <= HEADER_GET;

            crc16Current <= x"ffff";

          end if;

        when HEADER_GET =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then

            -- REMARK: Only support the header in one position?

            if (slaveSelect_i = "1100") then

              header <= slaveData_i(31 downto 16);

              tt <= slaveData_i(21 downto 20);

            elsif (slaveSelect_i = "0110") then

              header <= slaveData_i(23 downto 8);

              tt <= slaveData_i(13 downto 12);

            elsif (slaveSelect_i = "0011") then

              header <= slaveData_i(15 downto 0);

              tt <= slaveData_i(5 downto 4);

            else

              -- REMARK: Not supported.

            end if;

            slaveAck_o <= '1';

            state <= HEADER_ACK;

          else

            state <= RESTART_FRAME;

          end if;

        when HEADER_ACK =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          slaveAck_o <= '0';

          state <= DESTINATION_GET;

        when DESTINATION_GET =>

          ---------------------------------------------------------------------

          -- 

          ---------------------------------------------------------------------

          if ((slaveCyc_i = '1') and (slaveStb_i = '1')) then

            -- REMARK: Only support the destination in one position?

            if (slaveSelect_i = "1000") and (tt = "00") then

              dstAddr <= slaveData_i(31 downto 24);

            elsif (slaveSelect_i = "0100") and (tt = "00") then