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magro732 |
-------------------------------------------------------------------------------
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--
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-- RapidIO IP Library Core
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--
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-- This file is part of the RapidIO IP library project
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-- http://www.opencores.org/cores/rio/
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--
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-- Description
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-- Contains a platform to build endpoints on.
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--
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-- To Do:
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-- -
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--
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-- Author(s):
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-- - Magnus Rosenius, magro732@opencores.org
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2013 Authors and OPENCORES.ORG
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- RioLogicalMaintenance
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-- This logical layer module handles ingress maintenance requests and converts
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-- them into accesses on a Wishbone compatible bus accessing the configuration
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-- space.
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-- Addresses: 0x80 (maint read request) and 0x81 (maint write request).
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rio_common.all;
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-------------------------------------------------------------------------------
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-- Entity for RioLogicalMaintenance.
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-------------------------------------------------------------------------------
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entity RioLogicalMaintenance is
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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enable : in std_logic;
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configStb_o : out std_logic;
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configWe_o : out std_logic;
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configAdr_o : out std_logic_vector(21 downto 0);
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configDat_o : out std_logic_vector(31 downto 0);
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configDat_i : in std_logic_vector(31 downto 0);
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configAck_i : in std_logic;
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slaveCyc_i : in std_logic;
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slaveStb_i : in std_logic;
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slaveAdr_i : in std_logic_vector(7 downto 0);
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slaveDat_i : in std_logic_vector(31 downto 0);
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slaveAck_o : out std_logic;
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masterCyc_o : out std_logic;
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masterStb_o : out std_logic;
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masterDat_o : out std_logic_vector(31 downto 0);
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masterAck_i : in std_logic);
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end entity;
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-------------------------------------------------------------------------------
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--
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-------------------------------------------------------------------------------
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architecture RioLogicalMaintenance of RioLogicalMaintenance is
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component MaintenanceRequestInbound is
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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enable : in std_logic;
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requestReadReady_o : out std_logic;
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requestWriteReady_o : out std_logic;
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requestVc_o : out std_logic;
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requestCrf_o : out std_logic;
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requestPrio_o : out std_logic_vector(1 downto 0);
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requestTt_o : out std_logic_vector(1 downto 0);
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requestDstId_o : out std_logic_vector(31 downto 0);
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requestSrcId_o : out std_logic_vector(31 downto 0);
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requestTid_o : out std_logic_vector(7 downto 0);
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requestOffset_o : out std_logic_vector(20 downto 0);
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requestWdptr_o : out std_logic;
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requestPayloadLength_o : out std_logic_vector(3 downto 0);
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requestPayloadIndex_i : in std_logic_vector(3 downto 0);
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requestPayload_o : out std_logic_vector(31 downto 0);
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requestDone_i : in std_logic;
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slaveCyc_i : in std_logic;
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slaveStb_i : in std_logic;
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slaveAdr_i : in std_logic_vector(7 downto 0);
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slaveDat_i : in std_logic_vector(31 downto 0);
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slaveAck_o : out std_logic);
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end component;
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component MaintenanceResponseOutbound is
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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enable : in std_logic;
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responseReadReady_i : in std_logic;
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responseWriteReady_i : in std_logic;
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responseVc_i : in std_logic;
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responseCrf_i : in std_logic;
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responsePrio_i : in std_logic_vector(1 downto 0);
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responseTt_i : in std_logic_vector(1 downto 0);
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responseDstId_i : in std_logic_vector(31 downto 0);
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responseSrcId_i : in std_logic_vector(31 downto 0);
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responseTid_i : in std_logic_vector(7 downto 0);
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responseWdptr_i : in std_logic;
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responsePayloadLength_i : in std_logic_vector(3 downto 0);
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responsePayloadWrite_i : in std_logic;
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responsePayloadIndex_i : in std_logic_vector(3 downto 0);
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responsePayload_i : in std_logic_vector(31 downto 0);
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responseDone_o : out std_logic;
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masterCyc_o : out std_logic;
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masterStb_o : out std_logic;
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masterDat_o : out std_logic_vector(31 downto 0);
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masterAck_i : in std_logic);
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end component;
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type StateType is (IDLE,
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CONFIG_READ, CONFIG_READ_RESPONSE,
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CONFIG_WRITE, CONFIG_WRITE_RESPONSE);
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signal state : StateType;
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signal vc : std_logic;
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signal crf : std_logic;
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signal prio : std_logic_vector(1 downto 0);
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signal tt : std_logic_vector(1 downto 0);
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signal dstId : std_logic_vector(31 downto 0);
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signal srcId : std_logic_vector(31 downto 0);
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signal tid : std_logic_vector(7 downto 0);
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signal wdptr : std_logic;
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signal configAdr : std_logic_vector(21 downto 0);
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signal configDat : std_logic_vector(31 downto 0);
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signal requestReadReady : std_logic;
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signal requestWriteReady : std_logic;
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signal requestOffset : std_logic_vector(20 downto 0);
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signal requestPayloadLength : std_logic_vector(3 downto 0);
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signal requestPayloadIndex : std_logic_vector(3 downto 0);
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signal requestPayload : std_logic_vector(31 downto 0);
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signal requestDone : std_logic;
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signal responseReadReady : std_logic;
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signal responseWriteReady : std_logic;
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signal responsePayloadWrite : std_logic;
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signal responsePayloadIndex : std_logic_vector(3 downto 0);
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signal responseDone : std_logic;
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begin
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configAdr_o <= configAdr;
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configDat_o <= configDat;
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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Maintenance: process(clk, areset_n)
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begin
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if (areset_n = '0') then
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configStb_o <= '0';
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configWe_o <= '0';
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configAdr <= (others=>'0');
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configDat <= (others=>'0');
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responseReadReady <= '0';
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responseWriteReady <= '0';
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responsePayloadWrite <= '0';
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requestDone <= '0';
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requestPayloadIndex <= (others=>'0');
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elsif (clk'event and clk = '1') then
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requestDone <= '0';
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responsePayloadWrite <= '0';
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if (responsePayloadWrite = '1') then
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responsePayloadIndex <= std_logic_vector(unsigned(responsePayloadIndex) + 1);
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end if;
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case state is
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when IDLE =>
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---------------------------------------------------------------------
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--
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---------------------------------------------------------------------
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responsePayloadIndex <= (others=>'0');
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if (requestReadReady = '1') then
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configStb_o <= '1';
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configWe_o <= '0';
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configAdr <= requestOffset & wdptr;
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state <= CONFIG_READ;
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elsif (requestWriteReady = '1') then
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configStb_o <= '1';
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configWe_o <= '1';
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configAdr <= requestOffset & wdptr;
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configDat <= requestPayload;
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requestPayloadIndex <= std_logic_vector(unsigned(requestPayloadIndex) + 1);
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state <= CONFIG_WRITE;
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else
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responsePayloadIndex <= (others=>'0');
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requestPayloadIndex <= (others=>'0');
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end if;
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when CONFIG_READ =>
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---------------------------------------------------------------------
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--
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---------------------------------------------------------------------
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if (configAck_i = '1') then
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responsePayloadWrite <= '1';
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if (responsePayloadIndex /= requestPayloadLength) then
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configAdr <= std_logic_vector(unsigned(configAdr) + 1);
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else
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requestDone <= '1';
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configStb_o <= '0';
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state <= CONFIG_READ_RESPONSE;
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end if;
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end if;
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when CONFIG_READ_RESPONSE =>
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---------------------------------------------------------------------
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--
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---------------------------------------------------------------------
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if (responseDone = '1') then
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responseReadReady <= '0';
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state <= IDLE;
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else
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responseReadReady <= '1';
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end if;
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when CONFIG_WRITE =>
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---------------------------------------------------------------------
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--
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---------------------------------------------------------------------
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if (configAck_i = '1') then
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responsePayloadWrite <= '1';
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if (responsePayloadIndex /= requestPayloadLength) then
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configAdr <= std_logic_vector(unsigned(configAdr) + 1);
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configDat <= requestPayload;
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requestPayloadIndex <= std_logic_vector(unsigned(requestPayloadIndex) + 1);
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else
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requestDone <= '1';
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configStb_o <= '0';
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state <= CONFIG_WRITE_RESPONSE;
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end if;
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end if;
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when CONFIG_WRITE_RESPONSE =>
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---------------------------------------------------------------------
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--
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---------------------------------------------------------------------
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if (responseDone = '1') then
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responseWriteReady <= '0';
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state <= IDLE;
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else
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responseWriteReady <= '1';
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end if;
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when others =>
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end case;
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end if;
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end process;
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-----------------------------------------------------------------------------
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-- Request packet handler.
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-----------------------------------------------------------------------------
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RequestInbound: MaintenanceRequestInbound
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port map(
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clk=>clk,
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areset_n=>areset_n,
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enable=>enable,
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requestReadReady_o=>requestReadReady,
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requestWriteReady_o=>requestWriteReady,
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requestVc_o=>vc,
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requestCrf_o=>crf,
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requestPrio_o=>prio,
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requestTt_o=>tt,
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requestDstId_o=>dstId,
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requestSrcId_o=>srcId,
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311 |
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requestTid_o=>tid,
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requestOffset_o=>requestOffset,
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requestWdptr_o=>wdptr,
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requestPayloadLength_o=>requestPayloadLength,
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requestPayloadIndex_i=>requestPayloadIndex,
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requestPayload_o=>requestPayload,
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317 |
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requestDone_i=>requestDone,
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318 |
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slaveCyc_i=>slaveCyc_i,
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slaveStb_i=>slaveStb_i,
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slaveAdr_i=>slaveAdr_i,
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321 |
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slaveDat_i=>slaveDat_i,
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slaveAck_o=>slaveAck_o);
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323 |
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-----------------------------------------------------------------------------
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325 |
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-- Response packet handler.
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326 |
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-----------------------------------------------------------------------------
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327 |
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-- Note that the dstId and srcId is flipped since the response should be
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328 |
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-- returned to the source.
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329 |
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ResponseOutbound: MaintenanceResponseOutbound
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330 |
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port map(
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clk=>clk, areset_n=>areset_n, enable=>enable,
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332 |
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responseReadReady_i=>responseReadReady,
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333 |
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responseWriteReady_i=>responseWriteReady,
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334 |
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responseVc_i=>vc,
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responseCrf_i=>crf,
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336 |
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responsePrio_i=>prio,
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337 |
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responseTt_i=>tt,
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338 |
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responseDstId_i=>srcId,
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339 |
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responseSrcId_i=>dstId,
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340 |
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responseTid_i=>tid,
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341 |
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responseWdptr_i=>wdptr,
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responsePayloadLength_i=>requestPayloadLength,
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responsePayloadWrite_i=>responsePayloadWrite,
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344 |
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responsePayloadIndex_i=>responsePayloadIndex,
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345 |
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responsePayload_i=>configDat_i,
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responseDone_o=>responseDone,
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347 |
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masterCyc_o=>masterCyc_o,
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348 |
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masterStb_o=>masterStb_o,
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349 |
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masterDat_o=>masterDat_o,
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masterAck_i=>masterAck_i);
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351 |
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352 |
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end architecture;
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353 |
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354 |
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355 |
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|
-------------------------------------------------------------------------------
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356 |
|
|
--
|
357 |
|
|
-------------------------------------------------------------------------------
|
358 |
|
|
library ieee;
|
359 |
|
|
use ieee.std_logic_1164.all;
|
360 |
|
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use ieee.numeric_std.all;
|
361 |
|
|
use work.rio_common.all;
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362 |
|
|
|
363 |
|
|
|
364 |
|
|
-------------------------------------------------------------------------------
|
365 |
|
|
--
|
366 |
|
|
-------------------------------------------------------------------------------
|
367 |
|
|
entity MaintenanceRequestInbound is
|
368 |
|
|
port(
|
369 |
|
|
clk : in std_logic;
|
370 |
|
|
areset_n : in std_logic;
|
371 |
|
|
enable : in std_logic;
|
372 |
|
|
|
373 |
|
|
requestReadReady_o : out std_logic;
|
374 |
|
|
requestWriteReady_o : out std_logic;
|
375 |
|
|
requestVc_o : out std_logic;
|
376 |
|
|
requestCrf_o : out std_logic;
|
377 |
|
|
requestPrio_o : out std_logic_vector(1 downto 0);
|
378 |
|
|
requestTt_o : out std_logic_vector(1 downto 0);
|
379 |
|
|
requestDstId_o : out std_logic_vector(31 downto 0);
|
380 |
|
|
requestSrcId_o : out std_logic_vector(31 downto 0);
|
381 |
|
|
requestTid_o : out std_logic_vector(7 downto 0);
|
382 |
|
|
requestOffset_o : out std_logic_vector(20 downto 0);
|
383 |
|
|
requestWdptr_o : out std_logic;
|
384 |
|
|
requestPayloadLength_o : out std_logic_vector(3 downto 0);
|
385 |
|
|
requestPayloadIndex_i : in std_logic_vector(3 downto 0);
|
386 |
|
|
requestPayload_o : out std_logic_vector(31 downto 0);
|
387 |
|
|
requestDone_i : in std_logic;
|
388 |
|
|
|
389 |
|
|
slaveCyc_i : in std_logic;
|
390 |
|
|
slaveStb_i : in std_logic;
|
391 |
|
|
slaveAdr_i : in std_logic_vector(7 downto 0);
|
392 |
|
|
slaveDat_i : in std_logic_vector(31 downto 0);
|
393 |
|
|
slaveAck_o : out std_logic);
|
394 |
|
|
end entity;
|
395 |
|
|
|
396 |
|
|
|
397 |
|
|
-------------------------------------------------------------------------------
|
398 |
|
|
--
|
399 |
|
|
-------------------------------------------------------------------------------
|
400 |
|
|
architecture MaintenanceRequestInbound of MaintenanceRequestInbound is
|
401 |
|
|
component MemorySimpleDualPort
|
402 |
|
|
generic(
|
403 |
|
|
ADDRESS_WIDTH : natural := 1;
|
404 |
|
|
DATA_WIDTH : natural := 1);
|
405 |
|
|
port(
|
406 |
|
|
clkA_i : in std_logic;
|
407 |
|
|
enableA_i : in std_logic;
|
408 |
|
|
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
409 |
|
|
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
410 |
|
|
|
411 |
|
|
clkB_i : in std_logic;
|
412 |
|
|
enableB_i : in std_logic;
|
413 |
|
|
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
414 |
|
|
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
415 |
|
|
end component;
|
416 |
|
|
|
417 |
|
|
type StateType is (RECEIVE_PACKET, READY);
|
418 |
|
|
signal state : StateType;
|
419 |
|
|
|
420 |
|
|
signal wdptr : std_logic;
|
421 |
|
|
signal size : std_logic_vector(3 downto 0);
|
422 |
|
|
signal words : natural range 0 to 32;
|
423 |
|
|
|
424 |
|
|
signal slaveAck : std_logic;
|
425 |
|
|
signal maintReadComplete : std_logic;
|
426 |
|
|
signal maintWriteComplete : std_logic;
|
427 |
|
|
|
428 |
|
|
signal packetIndex : natural range 0 to 33;
|
429 |
|
|
signal requestData : std_logic_vector(31 downto 0);
|
430 |
|
|
|
431 |
|
|
signal memoryWrite : std_logic;
|
432 |
|
|
signal memoryAddress : std_logic_vector(3 downto 0);
|
433 |
|
|
signal memoryDataIn : std_logic_vector(31 downto 0);
|
434 |
|
|
|
435 |
|
|
begin
|
436 |
|
|
|
437 |
|
|
slaveAck_o <= slaveAck;
|
438 |
|
|
|
439 |
|
|
requestReadReady_o <= maintReadComplete when (state = READY) else '0';
|
440 |
|
|
requestWriteReady_o <= maintWriteComplete when (state = READY) else '0';
|
441 |
|
|
|
442 |
|
|
MaintenanceRequest: process(clk, areset_n)
|
443 |
|
|
begin
|
444 |
|
|
if (areset_n = '0') then
|
445 |
|
|
slaveAck <= '0';
|
446 |
|
|
|
447 |
|
|
maintReadComplete <= '0';
|
448 |
|
|
maintWriteComplete <= '0';
|
449 |
|
|
|
450 |
|
|
requestVc_o <= '0';
|
451 |
|
|
requestCrf_o <= '0';
|
452 |
|
|
requestPrio_o <= "00";
|
453 |
|
|
requestTt_o <= "00";
|
454 |
|
|
requestOffset_o <= (others=>'0');
|
455 |
|
|
|
456 |
|
|
wdptr <= '0';
|
457 |
|
|
size <= (others=>'0');
|
458 |
|
|
|
459 |
|
|
packetIndex <= 0;
|
460 |
|
|
memoryWrite <= '0';
|
461 |
|
|
memoryAddress <= (others=>'0');
|
462 |
|
|
memoryDataIn <= (others=>'0');
|
463 |
|
|
elsif (clk'event and clk = '1') then
|
464 |
|
|
case state is
|
465 |
|
|
when RECEIVE_PACKET =>
|
466 |
|
|
---------------------------------------------------------------------
|
467 |
|
|
-- This state waits for a new maintenance request packet, receives it
|
468 |
|
|
-- and parses it.
|
469 |
|
|
---------------------------------------------------------------------
|
470 |
|
|
if (slaveCyc_i = '1') then
|
471 |
|
|
if (slaveAck = '0') then
|
472 |
|
|
if (slaveStb_i = '1') then
|
473 |
|
|
if (slaveAdr_i = x"80") then
|
474 |
|
|
-------------------------------------------------------------
|
475 |
|
|
-- Maintenance Read Request packet parser.
|
476 |
|
|
-------------------------------------------------------------
|
477 |
|
|
case (packetIndex) is
|
478 |
|
|
when 0 =>
|
479 |
|
|
-- x"0000" & ackid & vc & crf & prio & tt & ftype
|
480 |
|
|
requestVc_o <= slaveDat_i(9);
|
481 |
|
|
requestCrf_o <= slaveDat_i(8);
|
482 |
|
|
requestPrio_o <= slaveDat_i(7 downto 6);
|
483 |
|
|
requestTt_o <= slaveDat_i(5 downto 4);
|
484 |
|
|
packetIndex <= packetIndex + 1;
|
485 |
|
|
when 1 =>
|
486 |
|
|
-- destid
|
487 |
|
|
requestDstId_o <= slaveDat_i;
|
488 |
|
|
packetIndex <= packetIndex + 1;
|
489 |
|
|
when 2 =>
|
490 |
|
|
-- srcid
|
491 |
|
|
requestSrcId_o <= slaveDat_i;
|
492 |
|
|
packetIndex <= packetIndex + 1;
|
493 |
|
|
when 3 =>
|
494 |
|
|
-- transaction & rdsize & srcTID & hop & config_offset(20:13)
|
495 |
|
|
size <= slaveDat_i(27 downto 24);
|
496 |
|
|
requestTid_o <= slaveDat_i(23 downto 16);
|
497 |
|
|
requestOffset_o(20 downto 13) <= slaveDat_i(7 downto 0);
|
498 |
|
|
packetIndex <= packetIndex + 1;
|
499 |
|
|
when 4 =>
|
500 |
|
|
-- config_offset(12:0) & wdptr & rsrv & crc(15:0)
|
501 |
|
|
requestOffset_o(12 downto 0) <= slaveDat_i(31 downto 19);
|
502 |
|
|
wdptr <= slaveDat_i(18);
|
503 |
|
|
packetIndex <= packetIndex + 1;
|
504 |
|
|
maintReadComplete <= '1';
|
505 |
|
|
when others =>
|
506 |
|
|
-- There should be no more content in a maintenance read request.
|
507 |
|
|
-- Discard.
|
508 |
|
|
end case;
|
509 |
|
|
elsif (slaveAdr_i = x"81") then
|
510 |
|
|
-------------------------------------------------------------
|
511 |
|
|
-- Maintenance Write Request packet parser.
|
512 |
|
|
-------------------------------------------------------------
|
513 |
|
|
case (packetIndex) is
|
514 |
|
|
when 0 =>
|
515 |
|
|
-- x"0000" & ackid & vc & crf & prio & tt & ftype
|
516 |
|
|
requestVc_o <= slaveDat_i(9);
|
517 |
|
|
requestCrf_o <= slaveDat_i(8);
|
518 |
|
|
requestPrio_o <= slaveDat_i(7 downto 6);
|
519 |
|
|
requestTt_o <= slaveDat_i(5 downto 4);
|
520 |
|
|
packetIndex <= packetIndex + 1;
|
521 |
|
|
when 1 =>
|
522 |
|
|
-- destId
|
523 |
|
|
requestDstId_o <= slaveDat_i;
|
524 |
|
|
packetIndex <= packetIndex + 1;
|
525 |
|
|
when 2 =>
|
526 |
|
|
-- srcId
|
527 |
|
|
requestSrcId_o <= slaveDat_i;
|
528 |
|
|
packetIndex <= packetIndex + 1;
|
529 |
|
|
when 3 =>
|
530 |
|
|
-- transaction & wrsize & srcTID & hop & config_offset(20:13)
|
531 |
|
|
size <= slaveDat_i(27 downto 24);
|
532 |
|
|
requestTid_o <= slaveDat_i(23 downto 16);
|
533 |
|
|
requestOffset_o(20 downto 13) <= slaveDat_i(7 downto 0);
|
534 |
|
|
packetIndex <= packetIndex + 1;
|
535 |
|
|
when 4 =>
|
536 |
|
|
-- config_offset(12:0) & wdptr & rsrv & double-word(63:48)
|
537 |
|
|
requestOffset_o(12 downto 0) <= slaveDat_i(31 downto 19);
|
538 |
|
|
wdptr <= slaveDat_i(18);
|
539 |
|
|
requestData(31 downto 16) <= slaveDat_i(15 downto 0);
|
540 |
|
|
packetIndex <= packetIndex + 1;
|
541 |
|
|
when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 =>
|
542 |
|
|
-- double-word(47:16)
|
543 |
|
|
requestData(31 downto 16) <= slaveDat_i(15 downto 0);
|
544 |
|
|
packetIndex <= packetIndex + 1;
|
545 |
|
|
|
546 |
|
|
if (not ((size = "1000") and (wdptr = '1'))) then
|
547 |
|
|
memoryWrite <= '1';
|
548 |
|
|
memoryDataIn <= requestData(31 downto 16) & slaveDat_i(31 downto 16);
|
549 |
|
|
end if;
|
550 |
|
|
when 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32 =>
|
551 |
|
|
-- double-word(15:0) & double-word(63:48)
|
552 |
|
|
requestData(31 downto 16) <= slaveDat_i(15 downto 0);
|
553 |
|
|
packetIndex <= packetIndex + 1;
|
554 |
|
|
|
555 |
|
|
memoryWrite <= '1';
|
556 |
|
|
memoryDataIn <= requestData(31 downto 16) & slaveDat_i(31 downto 16);
|
557 |
|
|
maintWriteComplete <= '1';
|
558 |
|
|
when others =>
|
559 |
|
|
-- There should be no more content in a maintenance write request.
|
560 |
|
|
-- Discard.
|
561 |
|
|
end case;
|
562 |
|
|
end if;
|
563 |
|
|
slaveAck <= '1';
|
564 |
|
|
end if;
|
565 |
|
|
else
|
566 |
|
|
if (memoryWrite = '1') then
|
567 |
|
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
568 |
|
|
end if;
|
569 |
|
|
|
570 |
|
|
memoryWrite <= '0';
|
571 |
|
|
slaveAck <= '0';
|
572 |
|
|
end if;
|
573 |
|
|
else
|
574 |
|
|
if (maintReadComplete = '1') or (maintWriteComplete = '1') then
|
575 |
|
|
state <= READY;
|
576 |
|
|
end if;
|
577 |
|
|
packetIndex <= 0;
|
578 |
|
|
memoryAddress <= (others=>'0');
|
579 |
|
|
end if;
|
580 |
|
|
|
581 |
|
|
when READY =>
|
582 |
|
|
---------------------------------------------------------------------
|
583 |
|
|
-- Wait for the handler of the packet to signal that it has been
|
584 |
|
|
-- processed.
|
585 |
|
|
---------------------------------------------------------------------
|
586 |
|
|
if (requestDone_i = '1') then
|
587 |
|
|
maintReadComplete <= '0';
|
588 |
|
|
maintWriteComplete <= '0';
|
589 |
|
|
state <= RECEIVE_PACKET;
|
590 |
|
|
end if;
|
591 |
|
|
|
592 |
|
|
when others =>
|
593 |
|
|
---------------------------------------------------------------------
|
594 |
|
|
--
|
595 |
|
|
---------------------------------------------------------------------
|
596 |
|
|
|
597 |
|
|
end case;
|
598 |
|
|
end if;
|
599 |
|
|
end process;
|
600 |
|
|
|
601 |
|
|
-----------------------------------------------------------------------------
|
602 |
|
|
-- Transformation of rdsize/wrsize into length of access and byte lanes.
|
603 |
|
|
-----------------------------------------------------------------------------
|
604 |
|
|
|
605 |
|
|
process(clk, areset_n)
|
606 |
|
|
begin
|
607 |
|
|
if (areset_n = '0') then
|
608 |
|
|
requestPayloadLength_o <= (others=>'0');
|
609 |
|
|
requestWdptr_o <= '0';
|
610 |
|
|
elsif (clk'event and clk = '1') then
|
611 |
|
|
if (maintReadComplete = '1') or (maintWriteComplete = '1') then
|
612 |
|
|
if (wdptr = '0') then
|
613 |
|
|
case size is
|
614 |
|
|
when "1000" =>
|
615 |
|
|
-- Read 1 word.
|
616 |
|
|
requestPayloadLength_o <= "0000";
|
617 |
|
|
requestWdptr_o <= '0';
|
618 |
|
|
when "1011" =>
|
619 |
|
|
-- Read 2 words.
|
620 |
|
|
requestPayloadLength_o <= "0001";
|
621 |
|
|
requestWdptr_o <= '0';
|
622 |
|
|
when "1100" =>
|
623 |
|
|
-- Read 8 words.
|
624 |
|
|
requestPayloadLength_o <= "0111";
|
625 |
|
|
requestWdptr_o <= '0';
|
626 |
|
|
when others =>
|
627 |
|
|
-- REMARK: Not allowed for a maintenance packet.
|
628 |
|
|
requestPayloadLength_o <= "0000";
|
629 |
|
|
requestWdptr_o <= '0';
|
630 |
|
|
end case;
|
631 |
|
|
else
|
632 |
|
|
case size is
|
633 |
|
|
when "1000" =>
|
634 |
|
|
-- Read 1 word.
|
635 |
|
|
requestPayloadLength_o <= "0000";
|
636 |
|
|
requestWdptr_o <= '1';
|
637 |
|
|
when "1011" =>
|
638 |
|
|
-- Read 4 words.
|
639 |
|
|
requestPayloadLength_o <= "0011";
|
640 |
|
|
requestWdptr_o <= '0';
|
641 |
|
|
when "1100" =>
|
642 |
|
|
-- Read 16 words.
|
643 |
|
|
requestPayloadLength_o <= "1111";
|
644 |
|
|
requestWdptr_o <= '0';
|
645 |
|
|
when others =>
|
646 |
|
|
-- REMARK: Not allowed for a maintenance packet.
|
647 |
|
|
requestPayloadLength_o <= "0000";
|
648 |
|
|
requestWdptr_o <= '0';
|
649 |
|
|
end case;
|
650 |
|
|
end if;
|
651 |
|
|
end if;
|
652 |
|
|
end if;
|
653 |
|
|
end process;
|
654 |
|
|
|
655 |
|
|
-----------------------------------------------------------------------------
|
656 |
|
|
-- Payload content memory.
|
657 |
|
|
-----------------------------------------------------------------------------
|
658 |
|
|
PayloadMemory: MemorySimpleDualPort
|
659 |
|
|
generic map(ADDRESS_WIDTH=>4, DATA_WIDTH=>32)
|
660 |
|
|
port map(clkA_i=>clk,
|
661 |
|
|
enableA_i=>memoryWrite,
|
662 |
|
|
addressA_i=>memoryAddress,
|
663 |
|
|
dataA_i=>memoryDataIn,
|
664 |
|
|
clkB_i=>clk,
|
665 |
|
|
enableB_i=>enable,
|
666 |
|
|
addressB_i=>requestPayloadIndex_i,
|
667 |
|
|
dataB_o=>requestPayload_o);
|
668 |
|
|
|
669 |
|
|
end architecture;
|
670 |
|
|
|
671 |
|
|
|
672 |
|
|
-------------------------------------------------------------------------------
|
673 |
|
|
--
|
674 |
|
|
-------------------------------------------------------------------------------
|
675 |
|
|
library ieee;
|
676 |
|
|
use ieee.std_logic_1164.all;
|
677 |
|
|
use ieee.numeric_std.all;
|
678 |
|
|
use work.rio_common.all;
|
679 |
|
|
|
680 |
|
|
-------------------------------------------------------------------------------
|
681 |
|
|
--
|
682 |
|
|
-------------------------------------------------------------------------------
|
683 |
|
|
-- REMARK: Add handler for maintenance response with error also...
|
684 |
|
|
entity MaintenanceResponseOutbound is
|
685 |
|
|
port(
|
686 |
|
|
clk : in std_logic;
|
687 |
|
|
areset_n : in std_logic;
|
688 |
|
|
enable : in std_logic;
|
689 |
|
|
|
690 |
|
|
responseReadReady_i : in std_logic;
|
691 |
|
|
responseWriteReady_i : in std_logic;
|
692 |
|
|
responseVc_i : in std_logic;
|
693 |
|
|
responseCrf_i : in std_logic;
|
694 |
|
|
responsePrio_i : in std_logic_vector(1 downto 0);
|
695 |
|
|
responseTt_i : in std_logic_vector(1 downto 0);
|
696 |
|
|
responseDstId_i : in std_logic_vector(31 downto 0);
|
697 |
|
|
responseSrcId_i : in std_logic_vector(31 downto 0);
|
698 |
|
|
responseTid_i : in std_logic_vector(7 downto 0);
|
699 |
|
|
responseWdptr_i : in std_logic;
|
700 |
|
|
responsePayloadLength_i : in std_logic_vector(3 downto 0);
|
701 |
|
|
responsePayloadWrite_i : in std_logic;
|
702 |
|
|
responsePayloadIndex_i : in std_logic_vector(3 downto 0);
|
703 |
|
|
responsePayload_i : in std_logic_vector(31 downto 0);
|
704 |
|
|
responseDone_o : out std_logic;
|
705 |
|
|
|
706 |
|
|
masterCyc_o : out std_logic;
|
707 |
|
|
masterStb_o : out std_logic;
|
708 |
|
|
masterDat_o : out std_logic_vector(31 downto 0);
|
709 |
|
|
masterAck_i : in std_logic);
|
710 |
|
|
end entity;
|
711 |
|
|
|
712 |
|
|
|
713 |
|
|
-------------------------------------------------------------------------------
|
714 |
|
|
--
|
715 |
|
|
-------------------------------------------------------------------------------
|
716 |
|
|
architecture MaintenanceResponseOutbound of MaintenanceResponseOutbound is
|
717 |
|
|
component MemorySimpleDualPort
|
718 |
|
|
generic(
|
719 |
|
|
ADDRESS_WIDTH : natural := 1;
|
720 |
|
|
DATA_WIDTH : natural := 1);
|
721 |
|
|
port(
|
722 |
|
|
clkA_i : in std_logic;
|
723 |
|
|
enableA_i : in std_logic;
|
724 |
|
|
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
725 |
|
|
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
726 |
|
|
|
727 |
|
|
clkB_i : in std_logic;
|
728 |
|
|
enableB_i : in std_logic;
|
729 |
|
|
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
730 |
|
|
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
731 |
|
|
end component;
|
732 |
|
|
|
733 |
|
|
type StateType is (WAIT_PACKET,
|
734 |
|
|
READ_RESPONSE, WRITE_RESPONSE,
|
735 |
|
|
WAIT_COMPLETE, RESPONSE_DONE);
|
736 |
|
|
signal state : StateType;
|
737 |
|
|
|
738 |
|
|
signal packetIndex : natural range 0 to 33;
|
739 |
|
|
signal responseHeader : std_logic_vector(31 downto 0);
|
740 |
|
|
signal responsePayload : std_logic_vector(31 downto 0);
|
741 |
|
|
signal responsePayloadIndex : std_logic_vector(2 downto 0);
|
742 |
|
|
|
743 |
|
|
signal memoryEnable : std_logic;
|
744 |
|
|
signal memoryAddress : std_logic_vector(3 downto 0);
|
745 |
|
|
signal memoryDataRead : std_logic_vector(31 downto 0);
|
746 |
|
|
|
747 |
|
|
begin
|
748 |
|
|
|
749 |
|
|
responseHeader <=
|
750 |
|
|
x"0000" & "000000" & responseVc_i & responseCrf_i &
|
751 |
|
|
responsePrio_i & responseTt_i & x"8";
|
752 |
|
|
|
753 |
|
|
MaintenanceResponse: process(clk, areset_n)
|
754 |
|
|
begin
|
755 |
|
|
if (areset_n = '0') then
|
756 |
|
|
masterCyc_o <= '0';
|
757 |
|
|
masterStb_o <= '0';
|
758 |
|
|
|
759 |
|
|
memoryEnable <= '0';
|
760 |
|
|
memoryAddress <= (others=>'0');
|
761 |
|
|
|
762 |
|
|
responsePayloadIndex <= (others=>'0');
|
763 |
|
|
responseDone_o <= '0';
|
764 |
|
|
|
765 |
|
|
state <= WAIT_PACKET;
|
766 |
|
|
elsif (clk'event and clk = '1') then
|
767 |
|
|
if (enable = '1') then
|
768 |
|
|
case state is
|
769 |
|
|
when WAIT_PACKET =>
|
770 |
|
|
-------------------------------------------------------------------
|
771 |
|
|
--
|
772 |
|
|
-------------------------------------------------------------------
|
773 |
|
|
if (responseReadReady_i = '1') then
|
774 |
|
|
masterCyc_o <= '1';
|
775 |
|
|
masterStb_o <= '1';
|
776 |
|
|
masterDat_o <= responseHeader;
|
777 |
|
|
packetIndex <= 1;
|
778 |
|
|
memoryEnable <= '1';
|
779 |
|
|
memoryAddress <= (others=>'0');
|
780 |
|
|
responsePayloadIndex <= (others=>'0');
|
781 |
|
|
state <= READ_RESPONSE;
|
782 |
|
|
elsif (responseWriteReady_i = '1') then
|
783 |
|
|
masterCyc_o <= '1';
|
784 |
|
|
masterStb_o <= '1';
|
785 |
|
|
masterDat_o <= responseHeader;
|
786 |
|
|
packetIndex <= 1;
|
787 |
|
|
state <= WRITE_RESPONSE;
|
788 |
|
|
end if;
|
789 |
|
|
|
790 |
|
|
when READ_RESPONSE =>
|
791 |
|
|
---------------------------------------------------------------------
|
792 |
|
|
--
|
793 |
|
|
---------------------------------------------------------------------
|
794 |
|
|
if (masterAck_i = '1') then
|
795 |
|
|
case (packetIndex) is
|
796 |
|
|
when 1 =>
|
797 |
|
|
-- destination
|
798 |
|
|
masterDat_o <= responseDstId_i;
|
799 |
|
|
packetIndex <= packetIndex + 1;
|
800 |
|
|
when 2 =>
|
801 |
|
|
-- source
|
802 |
|
|
masterDat_o <= responseSrcId_i;
|
803 |
|
|
packetIndex <= packetIndex + 1;
|
804 |
|
|
when 3 =>
|
805 |
|
|
-- transaction & status & targetTID & hop & reserved(7:0)
|
806 |
|
|
masterDat_o <= "0010" & "0000" & responseTid_i & x"ff" & x"00";
|
807 |
|
|
packetIndex <= packetIndex + 1;
|
808 |
|
|
when 4 =>
|
809 |
|
|
-- reserved(15:0) & double-wordN(63:48)
|
810 |
|
|
if (responsePayloadLength_i = "0000") and (responseWdptr_i = '0') then
|
811 |
|
|
masterDat_o <= x"0000" & memoryDataRead(31 downto 16);
|
812 |
|
|
responsePayload(31 downto 16) <= memoryDataRead(15 downto 0);
|
813 |
|
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
814 |
|
|
elsif (responsePayloadLength_i = "0000") and (responseWdptr_i = '1') then
|
815 |
|
|
masterDat_o <= x"0000" & x"0000";
|
816 |
|
|
else
|
817 |
|
|
masterDat_o <= x"0000" & memoryDataRead(31 downto 16);
|
818 |
|
|
responsePayload(31 downto 16) <= memoryDataRead(15 downto 0);
|
819 |
|
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
820 |
|
|
end if;
|
821 |
|
|
packetIndex <= packetIndex + 1;
|
822 |
|
|
when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 =>
|
823 |
|
|
-- double-wordN(47:16)
|
824 |
|
|
if (responsePayloadLength_i = "0000") and (responseWdptr_i = '0') then
|
825 |
|
|
masterDat_o <= responsePayload(31 downto 16) & x"0000";
|
826 |
|
|
elsif (responsePayloadLength_i = "0000") and (responseWdptr_i = '1') then
|
827 |
|
|
masterDat_o <= x"0000" & memoryDataRead(31 downto 16);
|
828 |
|
|
responsePayload(31 downto 16) <= memoryDataRead(15 downto 0);
|
829 |
|
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
830 |
|
|
else
|
831 |
|
|
masterDat_o <=
|
832 |
|
|
responsePayload(31 downto 16) & memoryDataRead(31 downto 16);
|
833 |
|
|
responsePayload(31 downto 16) <= memoryDataRead(15 downto 0);
|
834 |
|
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
835 |
|
|
end if;
|
836 |
|
|
packetIndex <= packetIndex + 1;
|
837 |
|
|
when 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32 =>
|
838 |
|
|
-- double-wordN(15:0) & double-wordN(63:48)
|
839 |
|
|
if (responsePayloadLength_i = "0000") and (responseWdptr_i = '0') then
|
840 |
|
|
masterDat_o <= x"0000" & x"0000";
|
841 |
|
|
elsif (responsePayloadLength_i = "0000") and (responseWdptr_i = '1') then
|
842 |
|
|
masterDat_o <= responsePayload(31 downto 16) & x"0000";
|
843 |
|
|
else
|
844 |
|
|
if (responsePayloadIndex /= responsePayloadLength_i(3 downto 1)) then
|
845 |
|
|
masterDat_o <=
|
846 |
|
|
responsePayload(31 downto 16) & memoryDataRead(31 downto 16);
|
847 |
|
|
responsePayload(31 downto 16) <= memoryDataRead(15 downto 0);
|
848 |
|
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
849 |
|
|
else
|
850 |
|
|
masterDat_o <=
|
851 |
|
|
responsePayload(31 downto 16) & x"0000";
|
852 |
|
|
responsePayload(31 downto 16) <= memoryDataRead(15 downto 0);
|
853 |
|
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
854 |
|
|
end if;
|
855 |
|
|
end if;
|
856 |
|
|
|
857 |
|
|
responsePayloadIndex <=
|
858 |
|
|
std_logic_vector(unsigned(responsePayloadIndex) + 1);
|
859 |
|
|
|
860 |
|
|
if (responsePayloadIndex = responsePayloadLength_i(3 downto 1)) then
|
861 |
|
|
state <= WAIT_COMPLETE;
|
862 |
|
|
else
|
863 |
|
|
packetIndex <= packetIndex + 1;
|
864 |
|
|
end if;
|
865 |
|
|
when others =>
|
866 |
|
|
-- Unallowed response length.
|
867 |
|
|
-- Dont do anything.
|
868 |
|
|
end case;
|
869 |
|
|
end if;
|
870 |
|
|
|
871 |
|
|
when WRITE_RESPONSE =>
|
872 |
|
|
---------------------------------------------------------------------
|
873 |
|
|
--
|
874 |
|
|
---------------------------------------------------------------------
|
875 |
|
|
if (masterAck_i = '1') then
|
876 |
|
|
case (packetIndex) is
|
877 |
|
|
when 1 =>
|
878 |
|
|
-- destination
|
879 |
|
|
masterDat_o <= responseDstId_i;
|
880 |
|
|
packetIndex <= packetIndex + 1;
|
881 |
|
|
when 2 =>
|
882 |
|
|
-- source
|
883 |
|
|
masterDat_o <= responseSrcId_i;
|
884 |
|
|
packetIndex <= packetIndex + 1;
|
885 |
|
|
when 3 =>
|
886 |
|
|
-- transaction & status & targetTID & hop & reserved(7:0)
|
887 |
|
|
masterDat_o <= "0011" & "0000" & responseTid_i & x"ff" & x"00";
|
888 |
|
|
packetIndex <= packetIndex + 1;
|
889 |
|
|
when others =>
|
890 |
|
|
-- reserved(15:0) & crc(15:0)
|
891 |
|
|
masterDat_o <= x"00000000";
|
892 |
|
|
packetIndex <= packetIndex + 1;
|
893 |
|
|
state <= WAIT_COMPLETE;
|
894 |
|
|
end case;
|
895 |
|
|
end if;
|
896 |
|
|
|
897 |
|
|
when WAIT_COMPLETE =>
|
898 |
|
|
-------------------------------------------------------------------
|
899 |
|
|
--
|
900 |
|
|
-------------------------------------------------------------------
|
901 |
|
|
if (masterAck_i = '1') then
|
902 |
|
|
masterCyc_o <= '0';
|
903 |
|
|
masterStb_o <= '0';
|
904 |
|
|
state <= RESPONSE_DONE;
|
905 |
|
|
end if;
|
906 |
|
|
|
907 |
|
|
when RESPONSE_DONE =>
|
908 |
|
|
---------------------------------------------------------------------
|
909 |
|
|
--
|
910 |
|
|
---------------------------------------------------------------------
|
911 |
|
|
memoryEnable <= '0';
|
912 |
|
|
if (responseReadReady_i = '0') and (responseWriteReady_i = '0') then
|
913 |
|
|
state <= WAIT_PACKET;
|
914 |
|
|
responseDone_o <= '0';
|
915 |
|
|
else
|
916 |
|
|
responseDone_o <= '1';
|
917 |
|
|
end if;
|
918 |
|
|
|
919 |
|
|
when others =>
|
920 |
|
|
---------------------------------------------------------------------
|
921 |
|
|
--
|
922 |
|
|
---------------------------------------------------------------------
|
923 |
|
|
state <= WAIT_PACKET;
|
924 |
|
|
|
925 |
|
|
end case;
|
926 |
|
|
end if;
|
927 |
|
|
end if;
|
928 |
|
|
end process;
|
929 |
|
|
|
930 |
|
|
-----------------------------------------------------------------------------
|
931 |
|
|
-- Payload content memory.
|
932 |
|
|
-----------------------------------------------------------------------------
|
933 |
|
|
PayloadMemory: MemorySimpleDualPort
|
934 |
|
|
generic map(ADDRESS_WIDTH=>4, DATA_WIDTH=>32)
|
935 |
|
|
port map(clkA_i=>clk,
|
936 |
|
|
enableA_i=>responsePayloadWrite_i,
|
937 |
|
|
addressA_i=>responsePayloadIndex_i,
|
938 |
|
|
dataA_i=>responsePayload_i,
|
939 |
|
|
clkB_i=>clk,
|
940 |
|
|
enableB_i=>memoryEnable,
|
941 |
|
|
addressB_i=>memoryAddress,
|
942 |
|
|
dataB_o=>memoryDataRead);
|
943 |
|
|
|
944 |
|
|
end architecture;
|