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magro732 |
-------------------------------------------------------------------------------
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--
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-- RapidIO IP Library Core
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--
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-- This file is part of the RapidIO IP library project
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-- http://www.opencores.org/cores/rio/
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--
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-- Description
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-- Contains a platform to build endpoints on.
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--
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-- To Do:
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45 |
magro732 |
-- REMARK: Dont set complete before the packet is ready in inbound packet
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-- handler.
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-- REMARK: Add error indication if erronous sizes are received.
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magro732 |
--
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-- Author(s):
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-- - Magnus Rosenius, magro732@opencores.org
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2013 Authors and OPENCORES.ORG
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- RioLogicalMaintenance
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-- This logical layer module handles ingress maintenance requests and converts
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-- them into accesses on a Wishbone compatible bus accessing the configuration
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-- space.
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-- Addresses: 0x80 (maint read request) and 0x81 (maint write request).
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.rio_common.all;
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-------------------------------------------------------------------------------
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-- Entity for RioLogicalMaintenance.
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-------------------------------------------------------------------------------
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entity RioLogicalMaintenance is
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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enable : in std_logic;
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configStb_o : out std_logic;
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configWe_o : out std_logic;
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configAdr_o : out std_logic_vector(21 downto 0);
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configDat_o : out std_logic_vector(31 downto 0);
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configDat_i : in std_logic_vector(31 downto 0);
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configAck_i : in std_logic;
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magro732 |
inboundCyc_i : in std_logic;
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inboundStb_i : in std_logic;
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inboundAdr_i : in std_logic_vector(7 downto 0);
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inboundDat_i : in std_logic_vector(31 downto 0);
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inboundAck_o : out std_logic;
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magro732 |
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magro732 |
outboundCyc_o : out std_logic;
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outboundStb_o : out std_logic;
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outboundDat_o : out std_logic_vector(31 downto 0);
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outboundAck_i : in std_logic);
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magro732 |
end entity;
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-------------------------------------------------------------------------------
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--
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-------------------------------------------------------------------------------
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architecture RioLogicalMaintenance of RioLogicalMaintenance is
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component MaintenanceRequestInbound is
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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enable : in std_logic;
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requestReadReady_o : out std_logic;
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requestWriteReady_o : out std_logic;
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requestVc_o : out std_logic;
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requestCrf_o : out std_logic;
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requestPrio_o : out std_logic_vector(1 downto 0);
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requestTt_o : out std_logic_vector(1 downto 0);
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requestDstId_o : out std_logic_vector(31 downto 0);
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requestSrcId_o : out std_logic_vector(31 downto 0);
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requestTid_o : out std_logic_vector(7 downto 0);
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requestOffset_o : out std_logic_vector(20 downto 0);
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requestWdptr_o : out std_logic;
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requestPayloadLength_o : out std_logic_vector(3 downto 0);
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requestPayloadIndex_i : in std_logic_vector(3 downto 0);
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requestPayload_o : out std_logic_vector(31 downto 0);
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requestDone_i : in std_logic;
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magro732 |
inboundCyc_i : in std_logic;
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inboundStb_i : in std_logic;
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inboundAdr_i : in std_logic_vector(7 downto 0);
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inboundDat_i : in std_logic_vector(31 downto 0);
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inboundAck_o : out std_logic);
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magro732 |
end component;
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component MaintenanceResponseOutbound is
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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enable : in std_logic;
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responseReadReady_i : in std_logic;
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responseWriteReady_i : in std_logic;
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responseVc_i : in std_logic;
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responseCrf_i : in std_logic;
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responsePrio_i : in std_logic_vector(1 downto 0);
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responseTt_i : in std_logic_vector(1 downto 0);
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responseDstId_i : in std_logic_vector(31 downto 0);
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responseSrcId_i : in std_logic_vector(31 downto 0);
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responseTid_i : in std_logic_vector(7 downto 0);
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responseWdptr_i : in std_logic;
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responsePayloadLength_i : in std_logic_vector(3 downto 0);
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responsePayloadWrite_i : in std_logic;
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responsePayloadIndex_i : in std_logic_vector(3 downto 0);
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responsePayload_i : in std_logic_vector(31 downto 0);
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responseDone_o : out std_logic;
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magro732 |
outboundCyc_o : out std_logic;
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outboundStb_o : out std_logic;
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outboundDat_o : out std_logic_vector(31 downto 0);
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outboundAck_i : in std_logic);
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magro732 |
end component;
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type StateType is (IDLE,
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CONFIG_READ, CONFIG_READ_RESPONSE,
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CONFIG_WRITE, CONFIG_WRITE_RESPONSE);
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signal state : StateType;
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signal vc : std_logic;
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signal crf : std_logic;
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signal prio : std_logic_vector(1 downto 0);
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signal tt : std_logic_vector(1 downto 0);
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signal dstId : std_logic_vector(31 downto 0);
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signal srcId : std_logic_vector(31 downto 0);
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signal tid : std_logic_vector(7 downto 0);
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signal wdptr : std_logic;
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signal configAdr : std_logic_vector(21 downto 0);
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signal configDat : std_logic_vector(31 downto 0);
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signal requestReadReady : std_logic;
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signal requestWriteReady : std_logic;
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signal requestOffset : std_logic_vector(20 downto 0);
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signal requestPayloadLength : std_logic_vector(3 downto 0);
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signal requestPayloadIndex : std_logic_vector(3 downto 0);
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signal requestPayload : std_logic_vector(31 downto 0);
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signal requestDone : std_logic;
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signal responseReadReady : std_logic;
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signal responseWriteReady : std_logic;
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signal responsePayloadWrite : std_logic;
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signal responsePayloadIndex : std_logic_vector(3 downto 0);
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signal responseDone : std_logic;
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begin
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configAdr_o <= configAdr;
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configDat_o <= configDat;
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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Maintenance: process(clk, areset_n)
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begin
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if (areset_n = '0') then
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configStb_o <= '0';
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configWe_o <= '0';
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configAdr <= (others=>'0');
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configDat <= (others=>'0');
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responseReadReady <= '0';
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responseWriteReady <= '0';
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responsePayloadWrite <= '0';
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requestDone <= '0';
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requestPayloadIndex <= (others=>'0');
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elsif (clk'event and clk = '1') then
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requestDone <= '0';
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responsePayloadWrite <= '0';
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if (responsePayloadWrite = '1') then
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responsePayloadIndex <= std_logic_vector(unsigned(responsePayloadIndex) + 1);
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end if;
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case state is
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when IDLE =>
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---------------------------------------------------------------------
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--
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---------------------------------------------------------------------
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responsePayloadIndex <= (others=>'0');
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if (requestReadReady = '1') then
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configStb_o <= '1';
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configWe_o <= '0';
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configAdr <= requestOffset & wdptr;
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state <= CONFIG_READ;
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elsif (requestWriteReady = '1') then
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configStb_o <= '1';
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configWe_o <= '1';
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configAdr <= requestOffset & wdptr;
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configDat <= requestPayload;
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requestPayloadIndex <= std_logic_vector(unsigned(requestPayloadIndex) + 1);
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state <= CONFIG_WRITE;
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else
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responsePayloadIndex <= (others=>'0');
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requestPayloadIndex <= (others=>'0');
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end if;
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when CONFIG_READ =>
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---------------------------------------------------------------------
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--
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---------------------------------------------------------------------
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if (configAck_i = '1') then
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responsePayloadWrite <= '1';
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if (responsePayloadIndex /= requestPayloadLength) then
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configAdr <= std_logic_vector(unsigned(configAdr) + 1);
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else
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requestDone <= '1';
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configStb_o <= '0';
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state <= CONFIG_READ_RESPONSE;
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end if;
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end if;
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when CONFIG_READ_RESPONSE =>
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---------------------------------------------------------------------
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--
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254 |
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---------------------------------------------------------------------
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if (responseDone = '1') then
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256 |
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responseReadReady <= '0';
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state <= IDLE;
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else
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259 |
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responseReadReady <= '1';
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end if;
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261 |
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262 |
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when CONFIG_WRITE =>
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---------------------------------------------------------------------
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264 |
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--
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265 |
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---------------------------------------------------------------------
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266 |
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if (configAck_i = '1') then
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267 |
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responsePayloadWrite <= '1';
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268 |
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269 |
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if (responsePayloadIndex /= requestPayloadLength) then
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270 |
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configAdr <= std_logic_vector(unsigned(configAdr) + 1);
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271 |
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configDat <= requestPayload;
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272 |
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requestPayloadIndex <= std_logic_vector(unsigned(requestPayloadIndex) + 1);
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273 |
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else
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274 |
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requestDone <= '1';
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275 |
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configStb_o <= '0';
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276 |
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state <= CONFIG_WRITE_RESPONSE;
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277 |
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end if;
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278 |
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end if;
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279 |
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280 |
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when CONFIG_WRITE_RESPONSE =>
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281 |
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---------------------------------------------------------------------
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282 |
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--
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283 |
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---------------------------------------------------------------------
|
284 |
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if (responseDone = '1') then
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285 |
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responseWriteReady <= '0';
|
286 |
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state <= IDLE;
|
287 |
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else
|
288 |
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responseWriteReady <= '1';
|
289 |
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end if;
|
290 |
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291 |
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when others =>
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292 |
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293 |
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end case;
|
294 |
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end if;
|
295 |
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end process;
|
296 |
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297 |
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-----------------------------------------------------------------------------
|
298 |
|
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-- Request packet handler.
|
299 |
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-----------------------------------------------------------------------------
|
300 |
|
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RequestInbound: MaintenanceRequestInbound
|
301 |
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port map(
|
302 |
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clk=>clk,
|
303 |
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areset_n=>areset_n,
|
304 |
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enable=>enable,
|
305 |
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requestReadReady_o=>requestReadReady,
|
306 |
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requestWriteReady_o=>requestWriteReady,
|
307 |
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requestVc_o=>vc,
|
308 |
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requestCrf_o=>crf,
|
309 |
|
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requestPrio_o=>prio,
|
310 |
|
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requestTt_o=>tt,
|
311 |
|
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requestDstId_o=>dstId,
|
312 |
|
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requestSrcId_o=>srcId,
|
313 |
|
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requestTid_o=>tid,
|
314 |
|
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requestOffset_o=>requestOffset,
|
315 |
|
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requestWdptr_o=>wdptr,
|
316 |
|
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requestPayloadLength_o=>requestPayloadLength,
|
317 |
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requestPayloadIndex_i=>requestPayloadIndex,
|
318 |
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requestPayload_o=>requestPayload,
|
319 |
|
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requestDone_i=>requestDone,
|
320 |
45 |
magro732 |
inboundCyc_i=>inboundCyc_i,
|
321 |
|
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inboundStb_i=>inboundStb_i,
|
322 |
|
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inboundAdr_i=>inboundAdr_i,
|
323 |
|
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inboundDat_i=>inboundDat_i,
|
324 |
|
|
inboundAck_o=>inboundAck_o);
|
325 |
39 |
magro732 |
|
326 |
|
|
-----------------------------------------------------------------------------
|
327 |
|
|
-- Response packet handler.
|
328 |
|
|
-----------------------------------------------------------------------------
|
329 |
|
|
-- Note that the dstId and srcId is flipped since the response should be
|
330 |
|
|
-- returned to the source.
|
331 |
|
|
ResponseOutbound: MaintenanceResponseOutbound
|
332 |
|
|
port map(
|
333 |
|
|
clk=>clk, areset_n=>areset_n, enable=>enable,
|
334 |
|
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responseReadReady_i=>responseReadReady,
|
335 |
|
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responseWriteReady_i=>responseWriteReady,
|
336 |
|
|
responseVc_i=>vc,
|
337 |
|
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responseCrf_i=>crf,
|
338 |
|
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responsePrio_i=>prio,
|
339 |
|
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responseTt_i=>tt,
|
340 |
|
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responseDstId_i=>srcId,
|
341 |
|
|
responseSrcId_i=>dstId,
|
342 |
|
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responseTid_i=>tid,
|
343 |
|
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responseWdptr_i=>wdptr,
|
344 |
|
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responsePayloadLength_i=>requestPayloadLength,
|
345 |
|
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responsePayloadWrite_i=>responsePayloadWrite,
|
346 |
|
|
responsePayloadIndex_i=>responsePayloadIndex,
|
347 |
|
|
responsePayload_i=>configDat_i,
|
348 |
|
|
responseDone_o=>responseDone,
|
349 |
45 |
magro732 |
outboundCyc_o=>outboundCyc_o,
|
350 |
|
|
outboundStb_o=>outboundStb_o,
|
351 |
|
|
outboundDat_o=>outboundDat_o,
|
352 |
|
|
outboundAck_i=>outboundAck_i);
|
353 |
39 |
magro732 |
|
354 |
|
|
end architecture;
|
355 |
|
|
|
356 |
|
|
|
357 |
|
|
-------------------------------------------------------------------------------
|
358 |
|
|
--
|
359 |
|
|
-------------------------------------------------------------------------------
|
360 |
|
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library ieee;
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361 |
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use ieee.std_logic_1164.all;
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362 |
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use ieee.numeric_std.all;
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363 |
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use work.rio_common.all;
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364 |
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366 |
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-------------------------------------------------------------------------------
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367 |
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--
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368 |
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-------------------------------------------------------------------------------
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369 |
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entity MaintenanceRequestInbound is
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370 |
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port(
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371 |
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clk : in std_logic;
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372 |
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areset_n : in std_logic;
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373 |
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enable : in std_logic;
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374 |
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375 |
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requestReadReady_o : out std_logic;
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376 |
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requestWriteReady_o : out std_logic;
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377 |
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requestVc_o : out std_logic;
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378 |
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requestCrf_o : out std_logic;
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379 |
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requestPrio_o : out std_logic_vector(1 downto 0);
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380 |
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requestTt_o : out std_logic_vector(1 downto 0);
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381 |
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requestDstId_o : out std_logic_vector(31 downto 0);
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382 |
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requestSrcId_o : out std_logic_vector(31 downto 0);
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383 |
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requestTid_o : out std_logic_vector(7 downto 0);
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384 |
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requestOffset_o : out std_logic_vector(20 downto 0);
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385 |
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requestWdptr_o : out std_logic;
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386 |
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requestPayloadLength_o : out std_logic_vector(3 downto 0);
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387 |
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requestPayloadIndex_i : in std_logic_vector(3 downto 0);
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388 |
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requestPayload_o : out std_logic_vector(31 downto 0);
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389 |
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requestDone_i : in std_logic;
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390 |
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391 |
45 |
magro732 |
inboundCyc_i : in std_logic;
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392 |
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inboundStb_i : in std_logic;
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393 |
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inboundAdr_i : in std_logic_vector(7 downto 0);
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394 |
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inboundDat_i : in std_logic_vector(31 downto 0);
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395 |
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inboundAck_o : out std_logic);
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396 |
39 |
magro732 |
end entity;
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397 |
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398 |
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399 |
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-------------------------------------------------------------------------------
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400 |
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--
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401 |
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-------------------------------------------------------------------------------
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402 |
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architecture MaintenanceRequestInbound of MaintenanceRequestInbound is
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403 |
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component MemorySimpleDualPort
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404 |
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generic(
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ADDRESS_WIDTH : natural := 1;
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406 |
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DATA_WIDTH : natural := 1);
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407 |
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port(
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408 |
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clkA_i : in std_logic;
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409 |
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enableA_i : in std_logic;
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410 |
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addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
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411 |
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dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
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412 |
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413 |
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clkB_i : in std_logic;
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414 |
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enableB_i : in std_logic;
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415 |
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addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
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416 |
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dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
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417 |
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end component;
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418 |
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419 |
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type StateType is (RECEIVE_PACKET, READY);
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420 |
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signal state : StateType;
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421 |
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422 |
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signal wdptr : std_logic;
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423 |
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signal size : std_logic_vector(3 downto 0);
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424 |
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signal words : natural range 0 to 32;
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425 |
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426 |
45 |
magro732 |
signal inboundAck : std_logic;
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427 |
39 |
magro732 |
signal maintReadComplete : std_logic;
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428 |
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signal maintWriteComplete : std_logic;
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429 |
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430 |
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signal packetIndex : natural range 0 to 33;
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431 |
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signal requestData : std_logic_vector(31 downto 0);
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432 |
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433 |
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signal memoryWrite : std_logic;
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434 |
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signal memoryAddress : std_logic_vector(3 downto 0);
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435 |
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signal memoryDataIn : std_logic_vector(31 downto 0);
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436 |
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437 |
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begin
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438 |
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439 |
45 |
magro732 |
inboundAck_o <= inboundAck;
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440 |
39 |
magro732 |
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441 |
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requestReadReady_o <= maintReadComplete when (state = READY) else '0';
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442 |
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requestWriteReady_o <= maintWriteComplete when (state = READY) else '0';
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443 |
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444 |
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MaintenanceRequest: process(clk, areset_n)
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445 |
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begin
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446 |
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if (areset_n = '0') then
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447 |
45 |
magro732 |
inboundAck <= '0';
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448 |
39 |
magro732 |
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449 |
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maintReadComplete <= '0';
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450 |
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maintWriteComplete <= '0';
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451 |
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452 |
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requestVc_o <= '0';
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453 |
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requestCrf_o <= '0';
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454 |
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requestPrio_o <= "00";
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455 |
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requestTt_o <= "00";
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456 |
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requestOffset_o <= (others=>'0');
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457 |
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458 |
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wdptr <= '0';
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459 |
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size <= (others=>'0');
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460 |
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461 |
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packetIndex <= 0;
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462 |
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memoryWrite <= '0';
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463 |
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memoryAddress <= (others=>'0');
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464 |
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memoryDataIn <= (others=>'0');
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465 |
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elsif (clk'event and clk = '1') then
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466 |
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case state is
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467 |
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when RECEIVE_PACKET =>
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468 |
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---------------------------------------------------------------------
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469 |
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-- This state waits for a new maintenance request packet, receives it
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470 |
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-- and parses it.
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471 |
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---------------------------------------------------------------------
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472 |
45 |
magro732 |
if (inboundCyc_i = '1') then
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473 |
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if (inboundAck = '0') then
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474 |
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if (inboundStb_i = '1') then
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475 |
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if (inboundAdr_i = x"80") then
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476 |
39 |
magro732 |
-------------------------------------------------------------
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477 |
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-- Maintenance Read Request packet parser.
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478 |
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-------------------------------------------------------------
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479 |
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case (packetIndex) is
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480 |
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when 0 =>
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481 |
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-- x"0000" & ackid & vc & crf & prio & tt & ftype
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482 |
45 |
magro732 |
requestVc_o <= inboundDat_i(9);
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483 |
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requestCrf_o <= inboundDat_i(8);
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484 |
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requestPrio_o <= inboundDat_i(7 downto 6);
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485 |
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requestTt_o <= inboundDat_i(5 downto 4);
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486 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
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487 |
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when 1 =>
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488 |
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-- destid
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489 |
45 |
magro732 |
requestDstId_o <= inboundDat_i;
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490 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
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491 |
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when 2 =>
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492 |
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-- srcid
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493 |
45 |
magro732 |
requestSrcId_o <= inboundDat_i;
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494 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
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495 |
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when 3 =>
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496 |
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-- transaction & rdsize & srcTID & hop & config_offset(20:13)
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497 |
45 |
magro732 |
size <= inboundDat_i(27 downto 24);
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498 |
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requestTid_o <= inboundDat_i(23 downto 16);
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499 |
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requestOffset_o(20 downto 13) <= inboundDat_i(7 downto 0);
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500 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
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501 |
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when 4 =>
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502 |
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-- config_offset(12:0) & wdptr & rsrv & crc(15:0)
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503 |
45 |
magro732 |
requestOffset_o(12 downto 0) <= inboundDat_i(31 downto 19);
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504 |
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wdptr <= inboundDat_i(18);
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505 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
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506 |
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maintReadComplete <= '1';
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507 |
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when others =>
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508 |
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-- There should be no more content in a maintenance read request.
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509 |
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-- Discard.
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510 |
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end case;
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511 |
45 |
magro732 |
inboundAck <= '1';
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512 |
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elsif (inboundAdr_i = x"81") then
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513 |
39 |
magro732 |
-------------------------------------------------------------
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514 |
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-- Maintenance Write Request packet parser.
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515 |
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-------------------------------------------------------------
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516 |
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case (packetIndex) is
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517 |
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when 0 =>
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518 |
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-- x"0000" & ackid & vc & crf & prio & tt & ftype
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519 |
45 |
magro732 |
requestVc_o <= inboundDat_i(9);
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520 |
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requestCrf_o <= inboundDat_i(8);
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521 |
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requestPrio_o <= inboundDat_i(7 downto 6);
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522 |
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requestTt_o <= inboundDat_i(5 downto 4);
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523 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
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524 |
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when 1 =>
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525 |
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-- destId
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526 |
45 |
magro732 |
requestDstId_o <= inboundDat_i;
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527 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
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528 |
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when 2 =>
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529 |
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-- srcId
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530 |
45 |
magro732 |
requestSrcId_o <= inboundDat_i;
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531 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
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532 |
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when 3 =>
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533 |
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-- transaction & wrsize & srcTID & hop & config_offset(20:13)
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534 |
45 |
magro732 |
size <= inboundDat_i(27 downto 24);
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535 |
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requestTid_o <= inboundDat_i(23 downto 16);
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536 |
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requestOffset_o(20 downto 13) <= inboundDat_i(7 downto 0);
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537 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
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538 |
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when 4 =>
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539 |
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-- config_offset(12:0) & wdptr & rsrv & double-word(63:48)
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540 |
45 |
magro732 |
requestOffset_o(12 downto 0) <= inboundDat_i(31 downto 19);
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541 |
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wdptr <= inboundDat_i(18);
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542 |
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requestData(31 downto 16) <= inboundDat_i(15 downto 0);
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543 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
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544 |
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when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 =>
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545 |
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-- double-word(47:16)
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546 |
45 |
magro732 |
requestData(31 downto 16) <= inboundDat_i(15 downto 0);
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547 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
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548 |
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|
549 |
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if (not ((size = "1000") and (wdptr = '1'))) then
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550 |
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memoryWrite <= '1';
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551 |
45 |
magro732 |
memoryDataIn <= requestData(31 downto 16) & inboundDat_i(31 downto 16);
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552 |
39 |
magro732 |
end if;
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553 |
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when 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32 =>
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554 |
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-- double-word(15:0) & double-word(63:48)
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555 |
45 |
magro732 |
requestData(31 downto 16) <= inboundDat_i(15 downto 0);
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556 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
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557 |
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|
558 |
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memoryWrite <= '1';
|
559 |
45 |
magro732 |
memoryDataIn <= requestData(31 downto 16) & inboundDat_i(31 downto 16);
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560 |
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-- REMARK: Dont set complete before the packet is ready...
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561 |
39 |
magro732 |
maintWriteComplete <= '1';
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562 |
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when others =>
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563 |
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-- There should be no more content in a maintenance write request.
|
564 |
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-- Discard.
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565 |
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end case;
|
566 |
45 |
magro732 |
inboundAck <= '1';
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567 |
39 |
magro732 |
end if;
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568 |
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end if;
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569 |
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else
|
570 |
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if (memoryWrite = '1') then
|
571 |
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memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
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572 |
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end if;
|
573 |
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|
574 |
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memoryWrite <= '0';
|
575 |
45 |
magro732 |
inboundAck <= '0';
|
576 |
39 |
magro732 |
end if;
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577 |
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else
|
578 |
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if (maintReadComplete = '1') or (maintWriteComplete = '1') then
|
579 |
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state <= READY;
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580 |
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end if;
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581 |
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packetIndex <= 0;
|
582 |
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memoryAddress <= (others=>'0');
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583 |
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end if;
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584 |
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|
585 |
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when READY =>
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586 |
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---------------------------------------------------------------------
|
587 |
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-- Wait for the handler of the packet to signal that it has been
|
588 |
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-- processed.
|
589 |
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---------------------------------------------------------------------
|
590 |
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if (requestDone_i = '1') then
|
591 |
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maintReadComplete <= '0';
|
592 |
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maintWriteComplete <= '0';
|
593 |
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state <= RECEIVE_PACKET;
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594 |
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end if;
|
595 |
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|
596 |
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when others =>
|
597 |
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---------------------------------------------------------------------
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598 |
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--
|
599 |
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---------------------------------------------------------------------
|
600 |
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|
601 |
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end case;
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602 |
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end if;
|
603 |
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end process;
|
604 |
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|
605 |
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-----------------------------------------------------------------------------
|
606 |
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-- Transformation of rdsize/wrsize into length of access and byte lanes.
|
607 |
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-----------------------------------------------------------------------------
|
608 |
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|
609 |
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process(clk, areset_n)
|
610 |
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begin
|
611 |
|
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if (areset_n = '0') then
|
612 |
|
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requestPayloadLength_o <= (others=>'0');
|
613 |
|
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requestWdptr_o <= '0';
|
614 |
|
|
elsif (clk'event and clk = '1') then
|
615 |
|
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if (maintReadComplete = '1') or (maintWriteComplete = '1') then
|
616 |
|
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if (wdptr = '0') then
|
617 |
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case size is
|
618 |
|
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when "1000" =>
|
619 |
|
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-- Read 1 word.
|
620 |
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requestPayloadLength_o <= "0000";
|
621 |
|
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requestWdptr_o <= '0';
|
622 |
|
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when "1011" =>
|
623 |
|
|
-- Read 2 words.
|
624 |
|
|
requestPayloadLength_o <= "0001";
|
625 |
|
|
requestWdptr_o <= '0';
|
626 |
|
|
when "1100" =>
|
627 |
|
|
-- Read 8 words.
|
628 |
|
|
requestPayloadLength_o <= "0111";
|
629 |
|
|
requestWdptr_o <= '0';
|
630 |
|
|
when others =>
|
631 |
|
|
-- REMARK: Not allowed for a maintenance packet.
|
632 |
|
|
requestPayloadLength_o <= "0000";
|
633 |
|
|
requestWdptr_o <= '0';
|
634 |
|
|
end case;
|
635 |
|
|
else
|
636 |
|
|
case size is
|
637 |
|
|
when "1000" =>
|
638 |
|
|
-- Read 1 word.
|
639 |
|
|
requestPayloadLength_o <= "0000";
|
640 |
|
|
requestWdptr_o <= '1';
|
641 |
|
|
when "1011" =>
|
642 |
|
|
-- Read 4 words.
|
643 |
|
|
requestPayloadLength_o <= "0011";
|
644 |
|
|
requestWdptr_o <= '0';
|
645 |
|
|
when "1100" =>
|
646 |
|
|
-- Read 16 words.
|
647 |
|
|
requestPayloadLength_o <= "1111";
|
648 |
|
|
requestWdptr_o <= '0';
|
649 |
|
|
when others =>
|
650 |
|
|
-- REMARK: Not allowed for a maintenance packet.
|
651 |
|
|
requestPayloadLength_o <= "0000";
|
652 |
|
|
requestWdptr_o <= '0';
|
653 |
|
|
end case;
|
654 |
|
|
end if;
|
655 |
|
|
end if;
|
656 |
|
|
end if;
|
657 |
|
|
end process;
|
658 |
|
|
|
659 |
|
|
-----------------------------------------------------------------------------
|
660 |
|
|
-- Payload content memory.
|
661 |
|
|
-----------------------------------------------------------------------------
|
662 |
|
|
PayloadMemory: MemorySimpleDualPort
|
663 |
|
|
generic map(ADDRESS_WIDTH=>4, DATA_WIDTH=>32)
|
664 |
|
|
port map(clkA_i=>clk,
|
665 |
|
|
enableA_i=>memoryWrite,
|
666 |
|
|
addressA_i=>memoryAddress,
|
667 |
|
|
dataA_i=>memoryDataIn,
|
668 |
|
|
clkB_i=>clk,
|
669 |
|
|
enableB_i=>enable,
|
670 |
|
|
addressB_i=>requestPayloadIndex_i,
|
671 |
|
|
dataB_o=>requestPayload_o);
|
672 |
|
|
|
673 |
|
|
end architecture;
|
674 |
|
|
|
675 |
|
|
|
676 |
|
|
-------------------------------------------------------------------------------
|
677 |
|
|
--
|
678 |
|
|
-------------------------------------------------------------------------------
|
679 |
|
|
library ieee;
|
680 |
|
|
use ieee.std_logic_1164.all;
|
681 |
|
|
use ieee.numeric_std.all;
|
682 |
|
|
use work.rio_common.all;
|
683 |
|
|
|
684 |
|
|
-------------------------------------------------------------------------------
|
685 |
|
|
--
|
686 |
|
|
-------------------------------------------------------------------------------
|
687 |
|
|
entity MaintenanceResponseOutbound is
|
688 |
|
|
port(
|
689 |
|
|
clk : in std_logic;
|
690 |
|
|
areset_n : in std_logic;
|
691 |
|
|
enable : in std_logic;
|
692 |
|
|
|
693 |
|
|
responseReadReady_i : in std_logic;
|
694 |
|
|
responseWriteReady_i : in std_logic;
|
695 |
|
|
responseVc_i : in std_logic;
|
696 |
|
|
responseCrf_i : in std_logic;
|
697 |
|
|
responsePrio_i : in std_logic_vector(1 downto 0);
|
698 |
|
|
responseTt_i : in std_logic_vector(1 downto 0);
|
699 |
|
|
responseDstId_i : in std_logic_vector(31 downto 0);
|
700 |
|
|
responseSrcId_i : in std_logic_vector(31 downto 0);
|
701 |
|
|
responseTid_i : in std_logic_vector(7 downto 0);
|
702 |
|
|
responseWdptr_i : in std_logic;
|
703 |
|
|
responsePayloadLength_i : in std_logic_vector(3 downto 0);
|
704 |
|
|
responsePayloadWrite_i : in std_logic;
|
705 |
|
|
responsePayloadIndex_i : in std_logic_vector(3 downto 0);
|
706 |
|
|
responsePayload_i : in std_logic_vector(31 downto 0);
|
707 |
|
|
responseDone_o : out std_logic;
|
708 |
|
|
|
709 |
45 |
magro732 |
outboundCyc_o : out std_logic;
|
710 |
|
|
outboundStb_o : out std_logic;
|
711 |
|
|
outboundDat_o : out std_logic_vector(31 downto 0);
|
712 |
|
|
outboundAck_i : in std_logic);
|
713 |
39 |
magro732 |
end entity;
|
714 |
|
|
|
715 |
|
|
|
716 |
|
|
-------------------------------------------------------------------------------
|
717 |
|
|
--
|
718 |
|
|
-------------------------------------------------------------------------------
|
719 |
|
|
architecture MaintenanceResponseOutbound of MaintenanceResponseOutbound is
|
720 |
|
|
component MemorySimpleDualPort
|
721 |
|
|
generic(
|
722 |
|
|
ADDRESS_WIDTH : natural := 1;
|
723 |
|
|
DATA_WIDTH : natural := 1);
|
724 |
|
|
port(
|
725 |
|
|
clkA_i : in std_logic;
|
726 |
|
|
enableA_i : in std_logic;
|
727 |
|
|
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
728 |
|
|
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
729 |
|
|
|
730 |
|
|
clkB_i : in std_logic;
|
731 |
|
|
enableB_i : in std_logic;
|
732 |
|
|
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
733 |
|
|
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
734 |
|
|
end component;
|
735 |
|
|
|
736 |
|
|
type StateType is (WAIT_PACKET,
|
737 |
|
|
READ_RESPONSE, WRITE_RESPONSE,
|
738 |
|
|
WAIT_COMPLETE, RESPONSE_DONE);
|
739 |
|
|
signal state : StateType;
|
740 |
|
|
|
741 |
|
|
signal packetIndex : natural range 0 to 33;
|
742 |
|
|
signal responseHeader : std_logic_vector(31 downto 0);
|
743 |
|
|
signal responsePayload : std_logic_vector(31 downto 0);
|
744 |
|
|
signal responsePayloadIndex : std_logic_vector(2 downto 0);
|
745 |
|
|
|
746 |
|
|
signal memoryEnable : std_logic;
|
747 |
|
|
signal memoryAddress : std_logic_vector(3 downto 0);
|
748 |
|
|
signal memoryDataRead : std_logic_vector(31 downto 0);
|
749 |
|
|
|
750 |
|
|
begin
|
751 |
|
|
|
752 |
|
|
responseHeader <=
|
753 |
|
|
x"0000" & "000000" & responseVc_i & responseCrf_i &
|
754 |
|
|
responsePrio_i & responseTt_i & x"8";
|
755 |
|
|
|
756 |
|
|
MaintenanceResponse: process(clk, areset_n)
|
757 |
|
|
begin
|
758 |
|
|
if (areset_n = '0') then
|
759 |
45 |
magro732 |
outboundCyc_o <= '0';
|
760 |
|
|
outboundStb_o <= '0';
|
761 |
39 |
magro732 |
|
762 |
|
|
memoryEnable <= '0';
|
763 |
|
|
memoryAddress <= (others=>'0');
|
764 |
|
|
|
765 |
|
|
responsePayloadIndex <= (others=>'0');
|
766 |
|
|
responseDone_o <= '0';
|
767 |
|
|
|
768 |
|
|
state <= WAIT_PACKET;
|
769 |
|
|
elsif (clk'event and clk = '1') then
|
770 |
|
|
if (enable = '1') then
|
771 |
|
|
case state is
|
772 |
|
|
when WAIT_PACKET =>
|
773 |
|
|
-------------------------------------------------------------------
|
774 |
|
|
--
|
775 |
|
|
-------------------------------------------------------------------
|
776 |
|
|
if (responseReadReady_i = '1') then
|
777 |
45 |
magro732 |
outboundCyc_o <= '1';
|
778 |
|
|
outboundStb_o <= '1';
|
779 |
|
|
outboundDat_o <= responseHeader;
|
780 |
39 |
magro732 |
packetIndex <= 1;
|
781 |
|
|
memoryEnable <= '1';
|
782 |
|
|
memoryAddress <= (others=>'0');
|
783 |
|
|
responsePayloadIndex <= (others=>'0');
|
784 |
|
|
state <= READ_RESPONSE;
|
785 |
|
|
elsif (responseWriteReady_i = '1') then
|
786 |
45 |
magro732 |
outboundCyc_o <= '1';
|
787 |
|
|
outboundStb_o <= '1';
|
788 |
|
|
outboundDat_o <= responseHeader;
|
789 |
39 |
magro732 |
packetIndex <= 1;
|
790 |
|
|
state <= WRITE_RESPONSE;
|
791 |
|
|
end if;
|
792 |
|
|
|
793 |
|
|
when READ_RESPONSE =>
|
794 |
|
|
---------------------------------------------------------------------
|
795 |
|
|
--
|
796 |
|
|
---------------------------------------------------------------------
|
797 |
45 |
magro732 |
if (outboundAck_i = '1') then
|
798 |
39 |
magro732 |
case (packetIndex) is
|
799 |
|
|
when 1 =>
|
800 |
|
|
-- destination
|
801 |
45 |
magro732 |
outboundDat_o <= responseDstId_i;
|
802 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
|
803 |
|
|
when 2 =>
|
804 |
|
|
-- source
|
805 |
45 |
magro732 |
outboundDat_o <= responseSrcId_i;
|
806 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
|
807 |
|
|
when 3 =>
|
808 |
|
|
-- transaction & status & targetTID & hop & reserved(7:0)
|
809 |
45 |
magro732 |
outboundDat_o <= "0010" & "0000" & responseTid_i & x"ff" & x"00";
|
810 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
|
811 |
|
|
when 4 =>
|
812 |
|
|
-- reserved(15:0) & double-wordN(63:48)
|
813 |
|
|
if (responsePayloadLength_i = "0000") and (responseWdptr_i = '0') then
|
814 |
45 |
magro732 |
outboundDat_o <= x"0000" & memoryDataRead(31 downto 16);
|
815 |
39 |
magro732 |
responsePayload(31 downto 16) <= memoryDataRead(15 downto 0);
|
816 |
|
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
817 |
|
|
elsif (responsePayloadLength_i = "0000") and (responseWdptr_i = '1') then
|
818 |
45 |
magro732 |
outboundDat_o <= x"0000" & x"0000";
|
819 |
39 |
magro732 |
else
|
820 |
45 |
magro732 |
outboundDat_o <= x"0000" & memoryDataRead(31 downto 16);
|
821 |
39 |
magro732 |
responsePayload(31 downto 16) <= memoryDataRead(15 downto 0);
|
822 |
|
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
823 |
|
|
end if;
|
824 |
|
|
packetIndex <= packetIndex + 1;
|
825 |
|
|
when 5 | 7 | 9 | 11 | 13 | 15 | 17 | 19 | 21 | 23 | 25 | 27 | 29 | 31 =>
|
826 |
|
|
-- double-wordN(47:16)
|
827 |
|
|
if (responsePayloadLength_i = "0000") and (responseWdptr_i = '0') then
|
828 |
45 |
magro732 |
outboundDat_o <= responsePayload(31 downto 16) & x"0000";
|
829 |
39 |
magro732 |
elsif (responsePayloadLength_i = "0000") and (responseWdptr_i = '1') then
|
830 |
45 |
magro732 |
outboundDat_o <= x"0000" & memoryDataRead(31 downto 16);
|
831 |
39 |
magro732 |
responsePayload(31 downto 16) <= memoryDataRead(15 downto 0);
|
832 |
|
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
833 |
|
|
else
|
834 |
45 |
magro732 |
outboundDat_o <=
|
835 |
39 |
magro732 |
responsePayload(31 downto 16) & memoryDataRead(31 downto 16);
|
836 |
|
|
responsePayload(31 downto 16) <= memoryDataRead(15 downto 0);
|
837 |
|
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
838 |
|
|
end if;
|
839 |
|
|
packetIndex <= packetIndex + 1;
|
840 |
|
|
when 6 | 8 | 10 | 12 | 14 | 16 | 18 | 20 | 22 | 24 | 26 | 28 | 30 | 32 =>
|
841 |
|
|
-- double-wordN(15:0) & double-wordN(63:48)
|
842 |
|
|
if (responsePayloadLength_i = "0000") and (responseWdptr_i = '0') then
|
843 |
45 |
magro732 |
outboundDat_o <= x"0000" & x"0000";
|
844 |
39 |
magro732 |
elsif (responsePayloadLength_i = "0000") and (responseWdptr_i = '1') then
|
845 |
45 |
magro732 |
outboundDat_o <= responsePayload(31 downto 16) & x"0000";
|
846 |
39 |
magro732 |
else
|
847 |
|
|
if (responsePayloadIndex /= responsePayloadLength_i(3 downto 1)) then
|
848 |
45 |
magro732 |
outboundDat_o <=
|
849 |
39 |
magro732 |
responsePayload(31 downto 16) & memoryDataRead(31 downto 16);
|
850 |
|
|
responsePayload(31 downto 16) <= memoryDataRead(15 downto 0);
|
851 |
|
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
852 |
|
|
else
|
853 |
45 |
magro732 |
outboundDat_o <=
|
854 |
39 |
magro732 |
responsePayload(31 downto 16) & x"0000";
|
855 |
|
|
responsePayload(31 downto 16) <= memoryDataRead(15 downto 0);
|
856 |
|
|
memoryAddress <= std_logic_vector(unsigned(memoryAddress) + 1);
|
857 |
|
|
end if;
|
858 |
|
|
end if;
|
859 |
|
|
|
860 |
|
|
responsePayloadIndex <=
|
861 |
|
|
std_logic_vector(unsigned(responsePayloadIndex) + 1);
|
862 |
|
|
|
863 |
|
|
if (responsePayloadIndex = responsePayloadLength_i(3 downto 1)) then
|
864 |
|
|
state <= WAIT_COMPLETE;
|
865 |
|
|
else
|
866 |
|
|
packetIndex <= packetIndex + 1;
|
867 |
|
|
end if;
|
868 |
|
|
when others =>
|
869 |
|
|
-- Unallowed response length.
|
870 |
|
|
-- Dont do anything.
|
871 |
|
|
end case;
|
872 |
|
|
end if;
|
873 |
|
|
|
874 |
|
|
when WRITE_RESPONSE =>
|
875 |
|
|
---------------------------------------------------------------------
|
876 |
|
|
--
|
877 |
|
|
---------------------------------------------------------------------
|
878 |
45 |
magro732 |
if (outboundAck_i = '1') then
|
879 |
39 |
magro732 |
case (packetIndex) is
|
880 |
|
|
when 1 =>
|
881 |
|
|
-- destination
|
882 |
45 |
magro732 |
outboundDat_o <= responseDstId_i;
|
883 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
|
884 |
|
|
when 2 =>
|
885 |
|
|
-- source
|
886 |
45 |
magro732 |
outboundDat_o <= responseSrcId_i;
|
887 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
|
888 |
|
|
when 3 =>
|
889 |
|
|
-- transaction & status & targetTID & hop & reserved(7:0)
|
890 |
45 |
magro732 |
outboundDat_o <= "0011" & "0000" & responseTid_i & x"ff" & x"00";
|
891 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
|
892 |
|
|
when others =>
|
893 |
|
|
-- reserved(15:0) & crc(15:0)
|
894 |
45 |
magro732 |
outboundDat_o <= x"00000000";
|
895 |
39 |
magro732 |
packetIndex <= packetIndex + 1;
|
896 |
|
|
state <= WAIT_COMPLETE;
|
897 |
|
|
end case;
|
898 |
|
|
end if;
|
899 |
|
|
|
900 |
|
|
when WAIT_COMPLETE =>
|
901 |
|
|
-------------------------------------------------------------------
|
902 |
|
|
--
|
903 |
|
|
-------------------------------------------------------------------
|
904 |
45 |
magro732 |
if (outboundAck_i = '1') then
|
905 |
|
|
outboundCyc_o <= '0';
|
906 |
|
|
outboundStb_o <= '0';
|
907 |
39 |
magro732 |
state <= RESPONSE_DONE;
|
908 |
|
|
end if;
|
909 |
|
|
|
910 |
|
|
when RESPONSE_DONE =>
|
911 |
|
|
---------------------------------------------------------------------
|
912 |
|
|
--
|
913 |
|
|
---------------------------------------------------------------------
|
914 |
|
|
memoryEnable <= '0';
|
915 |
|
|
if (responseReadReady_i = '0') and (responseWriteReady_i = '0') then
|
916 |
|
|
state <= WAIT_PACKET;
|
917 |
|
|
responseDone_o <= '0';
|
918 |
|
|
else
|
919 |
|
|
responseDone_o <= '1';
|
920 |
|
|
end if;
|
921 |
|
|
|
922 |
|
|
when others =>
|
923 |
|
|
---------------------------------------------------------------------
|
924 |
|
|
--
|
925 |
|
|
---------------------------------------------------------------------
|
926 |
|
|
state <= WAIT_PACKET;
|
927 |
|
|
|
928 |
|
|
end case;
|
929 |
|
|
end if;
|
930 |
|
|
end if;
|
931 |
|
|
end process;
|
932 |
|
|
|
933 |
|
|
-----------------------------------------------------------------------------
|
934 |
|
|
-- Payload content memory.
|
935 |
|
|
-----------------------------------------------------------------------------
|
936 |
|
|
PayloadMemory: MemorySimpleDualPort
|
937 |
|
|
generic map(ADDRESS_WIDTH=>4, DATA_WIDTH=>32)
|
938 |
|
|
port map(clkA_i=>clk,
|
939 |
|
|
enableA_i=>responsePayloadWrite_i,
|
940 |
|
|
addressA_i=>responsePayloadIndex_i,
|
941 |
|
|
dataA_i=>responsePayload_i,
|
942 |
|
|
clkB_i=>clk,
|
943 |
|
|
enableB_i=>memoryEnable,
|
944 |
|
|
addressB_i=>memoryAddress,
|
945 |
|
|
dataB_o=>memoryDataRead);
|
946 |
|
|
|
947 |
|
|
end architecture;
|