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magro732 |
-------------------------------------------------------------------------------
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--
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-- RapidIO IP Library Core
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--
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-- This file is part of the RapidIO IP library project
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-- http://www.opencores.org/cores/rio/
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--
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-- Description
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-- Contains automatic simulation test code to verify a RioSwitch implementation.
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--
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-- To Do:
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-- -
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--
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-- Author(s):
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-- - Magnus Rosenius, magro732@opencores.org
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2013 Authors and OPENCORES.ORG
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- TestRioSwitch.
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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library std;
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use std.textio.all;
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use work.rio_common.all;
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-------------------------------------------------------------------------------
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-- Entity for TestRioSwitch.
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-------------------------------------------------------------------------------
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entity TestRioSwitch is
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end entity;
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-------------------------------------------------------------------------------
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-- Architecture for TestRioSwitch.
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-------------------------------------------------------------------------------
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architecture TestRioSwitchImpl of TestRioSwitch is
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component RioSwitch is
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generic(
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SWITCH_PORTS : natural range 3 to 255 := 4;
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DEVICE_IDENTITY : std_logic_vector(15 downto 0);
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DEVICE_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
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DEVICE_REV : std_logic_vector(31 downto 0);
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ASSY_IDENTITY : std_logic_vector(15 downto 0);
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ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0);
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ASSY_REV : std_logic_vector(15 downto 0));
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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writeFrameFull_i : in Array1(SWITCH_PORTS-1 downto 0);
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writeFrame_o : out Array1(SWITCH_PORTS-1 downto 0);
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writeFrameAbort_o : out Array1(SWITCH_PORTS-1 downto 0);
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writeContent_o : out Array1(SWITCH_PORTS-1 downto 0);
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writeContentData_o : out Array32(SWITCH_PORTS-1 downto 0);
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readFrameEmpty_i : in Array1(SWITCH_PORTS-1 downto 0);
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readFrame_o : out Array1(SWITCH_PORTS-1 downto 0);
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readFrameRestart_o : out Array1(SWITCH_PORTS-1 downto 0);
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readFrameAborted_i : in Array1(SWITCH_PORTS-1 downto 0);
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readContentEmpty_i : in Array1(SWITCH_PORTS-1 downto 0);
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readContent_o : out Array1(SWITCH_PORTS-1 downto 0);
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readContentEnd_i : in Array1(SWITCH_PORTS-1 downto 0);
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readContentData_i : in Array32(SWITCH_PORTS-1 downto 0);
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portLinkTimeout_o : out std_logic_vector(23 downto 0);
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linkInitialized_i : in Array1(SWITCH_PORTS-1 downto 0);
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outputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
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inputPortEnable_o : out Array1(SWITCH_PORTS-1 downto 0);
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localAckIdWrite_o : out Array1(SWITCH_PORTS-1 downto 0);
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clrOutstandingAckId_o : out Array1(SWITCH_PORTS-1 downto 0);
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inboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
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outstandingAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
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outboundAckId_o : out Array5(SWITCH_PORTS-1 downto 0);
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inboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
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outstandingAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
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outboundAckId_i : in Array5(SWITCH_PORTS-1 downto 0);
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configStb_o : out std_logic;
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configWe_o : out std_logic;
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configAddr_o : out std_logic_vector(23 downto 0);
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configData_o : out std_logic_vector(31 downto 0);
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configData_i : in std_logic_vector(31 downto 0));
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end component;
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component TestPort is
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port(
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clk : in std_logic;
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areset_n : in std_logic;
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frameValid_i : in std_logic;
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frameWrite_i : in RioFrame;
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frameComplete_o : out std_logic;
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frameExpected_i : in std_logic;
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frameRead_i : in RioFrame;
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frameReceived_o : out std_logic;
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readFrameEmpty_o : out std_logic;
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readFrame_i : in std_logic;
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readFrameRestart_i : in std_logic;
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readFrameAborted_o : out std_logic;
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readContentEmpty_o : out std_logic;
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readContent_i : in std_logic;
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readContentEnd_o : out std_logic;
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readContentData_o : out std_logic_vector(31 downto 0);
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writeFrameFull_o : out std_logic;
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writeFrame_i : in std_logic;
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writeFrameAbort_i : in std_logic;
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writeContent_i : in std_logic;
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writeContentData_i : in std_logic_vector(31 downto 0));
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end component;
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constant PORTS : natural := 7;
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constant SWITCH_IDENTITY : std_logic_vector(15 downto 0) := x"0123";
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constant SWITCH_VENDOR_IDENTITY : std_logic_vector(15 downto 0) := x"4567";
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constant SWITCH_REV : std_logic_vector(31 downto 0) := x"89abcdef";
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constant SWITCH_ASSY_IDENTITY : std_logic_vector(15 downto 0) := x"0011";
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constant SWITCH_ASSY_VENDOR_IDENTITY : std_logic_vector(15 downto 0) := x"2233";
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constant SWITCH_ASSY_REV : std_logic_vector(15 downto 0) := x"4455";
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signal clk : std_logic;
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signal areset_n : std_logic;
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signal frameValid : Array1(PORTS-1 downto 0);
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signal frameWrite : RioFrameArray(PORTS-1 downto 0);
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signal frameComplete : Array1(PORTS-1 downto 0);
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signal frameExpected : Array1(PORTS-1 downto 0);
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signal frameRead : RioFrameArray(PORTS-1 downto 0);
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signal frameReceived : Array1(PORTS-1 downto 0);
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signal writeFrameFull : Array1(PORTS-1 downto 0);
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signal writeFrame : Array1(PORTS-1 downto 0);
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signal writeFrameAbort : Array1(PORTS-1 downto 0);
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signal writeContent : Array1(PORTS-1 downto 0);
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signal writeContentData : Array32(PORTS-1 downto 0);
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signal readFrameEmpty : Array1(PORTS-1 downto 0);
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signal readFrame : Array1(PORTS-1 downto 0);
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signal readFrameRestart : Array1(PORTS-1 downto 0);
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signal readFrameAborted : Array1(PORTS-1 downto 0);
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signal readContentEmpty : Array1(PORTS-1 downto 0);
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signal readContent : Array1(PORTS-1 downto 0);
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signal readContentEnd : Array1(PORTS-1 downto 0);
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signal readContentData : Array32(PORTS-1 downto 0);
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signal portLinkTimeout : std_logic_vector(23 downto 0);
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signal linkInitialized : Array1(PORTS-1 downto 0);
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signal outputPortEnable : Array1(PORTS-1 downto 0);
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signal inputPortEnable : Array1(PORTS-1 downto 0);
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signal localAckIdWrite : Array1(PORTS-1 downto 0);
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signal clrOutstandingAckId : Array1(PORTS-1 downto 0);
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signal inboundAckIdWrite : Array5(PORTS-1 downto 0);
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signal outstandingAckIdWrite : Array5(PORTS-1 downto 0);
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signal outboundAckIdWrite : Array5(PORTS-1 downto 0);
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signal inboundAckIdRead : Array5(PORTS-1 downto 0);
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signal outstandingAckIdRead : Array5(PORTS-1 downto 0);
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signal outboundAckIdRead : Array5(PORTS-1 downto 0);
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signal configStb, configStbExpected : std_logic;
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signal configWe, configWeExpected : std_logic;
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signal configAddr, configAddrExpected : std_logic_vector(23 downto 0);
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signal configDataWrite, configDataWriteExpected : std_logic_vector(31 downto 0);
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signal configDataRead, configDataReadExpected : std_logic_vector(31 downto 0);
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begin
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-----------------------------------------------------------------------------
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-- Clock generation.
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-----------------------------------------------------------------------------
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ClockGenerator: process
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begin
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clk <= '0';
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wait for 20 ns;
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clk <= '1';
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wait for 20 ns;
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end process;
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-----------------------------------------------------------------------------
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-- Serial port emulator.
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-----------------------------------------------------------------------------
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TestDriver: process
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---------------------------------------------------------------------------
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--
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---------------------------------------------------------------------------
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procedure SendFrame(constant portIndex : natural range 0 to 7;
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constant frame : RioFrame) is
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begin
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frameValid(portIndex) <= '1';
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frameWrite(portIndex) <= frame;
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wait until frameComplete(portIndex) = '1';
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frameValid(portIndex) <= '0';
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end procedure;
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---------------------------------------------------------------------------
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--
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---------------------------------------------------------------------------
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procedure ReceiveFrame(constant portIndex : natural range 0 to 7;
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constant frame : RioFrame) is
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begin
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frameExpected(portIndex) <= '1';
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frameRead(portIndex) <= frame;
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wait until frameReceived(portIndex) = '1';
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frameExpected(portIndex) <= '0';
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end procedure;
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---------------------------------------------------------------------------
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--
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---------------------------------------------------------------------------
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procedure ReadConfig32(constant portIndex : natural range 0 to 7;
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constant destinationId : std_logic_vector(15 downto 0);
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constant sourceId : std_logic_vector(15 downto 0);
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constant hop : std_logic_vector(7 downto 0);
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constant tid : std_logic_vector(7 downto 0);
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constant address : std_logic_vector(23 downto 0);
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constant data : std_logic_vector(31 downto 0)) is
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variable maintData : DoubleWordArray(0 to 7);
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begin
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SendFrame(portIndex, RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
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tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
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sourceId=>sourceId, destId=>destinationId,
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payload=>RioMaintenance(transaction=>"0000",
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size=>"1000",
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tid=>tid,
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hopCount=>hop,
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configOffset=>address(23 downto 3),
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wdptr=>address(2),
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dataLength=>0,
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data=>maintData)));
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if (address(2) = '0') then
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maintData(0) := data & x"00000000";
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else
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maintData(0) := x"00000000" & data ;
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end if;
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ReceiveFrame(portIndex, RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
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tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
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sourceId=>destinationId, destId=>sourceId,
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payload=>RioMaintenance(transaction=>"0010",
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size=>"0000",
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tid=>tid,
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hopCount=>x"ff",
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configOffset=>"000000000000000000000",
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wdptr=>'0',
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dataLength=>1,
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data=>maintData)));
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end procedure;
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---------------------------------------------------------------------------
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--
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---------------------------------------------------------------------------
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procedure WriteConfig32(constant portIndex : natural range 0 to 7;
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constant destinationId : std_logic_vector(15 downto 0);
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constant sourceId : std_logic_vector(15 downto 0);
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constant hop : std_logic_vector(7 downto 0);
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constant tid : std_logic_vector(7 downto 0);
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constant address : std_logic_vector(23 downto 0);
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constant data : std_logic_vector(31 downto 0)) is
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variable maintData : DoubleWordArray(0 to 7);
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begin
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if (address(2) = '0') then
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maintData(0) := data & x"00000000";
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else
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maintData(0) := x"00000000" & data ;
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end if;
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SendFrame(portIndex, RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
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tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
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sourceId=>sourceId, destId=>destinationId,
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payload=>RioMaintenance(transaction=>"0001",
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size=>"1000",
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tid=>tid,
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hopCount=>hop,
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configOffset=>address(23 downto 3),
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wdptr=>address(2),
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dataLength=>1,
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data=>maintData)));
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ReceiveFrame(portIndex, RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
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tt=>"01", ftype=>FTYPE_MAINTENANCE_CLASS,
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sourceId=>destinationId, destId=>sourceId,
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|
|
payload=>RioMaintenance(transaction=>"0011",
|
| 322 |
|
|
size=>"0000",
|
| 323 |
|
|
tid=>tid,
|
| 324 |
|
|
hopCount=>x"ff",
|
| 325 |
|
|
configOffset=>"000000000000000000000",
|
| 326 |
|
|
wdptr=>'0',
|
| 327 |
|
|
dataLength=>0,
|
| 328 |
|
|
data=>maintData)));
|
| 329 |
|
|
end procedure;
|
| 330 |
|
|
|
| 331 |
|
|
---------------------------------------------------------------------------
|
| 332 |
|
|
--
|
| 333 |
|
|
---------------------------------------------------------------------------
|
| 334 |
|
|
procedure RouteFrame(constant sourcePortIndex : natural range 0 to 7;
|
| 335 |
|
|
constant destinationPortIndex : natural range 0 to 7;
|
| 336 |
|
|
constant sourceId : std_logic_vector(15 downto 0);
|
| 337 |
|
|
constant destinationId : std_logic_vector(15 downto 0);
|
| 338 |
|
|
constant payload : RioPayload) is
|
| 339 |
|
|
variable frame : RioFrame;
|
| 340 |
|
|
begin
|
| 341 |
|
|
frame := RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
|
| 342 |
|
|
tt=>"01", ftype=>"0000",
|
| 343 |
|
|
sourceId=>sourceId, destId=>destinationId,
|
| 344 |
|
|
payload=>payload);
|
| 345 |
|
|
|
| 346 |
|
|
frameExpected(destinationPortIndex) <= '1';
|
| 347 |
|
|
frameRead(destinationPortIndex) <= frame;
|
| 348 |
|
|
|
| 349 |
|
|
frameValid(sourcePortIndex) <= '1';
|
| 350 |
|
|
frameWrite(sourcePortIndex) <= frame;
|
| 351 |
|
|
wait until frameComplete(sourcePortIndex) = '1';
|
| 352 |
|
|
frameValid(sourcePortIndex) <= '0';
|
| 353 |
|
|
|
| 354 |
|
|
wait until frameReceived(destinationPortIndex) = '1';
|
| 355 |
|
|
frameExpected(destinationPortIndex) <= '0';
|
| 356 |
|
|
|
| 357 |
|
|
end procedure;
|
| 358 |
|
|
|
| 359 |
|
|
---------------------------------------------------------------------------
|
| 360 |
|
|
--
|
| 361 |
|
|
---------------------------------------------------------------------------
|
| 362 |
|
|
procedure SendFrame(constant portIndex : natural range 0 to 7;
|
| 363 |
|
|
constant sourceId : std_logic_vector(15 downto 0);
|
| 364 |
|
|
constant destinationId : std_logic_vector(15 downto 0);
|
| 365 |
|
|
constant payload : RioPayload) is
|
| 366 |
|
|
variable frame : RioFrame;
|
| 367 |
|
|
begin
|
| 368 |
|
|
frame := RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
|
| 369 |
|
|
tt=>"01", ftype=>"0000",
|
| 370 |
|
|
sourceId=>sourceId, destId=>destinationId,
|
| 371 |
|
|
payload=>payload);
|
| 372 |
|
|
|
| 373 |
|
|
frameValid(portIndex) <= '1';
|
| 374 |
|
|
frameWrite(portIndex) <= frame;
|
| 375 |
|
|
end procedure;
|
| 376 |
|
|
|
| 377 |
|
|
---------------------------------------------------------------------------
|
| 378 |
|
|
--
|
| 379 |
|
|
---------------------------------------------------------------------------
|
| 380 |
|
|
procedure ReceiveFrame(constant portIndex : natural range 0 to 7;
|
| 381 |
|
|
constant sourceId : std_logic_vector(15 downto 0);
|
| 382 |
|
|
constant destinationId : std_logic_vector(15 downto 0);
|
| 383 |
|
|
constant payload : RioPayload) is
|
| 384 |
|
|
variable frame : RioFrame;
|
| 385 |
|
|
begin
|
| 386 |
|
|
frame := RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
|
| 387 |
|
|
tt=>"01", ftype=>"0000",
|
| 388 |
|
|
sourceId=>sourceId, destId=>destinationId,
|
| 389 |
|
|
payload=>payload);
|
| 390 |
|
|
|
| 391 |
|
|
frameExpected(portIndex) <= '1';
|
| 392 |
|
|
frameRead(portIndex) <= frame;
|
| 393 |
|
|
end procedure;
|
| 394 |
|
|
|
| 395 |
|
|
-- These variabels are needed for the random number generation.
|
| 396 |
|
|
variable seed1 : positive := 1;
|
| 397 |
|
|
variable seed2: positive := 1;
|
| 398 |
|
|
|
| 399 |
|
|
variable data : DoubleWordArray(0 to 31);
|
| 400 |
|
|
variable randomPayload : RioPayload;
|
| 401 |
|
|
variable randomPayload1 : RioPayload;
|
| 402 |
|
|
variable randomPayload2 : RioPayload;
|
| 403 |
|
|
variable frame : RioFrameArray(0 to PORTS-1);
|
| 404 |
|
|
|
| 405 |
|
|
begin
|
| 406 |
|
|
areset_n <= '0';
|
| 407 |
|
|
|
| 408 |
|
|
linkInitialized <= (others=>'0');
|
| 409 |
|
|
|
| 410 |
|
|
for portIndex in 0 to PORTS-1 loop
|
| 411 |
|
|
frameValid(portIndex) <= '0';
|
| 412 |
|
|
frameExpected(portIndex) <= '0';
|
| 413 |
|
|
localAckIdWrite(portIndex) <= '0';
|
| 414 |
|
|
clrOutstandingAckId(portIndex) <= '0';
|
| 415 |
|
|
inboundAckIdWrite(portIndex) <= (others=>'0');
|
| 416 |
|
|
outstandingAckIdWrite(portIndex) <= (others=>'0');
|
| 417 |
|
|
outboundAckIdWrite(portIndex) <= (others=>'0');
|
| 418 |
|
|
end loop;
|
| 419 |
|
|
|
| 420 |
|
|
wait until clk'event and clk = '1';
|
| 421 |
|
|
wait until clk'event and clk = '1';
|
| 422 |
|
|
areset_n <= '1';
|
| 423 |
|
|
wait until clk'event and clk = '1';
|
| 424 |
|
|
wait until clk'event and clk = '1';
|
| 425 |
|
|
|
| 426 |
|
|
---------------------------------------------------------------------------
|
| 427 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 428 |
|
|
PrintS("TG_RioSwitch");
|
| 429 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 430 |
|
|
PrintS("TG_RioSwitch-TC1");
|
| 431 |
|
|
PrintS("Description: Test switch maintenance accesses on different ports.");
|
| 432 |
|
|
PrintS("Requirement: XXXXX");
|
| 433 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 434 |
|
|
PrintS("Step 1:");
|
| 435 |
|
|
PrintS("Action: Send maintenance read request packets to read switch identity.");
|
| 436 |
|
|
PrintS("Result: The switch should answer with its configured identitiy.");
|
| 437 |
|
|
---------------------------------------------------------------------------
|
| 438 |
|
|
PrintR("TG_RioSwitch-TC1-Step1");
|
| 439 |
|
|
---------------------------------------------------------------------------
|
| 440 |
|
|
|
| 441 |
|
|
ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 442 |
|
|
tid=>x"00", address=>x"000000", data=>(SWITCH_IDENTITY & SWITCH_VENDOR_IDENTITY));
|
| 443 |
|
|
ReadConfig32(portIndex=>1, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 444 |
|
|
tid=>x"01", address=>x"000004", data=>SWITCH_REV);
|
| 445 |
|
|
ReadConfig32(portIndex=>2, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 446 |
|
|
tid=>x"02", address=>x"000008", data=>(SWITCH_ASSY_IDENTITY & SWITCH_ASSY_VENDOR_IDENTITY));
|
| 447 |
|
|
ReadConfig32(portIndex=>3, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 448 |
|
|
tid=>x"03", address=>x"00000c", data=>(SWITCH_ASSY_REV & x"0100"));
|
| 449 |
|
|
|
| 450 |
|
|
---------------------------------------------------------------------------
|
| 451 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 452 |
|
|
PrintS("Step 2:");
|
| 453 |
|
|
PrintS("Action: Check the switch Processing Element Features.");
|
| 454 |
|
|
PrintS("Result: The expected switch features should be returned. ");
|
| 455 |
|
|
PrintS(" Switch with extended features pointer valid. Common ");
|
| 456 |
|
|
PrintS(" transport large system support and standard route table ");
|
| 457 |
|
|
PrintS(" configuration support.");
|
| 458 |
|
|
---------------------------------------------------------------------------
|
| 459 |
|
|
PrintR("TG_RioSwitch-TC1-Step2");
|
| 460 |
|
|
---------------------------------------------------------------------------
|
| 461 |
|
|
|
| 462 |
|
|
ReadConfig32(portIndex=>4, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 463 |
|
|
tid=>x"04", address=>x"000010", data=>x"10000118");
|
| 464 |
|
|
|
| 465 |
|
|
---------------------------------------------------------------------------
|
| 466 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 467 |
|
|
PrintS("Step 3:");
|
| 468 |
|
|
PrintS("Action: Check the switch port information.");
|
| 469 |
|
|
PrintS("Result: The expected port and number of ports should be returned.");
|
| 470 |
|
|
---------------------------------------------------------------------------
|
| 471 |
|
|
PrintR("TG_RioSwitch-TC1-Step3");
|
| 472 |
|
|
---------------------------------------------------------------------------
|
| 473 |
|
|
|
| 474 |
|
|
ReadConfig32(portIndex=>5, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 475 |
|
|
tid=>x"05", address=>x"000014", data=>x"00000705");
|
| 476 |
|
|
|
| 477 |
|
|
---------------------------------------------------------------------------
|
| 478 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 479 |
|
|
PrintS("Step 4:");
|
| 480 |
|
|
PrintS("Action: Check the switch number of supported routes.");
|
| 481 |
|
|
PrintS("Result: The expected number of supported routes should be returned.");
|
| 482 |
|
|
---------------------------------------------------------------------------
|
| 483 |
|
|
PrintR("TG_RioSwitch-TC1-Step4");
|
| 484 |
|
|
---------------------------------------------------------------------------
|
| 485 |
|
|
|
| 486 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 487 |
|
|
tid=>x"06", address=>x"000034", data=>x"00000800");
|
| 488 |
|
|
|
| 489 |
|
|
---------------------------------------------------------------------------
|
| 490 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 491 |
|
|
PrintS("Step 5:");
|
| 492 |
|
|
PrintS("Action: Test host base device id lock by reading it, then hold it ");
|
| 493 |
|
|
PrintS(" and try to grab it from another address.");
|
| 494 |
|
|
PrintS("Result: The value should follow the specification.");
|
| 495 |
|
|
---------------------------------------------------------------------------
|
| 496 |
|
|
PrintR("TG_RioSwitch-TC1-Step5");
|
| 497 |
|
|
---------------------------------------------------------------------------
|
| 498 |
|
|
|
| 499 |
|
|
-- Check that the lock is released.
|
| 500 |
|
|
ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 501 |
|
|
tid=>x"00", address=>x"000068", data=>x"0000ffff");
|
| 502 |
|
|
|
| 503 |
|
|
-- Try to accuire the lock.
|
| 504 |
|
|
WriteConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 505 |
|
|
tid=>x"00", address=>x"000068", data=>x"00000002");
|
| 506 |
|
|
|
| 507 |
|
|
-- Check that the lock has been accuired.
|
| 508 |
|
|
ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 509 |
|
|
tid=>x"00", address=>x"000068", data=>x"00000002");
|
| 510 |
|
|
|
| 511 |
|
|
-- Try to accuire the lock from another source.
|
| 512 |
|
|
WriteConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 513 |
|
|
tid=>x"00", address=>x"000068", data=>x"00000003");
|
| 514 |
|
|
|
| 515 |
|
|
-- Check that the lock refuses the new access.
|
| 516 |
|
|
ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 517 |
|
|
tid=>x"00", address=>x"000068", data=>x"00000002");
|
| 518 |
|
|
|
| 519 |
|
|
-- Release the lock.
|
| 520 |
|
|
WriteConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 521 |
|
|
tid=>x"00", address=>x"000068", data=>x"00000002");
|
| 522 |
|
|
|
| 523 |
|
|
-- Check that the lock is released.
|
| 524 |
|
|
ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 525 |
|
|
tid=>x"00", address=>x"000068", data=>x"0000ffff");
|
| 526 |
|
|
|
| 527 |
|
|
-- Check that the lock can be accuired from another source once unlocked.
|
| 528 |
|
|
WriteConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 529 |
|
|
tid=>x"00", address=>x"000068", data=>x"00000003");
|
| 530 |
|
|
|
| 531 |
|
|
-- Check that the lock is released.
|
| 532 |
|
|
ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 533 |
|
|
tid=>x"00", address=>x"000068", data=>x"00000003");
|
| 534 |
|
|
|
| 535 |
|
|
-- Release the lock again.
|
| 536 |
|
|
WriteConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 537 |
|
|
tid=>x"00", address=>x"000068", data=>x"00000003");
|
| 538 |
|
|
|
| 539 |
|
|
-- Check that the lock is released.
|
| 540 |
|
|
ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 541 |
|
|
tid=>x"00", address=>x"000068", data=>x"0000ffff");
|
| 542 |
|
|
|
| 543 |
|
|
---------------------------------------------------------------------------
|
| 544 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 545 |
|
|
PrintS("Step 6");
|
| 546 |
|
|
PrintS("Action: Check the component tag register.");
|
| 547 |
|
|
PrintS("Result: The written value in the component tag should be saved.");
|
| 548 |
|
|
---------------------------------------------------------------------------
|
| 549 |
|
|
PrintR("TG_RioSwitch-TC1-Step6");
|
| 550 |
|
|
---------------------------------------------------------------------------
|
| 551 |
|
|
|
| 552 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 553 |
|
|
tid=>x"06", address=>x"00006c", data=>x"00000000");
|
| 554 |
|
|
|
| 555 |
|
|
WriteConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 556 |
|
|
tid=>x"06", address=>x"00006c", data=>x"ffffffff");
|
| 557 |
|
|
|
| 558 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 559 |
|
|
tid=>x"06", address=>x"00006c", data=>x"ffffffff");
|
| 560 |
|
|
|
| 561 |
|
|
---------------------------------------------------------------------------
|
| 562 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 563 |
|
|
PrintS("Step 7");
|
| 564 |
|
|
PrintS("Action: Read and write to the port link timeout.");
|
| 565 |
|
|
PrintS("Result: Check that the portLinkTimeout output from the switch changes.");
|
| 566 |
|
|
---------------------------------------------------------------------------
|
| 567 |
|
|
PrintR("TG_RioSwitch-TC1-Step7");
|
| 568 |
|
|
---------------------------------------------------------------------------
|
| 569 |
|
|
|
| 570 |
|
|
assert portLinkTimeout = x"ffffff" report "Unexpected portLinkTimeout." severity error;
|
| 571 |
|
|
|
| 572 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 573 |
|
|
tid=>x"06", address=>x"000120", data=>x"ffffff00");
|
| 574 |
|
|
|
| 575 |
|
|
WriteConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 576 |
|
|
tid=>x"06", address=>x"000120", data=>x"00000100");
|
| 577 |
|
|
|
| 578 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 579 |
|
|
tid=>x"06", address=>x"000120", data=>x"00000100");
|
| 580 |
|
|
|
| 581 |
|
|
assert portLinkTimeout = x"000001" report "Unexpected portLinkTimeout." severity error;
|
| 582 |
|
|
|
| 583 |
|
|
---------------------------------------------------------------------------
|
| 584 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 585 |
|
|
PrintS("Step 8");
|
| 586 |
|
|
PrintS("Action: Read from the port general control.");
|
| 587 |
|
|
PrintS("Result: Check the discovered bit.");
|
| 588 |
|
|
---------------------------------------------------------------------------
|
| 589 |
|
|
PrintR("TG_RioSwitch-TC1-Step8");
|
| 590 |
|
|
---------------------------------------------------------------------------
|
| 591 |
|
|
|
| 592 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 593 |
|
|
tid=>x"06", address=>x"00013c", data=>x"00000000");
|
| 594 |
|
|
|
| 595 |
|
|
WriteConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 596 |
|
|
tid=>x"06", address=>x"00013c", data=>x"20000000");
|
| 597 |
|
|
|
| 598 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 599 |
|
|
tid=>x"06", address=>x"00013c", data=>x"20000000");
|
| 600 |
|
|
|
| 601 |
|
|
WriteConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 602 |
|
|
tid=>x"06", address=>x"00013c", data=>x"00000000");
|
| 603 |
|
|
|
| 604 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 605 |
|
|
tid=>x"06", address=>x"00013c", data=>x"00000000");
|
| 606 |
|
|
|
| 607 |
|
|
---------------------------------------------------------------------------
|
| 608 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 609 |
|
|
PrintS("Step 9");
|
| 610 |
|
|
PrintS("Action: Read from the port N error and status.");
|
| 611 |
|
|
PrintS("Result: Check the port ok and port uninitialized bits.");
|
| 612 |
|
|
---------------------------------------------------------------------------
|
| 613 |
|
|
PrintR("TG_RioSwitch-TC1-Step9");
|
| 614 |
|
|
---------------------------------------------------------------------------
|
| 615 |
|
|
|
| 616 |
|
|
linkInitialized(0) <= '0';
|
| 617 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 618 |
|
|
tid=>x"06", address=>x"000158", data=>x"00000001");
|
| 619 |
|
|
linkInitialized(0) <= '1';
|
| 620 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 621 |
|
|
tid=>x"06", address=>x"000158", data=>x"00000002");
|
| 622 |
|
|
|
| 623 |
|
|
linkInitialized(1) <= '0';
|
| 624 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 625 |
|
|
tid=>x"06", address=>x"000178", data=>x"00000001");
|
| 626 |
|
|
linkInitialized(1) <= '1';
|
| 627 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 628 |
|
|
tid=>x"06", address=>x"000178", data=>x"00000002");
|
| 629 |
|
|
|
| 630 |
|
|
linkInitialized(2) <= '0';
|
| 631 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 632 |
|
|
tid=>x"06", address=>x"000198", data=>x"00000001");
|
| 633 |
|
|
linkInitialized(2) <= '1';
|
| 634 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 635 |
|
|
tid=>x"06", address=>x"000198", data=>x"00000002");
|
| 636 |
|
|
|
| 637 |
|
|
linkInitialized(3) <= '0';
|
| 638 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 639 |
|
|
tid=>x"06", address=>x"0001b8", data=>x"00000001");
|
| 640 |
|
|
linkInitialized(3) <= '1';
|
| 641 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 642 |
|
|
tid=>x"06", address=>x"0001b8", data=>x"00000002");
|
| 643 |
|
|
|
| 644 |
|
|
linkInitialized(4) <= '0';
|
| 645 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 646 |
|
|
tid=>x"06", address=>x"0001d8", data=>x"00000001");
|
| 647 |
|
|
linkInitialized(4) <= '1';
|
| 648 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 649 |
|
|
tid=>x"06", address=>x"0001d8", data=>x"00000002");
|
| 650 |
|
|
|
| 651 |
|
|
linkInitialized(5) <= '0';
|
| 652 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 653 |
|
|
tid=>x"06", address=>x"0001f8", data=>x"00000001");
|
| 654 |
|
|
linkInitialized(5) <= '1';
|
| 655 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 656 |
|
|
tid=>x"06", address=>x"0001f8", data=>x"00000002");
|
| 657 |
|
|
|
| 658 |
|
|
linkInitialized(6) <= '0';
|
| 659 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 660 |
|
|
tid=>x"06", address=>x"000218", data=>x"00000001");
|
| 661 |
|
|
linkInitialized(6) <= '1';
|
| 662 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 663 |
|
|
tid=>x"06", address=>x"000218", data=>x"00000002");
|
| 664 |
|
|
|
| 665 |
|
|
---------------------------------------------------------------------------
|
| 666 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 667 |
|
|
PrintS("Step 10");
|
| 668 |
|
|
PrintS("Action: Read and write to/from the port N control.");
|
| 669 |
|
|
PrintS("Result: Check the output/input port enable.");
|
| 670 |
|
|
---------------------------------------------------------------------------
|
| 671 |
|
|
PrintR("TG_RioSwitch-TC1-Step10");
|
| 672 |
|
|
---------------------------------------------------------------------------
|
| 673 |
|
|
|
| 674 |
|
|
assert outputPortEnable(0) = '0' report "Unexpected outputPortEnable." severity error;
|
| 675 |
|
|
assert inputPortEnable(0) = '0' report "Unexpected inputPortEnable." severity error;
|
| 676 |
|
|
|
| 677 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 678 |
|
|
tid=>x"06", address=>x"00015c", data=>x"00000001");
|
| 679 |
|
|
|
| 680 |
|
|
WriteConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 681 |
|
|
tid=>x"06", address=>x"00015c", data=>x"00600001");
|
| 682 |
|
|
|
| 683 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 684 |
|
|
tid=>x"06", address=>x"00015c", data=>x"00600001");
|
| 685 |
|
|
|
| 686 |
|
|
assert outputPortEnable(0) = '1' report "Unexpected outputPortEnable." severity error;
|
| 687 |
|
|
assert inputPortEnable(0) = '1' report "Unexpected inputPortEnable." severity error;
|
| 688 |
|
|
|
| 689 |
|
|
---------------------------------------------------------------------------
|
| 690 |
|
|
|
| 691 |
|
|
assert outputPortEnable(1) = '0' report "Unexpected outputPortEnable." severity error;
|
| 692 |
|
|
assert inputPortEnable(1) = '0' report "Unexpected inputPortEnable." severity error;
|
| 693 |
|
|
|
| 694 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 695 |
|
|
tid=>x"06", address=>x"00017c", data=>x"00000001");
|
| 696 |
|
|
|
| 697 |
|
|
WriteConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 698 |
|
|
tid=>x"06", address=>x"00017c", data=>x"00600001");
|
| 699 |
|
|
|
| 700 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 701 |
|
|
tid=>x"06", address=>x"00017c", data=>x"00600001");
|
| 702 |
|
|
|
| 703 |
|
|
assert outputPortEnable(1) = '1' report "Unexpected outputPortEnable." severity error;
|
| 704 |
|
|
assert inputPortEnable(1) = '1' report "Unexpected inputPortEnable." severity error;
|
| 705 |
|
|
|
| 706 |
|
|
---------------------------------------------------------------------------
|
| 707 |
|
|
|
| 708 |
|
|
assert outputPortEnable(2) = '0' report "Unexpected outputPortEnable." severity error;
|
| 709 |
|
|
assert inputPortEnable(2) = '0' report "Unexpected inputPortEnable." severity error;
|
| 710 |
|
|
|
| 711 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 712 |
|
|
tid=>x"06", address=>x"00019c", data=>x"00000001");
|
| 713 |
|
|
|
| 714 |
|
|
WriteConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 715 |
|
|
tid=>x"06", address=>x"00019c", data=>x"00600001");
|
| 716 |
|
|
|
| 717 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 718 |
|
|
tid=>x"06", address=>x"00019c", data=>x"00600001");
|
| 719 |
|
|
|
| 720 |
|
|
assert outputPortEnable(2) = '1' report "Unexpected outputPortEnable." severity error;
|
| 721 |
|
|
assert inputPortEnable(2) = '1' report "Unexpected inputPortEnable." severity error;
|
| 722 |
|
|
|
| 723 |
|
|
---------------------------------------------------------------------------
|
| 724 |
|
|
|
| 725 |
|
|
assert outputPortEnable(3) = '0' report "Unexpected outputPortEnable." severity error;
|
| 726 |
|
|
assert inputPortEnable(3) = '0' report "Unexpected inputPortEnable." severity error;
|
| 727 |
|
|
|
| 728 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 729 |
|
|
tid=>x"06", address=>x"0001bc", data=>x"00000001");
|
| 730 |
|
|
|
| 731 |
|
|
WriteConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 732 |
|
|
tid=>x"06", address=>x"0001bc", data=>x"00600001");
|
| 733 |
|
|
|
| 734 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 735 |
|
|
tid=>x"06", address=>x"0001bc", data=>x"00600001");
|
| 736 |
|
|
|
| 737 |
|
|
assert outputPortEnable(3) = '1' report "Unexpected outputPortEnable." severity error;
|
| 738 |
|
|
assert inputPortEnable(3) = '1' report "Unexpected inputPortEnable." severity error;
|
| 739 |
|
|
|
| 740 |
|
|
---------------------------------------------------------------------------
|
| 741 |
|
|
|
| 742 |
|
|
assert outputPortEnable(4) = '0' report "Unexpected outputPortEnable." severity error;
|
| 743 |
|
|
assert inputPortEnable(4) = '0' report "Unexpected inputPortEnable." severity error;
|
| 744 |
|
|
|
| 745 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 746 |
|
|
tid=>x"06", address=>x"0001dc", data=>x"00000001");
|
| 747 |
|
|
|
| 748 |
|
|
WriteConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 749 |
|
|
tid=>x"06", address=>x"0001dc", data=>x"00600001");
|
| 750 |
|
|
|
| 751 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 752 |
|
|
tid=>x"06", address=>x"0001dc", data=>x"00600001");
|
| 753 |
|
|
|
| 754 |
|
|
assert outputPortEnable(4) = '1' report "Unexpected outputPortEnable." severity error;
|
| 755 |
|
|
assert inputPortEnable(4) = '1' report "Unexpected inputPortEnable." severity error;
|
| 756 |
|
|
|
| 757 |
|
|
---------------------------------------------------------------------------
|
| 758 |
|
|
|
| 759 |
|
|
assert outputPortEnable(5) = '0' report "Unexpected outputPortEnable." severity error;
|
| 760 |
|
|
assert inputPortEnable(5) = '0' report "Unexpected inputPortEnable." severity error;
|
| 761 |
|
|
|
| 762 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 763 |
|
|
tid=>x"06", address=>x"0001fc", data=>x"00000001");
|
| 764 |
|
|
|
| 765 |
|
|
WriteConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 766 |
|
|
tid=>x"06", address=>x"0001fc", data=>x"00600001");
|
| 767 |
|
|
|
| 768 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 769 |
|
|
tid=>x"06", address=>x"0001fc", data=>x"00600001");
|
| 770 |
|
|
|
| 771 |
|
|
assert outputPortEnable(5) = '1' report "Unexpected outputPortEnable." severity error;
|
| 772 |
|
|
assert inputPortEnable(5) = '1' report "Unexpected inputPortEnable." severity error;
|
| 773 |
|
|
|
| 774 |
|
|
---------------------------------------------------------------------------
|
| 775 |
|
|
|
| 776 |
|
|
assert outputPortEnable(6) = '0' report "Unexpected outputPortEnable." severity error;
|
| 777 |
|
|
assert inputPortEnable(6) = '0' report "Unexpected inputPortEnable." severity error;
|
| 778 |
|
|
|
| 779 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 780 |
|
|
tid=>x"06", address=>x"00021c", data=>x"00000001");
|
| 781 |
|
|
|
| 782 |
|
|
WriteConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 783 |
|
|
tid=>x"06", address=>x"00021c", data=>x"00600001");
|
| 784 |
|
|
|
| 785 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 786 |
|
|
tid=>x"06", address=>x"00021c", data=>x"00600001");
|
| 787 |
|
|
|
| 788 |
|
|
assert outputPortEnable(6) = '1' report "Unexpected outputPortEnable." severity error;
|
| 789 |
|
|
assert inputPortEnable(6) = '1' report "Unexpected inputPortEnable." severity error;
|
| 790 |
|
|
|
| 791 |
|
|
---------------------------------------------------------------------------
|
| 792 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 793 |
|
|
PrintS("Step 11");
|
| 794 |
|
|
PrintS("Action: Read and write to/from the implementation defined space.");
|
| 795 |
|
|
PrintS("Result: Check the accesses on the external configuration port.");
|
| 796 |
|
|
---------------------------------------------------------------------------
|
| 797 |
|
|
PrintR("TG_RioSwitch-TC1-Step11");
|
| 798 |
|
|
---------------------------------------------------------------------------
|
| 799 |
|
|
|
| 800 |
|
|
configStbExpected <= '1';
|
| 801 |
|
|
configWeExpected <= '0';
|
| 802 |
|
|
configAddrExpected <= x"010000";
|
| 803 |
|
|
configDataReadExpected <= x"deadbeef";
|
| 804 |
|
|
|
| 805 |
|
|
ReadConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 806 |
|
|
tid=>x"06", address=>x"010000", data=>x"deadbeef");
|
| 807 |
|
|
|
| 808 |
|
|
configStbExpected <= '1';
|
| 809 |
|
|
configWeExpected <= '1';
|
| 810 |
|
|
configAddrExpected <= x"010004";
|
| 811 |
|
|
configDataWriteExpected <= x"c0debabe";
|
| 812 |
|
|
|
| 813 |
|
|
WriteConfig32(portIndex=>6, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 814 |
|
|
tid=>x"06", address=>x"010004", data=>x"c0debabe");
|
| 815 |
|
|
|
| 816 |
|
|
---------------------------------------------------------------------------
|
| 817 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 818 |
|
|
PrintS("TG_RioSwitch-TC2");
|
| 819 |
|
|
PrintS("Description: Test the configuration of the routing table and the ");
|
| 820 |
|
|
PrintS(" routing of packets.");
|
| 821 |
|
|
PrintS("Requirement: XXXXX");
|
| 822 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 823 |
|
|
PrintS("Step 1:");
|
| 824 |
|
|
PrintS("Action: Configure the routing table for address 0->port 1.");
|
| 825 |
|
|
PrintS("Result: A packet to address 0 should be forwarded to port 1.");
|
| 826 |
|
|
---------------------------------------------------------------------------
|
| 827 |
|
|
PrintR("TG_RioSwitch-TC2-Step1");
|
| 828 |
|
|
---------------------------------------------------------------------------
|
| 829 |
|
|
|
| 830 |
|
|
ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 831 |
|
|
tid=>x"07", address=>x"000070", data=>x"00000000");
|
| 832 |
|
|
WriteConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 833 |
|
|
tid=>x"08", address=>x"000074", data=>x"00000001");
|
| 834 |
|
|
ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 835 |
|
|
tid=>x"09", address=>x"000074", data=>x"00000001");
|
| 836 |
|
|
|
| 837 |
|
|
-- Send a frame from a port and check if it is correctly routed.
|
| 838 |
|
|
randomPayload.length := 3;
|
| 839 |
|
|
CreateRandomPayload(randomPayload.data, seed1, seed2);
|
| 840 |
|
|
RouteFrame(sourcePortIndex=>0, destinationPortIndex=>1,
|
| 841 |
|
|
sourceId=>x"ffff", destinationId=>x"0000", payload=>randomPayload);
|
| 842 |
|
|
|
| 843 |
|
|
---------------------------------------------------------------------------
|
| 844 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 845 |
|
|
PrintS("Step 2:");
|
| 846 |
|
|
PrintS("Action: Test the configuration of the default route->port 6.");
|
| 847 |
|
|
PrintS("Result: An unknown address should be routed to port 6.");
|
| 848 |
|
|
---------------------------------------------------------------------------
|
| 849 |
|
|
PrintR("TG_RioSwitch-TC2-Step2");
|
| 850 |
|
|
---------------------------------------------------------------------------
|
| 851 |
|
|
|
| 852 |
|
|
ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 853 |
|
|
tid=>x"0a", address=>x"000078", data=>x"00000000");
|
| 854 |
|
|
WriteConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 855 |
|
|
tid=>x"0b", address=>x"000078", data=>x"00000006");
|
| 856 |
|
|
ReadConfig32(portIndex=>0, destinationId=>x"0000", sourceId=>x"0002", hop=>x"00",
|
| 857 |
|
|
tid=>x"0c", address=>x"000078", data=>x"00000006");
|
| 858 |
|
|
|
| 859 |
|
|
-- Send a frame from a port and check if it is correctly routed.
|
| 860 |
|
|
randomPayload.length := 4;
|
| 861 |
|
|
CreateRandomPayload(randomPayload.data, seed1, seed2);
|
| 862 |
|
|
RouteFrame(sourcePortIndex=>1, destinationPortIndex=>6,
|
| 863 |
|
|
sourceId=>x"0000", destinationId=>x"ffff", payload=>randomPayload);
|
| 864 |
|
|
|
| 865 |
|
|
---------------------------------------------------------------------------
|
| 866 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 867 |
|
|
PrintS("TG_RioSwitch-TC3");
|
| 868 |
|
|
PrintS("Description: Test the routing of normal packets.");
|
| 869 |
|
|
PrintS("Requirement: XXXXX");
|
| 870 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 871 |
|
|
PrintS("Step 1:");
|
| 872 |
|
|
PrintS("Action: Send two packets but not the same time.");
|
| 873 |
|
|
PrintS("Result: Both packets should be received at the expected ports.");
|
| 874 |
|
|
---------------------------------------------------------------------------
|
| 875 |
|
|
PrintR("TG_RioSwitch-TC3-Step1");
|
| 876 |
|
|
---------------------------------------------------------------------------
|
| 877 |
|
|
|
| 878 |
|
|
-- Frame on port 0 to port 1.
|
| 879 |
|
|
randomPayload.length := 3;
|
| 880 |
|
|
CreateRandomPayload(randomPayload.data, seed1, seed2);
|
| 881 |
|
|
SendFrame(portIndex=>0,
|
| 882 |
|
|
sourceId=>x"ffff", destinationId=>x"0000", payload=>randomPayload);
|
| 883 |
|
|
ReceiveFrame(portIndex=>1,
|
| 884 |
|
|
sourceId=>x"ffff", destinationId=>x"0000", payload=>randomPayload);
|
| 885 |
|
|
|
| 886 |
|
|
-- Frame on port 1 to port 6.
|
| 887 |
|
|
randomPayload.length := 4;
|
| 888 |
|
|
CreateRandomPayload(randomPayload.data, seed1, seed2);
|
| 889 |
|
|
SendFrame(portIndex=>1,
|
| 890 |
|
|
sourceId=>x"0000", destinationId=>x"ffff", payload=>randomPayload);
|
| 891 |
|
|
ReceiveFrame(portIndex=>6,
|
| 892 |
|
|
sourceId=>x"0000", destinationId=>x"ffff", payload=>randomPayload);
|
| 893 |
|
|
|
| 894 |
|
|
wait until frameComplete(1) = '1';
|
| 895 |
|
|
frameValid(1) <= '0';
|
| 896 |
|
|
wait until frameReceived(6) = '1';
|
| 897 |
|
|
frameExpected(6) <= '0';
|
| 898 |
|
|
|
| 899 |
|
|
wait until frameComplete(0) = '1';
|
| 900 |
|
|
frameValid(0) <= '0';
|
| 901 |
|
|
wait until frameReceived(1) = '1';
|
| 902 |
|
|
frameExpected(1) <= '0';
|
| 903 |
|
|
|
| 904 |
|
|
---------------------------------------------------------------------------
|
| 905 |
|
|
PrintS("-----------------------------------------------------------------");
|
| 906 |
|
|
PrintS("Step 2:");
|
| 907 |
|
|
PrintS("Action: Send two packets to the same port with is full and one to");
|
| 908 |
|
|
PrintS(" another that is also full. Then receive the packets one at");
|
| 909 |
|
|
PrintS(" a time.");
|
| 910 |
|
|
PrintS("Result: The packet to the port that is ready should go though.");
|
| 911 |
|
|
---------------------------------------------------------------------------
|
| 912 |
|
|
PrintR("TG_RioSwitch-TC3-Step2");
|
| 913 |
|
|
---------------------------------------------------------------------------
|
| 914 |
|
|
|
| 915 |
|
|
-- Frame on port 0 to port 1.
|
| 916 |
|
|
randomPayload.length := 5;
|
| 917 |
|
|
CreateRandomPayload(randomPayload.data, seed1, seed2);
|
| 918 |
|
|
SendFrame(portIndex=>0,
|
| 919 |
|
|
sourceId=>x"ffff", destinationId=>x"0000", payload=>randomPayload);
|
| 920 |
|
|
|
| 921 |
|
|
-- Frame on port 1 to port 6.
|
| 922 |
|
|
randomPayload1.length := 6;
|
| 923 |
|
|
CreateRandomPayload(randomPayload1.data, seed1, seed2);
|
| 924 |
|
|
SendFrame(portIndex=>1,
|
| 925 |
|
|
sourceId=>x"0000", destinationId=>x"ffff", payload=>randomPayload1);
|
| 926 |
|
|
|
| 927 |
|
|
-- Frame on port 2 to port 6.
|
| 928 |
|
|
randomPayload2.length := 7;
|
| 929 |
|
|
CreateRandomPayload(randomPayload2.data, seed1, seed2);
|
| 930 |
|
|
SendFrame(portIndex=>2,
|
| 931 |
|
|
sourceId=>x"0000", destinationId=>x"ffff", payload=>randomPayload2);
|
| 932 |
|
|
|
| 933 |
|
|
wait for 10 us;
|
| 934 |
|
|
|
| 935 |
|
|
ReceiveFrame(portIndex=>1,
|
| 936 |
|
|
sourceId=>x"ffff", destinationId=>x"0000", payload=>randomPayload);
|
| 937 |
|
|
wait until frameComplete(0) = '1';
|
| 938 |
|
|
frameValid(0) <= '0';
|
| 939 |
|
|
wait until frameReceived(1) = '1';
|
| 940 |
|
|
frameExpected(1) <= '0';
|
| 941 |
|
|
|
| 942 |
|
|
wait for 10 us;
|
| 943 |
|
|
|
| 944 |
|
|
ReceiveFrame(portIndex=>6,
|
| 945 |
|
|
sourceId=>x"0000", destinationId=>x"ffff", payload=>randomPayload1);
|
| 946 |
|
|
wait until frameComplete(1) = '1';
|
| 947 |
|
|
frameValid(1) <= '0';
|
| 948 |
|
|
wait until frameReceived(6) = '1';
|
| 949 |
|
|
frameExpected(6) <= '0';
|
| 950 |
|
|
|
| 951 |
|
|
wait for 10 us;
|
| 952 |
|
|
|
| 953 |
|
|
ReceiveFrame(portIndex=>6,
|
| 954 |
|
|
sourceId=>x"0000", destinationId=>x"ffff", payload=>randomPayload2);
|
| 955 |
|
|
wait until frameComplete(2) = '1';
|
| 956 |
|
|
frameValid(2) <= '0';
|
| 957 |
|
|
wait until frameReceived(6) = '1';
|
| 958 |
|
|
frameExpected(6) <= '0';
|
| 959 |
|
|
|
| 960 |
|
|
---------------------------------------------------------------------------
|
| 961 |
|
|
-- Test completed.
|
| 962 |
|
|
---------------------------------------------------------------------------
|
| 963 |
|
|
|
| 964 |
|
|
wait for 10 us;
|
| 965 |
|
|
|
| 966 |
|
|
assert readContentEmpty = "1111111"
|
| 967 |
|
|
report "Pending frames exist." severity error;
|
| 968 |
|
|
|
| 969 |
|
|
TestEnd;
|
| 970 |
|
|
end process;
|
| 971 |
|
|
|
| 972 |
|
|
-----------------------------------------------------------------------------
|
| 973 |
|
|
-- Instantiate a process receiving the configuration accesses to the
|
| 974 |
|
|
-- implementation defined space.
|
| 975 |
|
|
-----------------------------------------------------------------------------
|
| 976 |
|
|
process
|
| 977 |
|
|
begin
|
| 978 |
|
|
loop
|
| 979 |
|
|
wait until configStb = '1' and clk'event and clk = '1';
|
| 980 |
|
|
assert configStb = configStbExpected report "Unexpected configStb." severity error;
|
| 981 |
|
|
assert configWe = configWeExpected report "Unexpected configWe." severity error;
|
| 982 |
|
|
assert configAddr = configAddrExpected report "Unexpected configAddr." severity error;
|
| 983 |
|
|
if (configWe = '1') then
|
| 984 |
|
|
assert configDataWrite = configDataWriteExpected report "Unexpected configDataWrite." severity error;
|
| 985 |
|
|
else
|
| 986 |
|
|
configDataRead <= configDataReadExpected;
|
| 987 |
|
|
end if;
|
| 988 |
|
|
end loop;
|
| 989 |
|
|
end process;
|
| 990 |
|
|
|
| 991 |
|
|
-----------------------------------------------------------------------------
|
| 992 |
|
|
-- Instantiate the test port array.
|
| 993 |
|
|
-----------------------------------------------------------------------------
|
| 994 |
|
|
|
| 995 |
|
|
TestPortGeneration: for portIndex in 0 to PORTS-1 generate
|
| 996 |
|
|
TestPortInst: TestPort
|
| 997 |
|
|
port map(
|
| 998 |
|
|
clk=>clk, areset_n=>areset_n,
|
| 999 |
|
|
frameValid_i=>frameValid(portIndex),
|
| 1000 |
|
|
frameWrite_i=>frameWrite(portIndex),
|
| 1001 |
|
|
frameComplete_o=>frameComplete(portIndex),
|
| 1002 |
|
|
frameExpected_i=>frameExpected(portIndex),
|
| 1003 |
|
|
frameRead_i=>frameRead(portIndex),
|
| 1004 |
|
|
frameReceived_o=>frameReceived(portIndex),
|
| 1005 |
|
|
readFrameEmpty_o=>readFrameEmpty(portIndex),
|
| 1006 |
|
|
readFrame_i=>readFrame(portIndex),
|
| 1007 |
|
|
readFrameRestart_i=>readFrameRestart(portIndex),
|
| 1008 |
|
|
readFrameAborted_o=>readFrameAborted(portIndex),
|
| 1009 |
|
|
readContentEmpty_o=>readContentEmpty(portIndex),
|
| 1010 |
|
|
readContent_i=>readContent(portIndex),
|
| 1011 |
|
|
readContentEnd_o=>readContentEnd(portIndex),
|
| 1012 |
|
|
readContentData_o=>readContentData(portIndex),
|
| 1013 |
|
|
writeFrameFull_o=>writeFrameFull(portIndex),
|
| 1014 |
|
|
writeFrame_i=>writeFrame(portIndex),
|
| 1015 |
|
|
writeFrameAbort_i=>writeFrameAbort(portIndex),
|
| 1016 |
|
|
writeContent_i=>writeContent(portIndex),
|
| 1017 |
|
|
writeContentData_i=>writeContentData(portIndex));
|
| 1018 |
|
|
end generate;
|
| 1019 |
|
|
|
| 1020 |
|
|
-----------------------------------------------------------------------------
|
| 1021 |
|
|
-- Instantiate the switch.
|
| 1022 |
|
|
-----------------------------------------------------------------------------
|
| 1023 |
|
|
|
| 1024 |
|
|
TestSwitch: RioSwitch
|
| 1025 |
|
|
generic map(
|
| 1026 |
|
|
SWITCH_PORTS=>7,
|
| 1027 |
|
|
DEVICE_IDENTITY=>SWITCH_IDENTITY,
|
| 1028 |
|
|
DEVICE_VENDOR_IDENTITY=>SWITCH_VENDOR_IDENTITY,
|
| 1029 |
|
|
DEVICE_REV=>SWITCH_REV,
|
| 1030 |
|
|
ASSY_IDENTITY=>SWITCH_ASSY_IDENTITY,
|
| 1031 |
|
|
ASSY_VENDOR_IDENTITY=>SWITCH_ASSY_VENDOR_IDENTITY,
|
| 1032 |
|
|
ASSY_REV=>SWITCH_ASSY_REV)
|
| 1033 |
|
|
port map(
|
| 1034 |
|
|
clk=>clk, areset_n=>areset_n,
|
| 1035 |
|
|
writeFrameFull_i=>writeFrameFull,
|
| 1036 |
|
|
writeFrame_o=>writeFrame, writeFrameAbort_o=>writeFrameAbort,
|
| 1037 |
|
|
writeContent_o=>writeContent, writeContentData_o=>writeContentData,
|
| 1038 |
|
|
readFrameEmpty_i=>readFrameEmpty,
|
| 1039 |
|
|
readFrame_o=>readFrame, readFrameRestart_o=>readFrameRestart,
|
| 1040 |
|
|
readFrameAborted_i=>readFrameAborted,
|
| 1041 |
|
|
readContentEmpty_i=>readContentEmpty,
|
| 1042 |
|
|
readContent_o=>readContent, readContentEnd_i=>readContentEnd,
|
| 1043 |
|
|
readContentData_i=>readContentData,
|
| 1044 |
|
|
portLinkTimeout_o=>portLinkTimeout,
|
| 1045 |
|
|
linkInitialized_i=>linkInitialized,
|
| 1046 |
|
|
outputPortEnable_o=>outputPortEnable, inputPortEnable_o=>inputPortEnable,
|
| 1047 |
|
|
localAckIdWrite_o=>localAckIdWrite,
|
| 1048 |
|
|
clrOutstandingAckId_o=>clrOutstandingAckId,
|
| 1049 |
|
|
inboundAckId_o=>inboundAckIdWrite,
|
| 1050 |
|
|
outstandingAckId_o=>outstandingAckIdWrite,
|
| 1051 |
|
|
outboundAckId_o=>outboundAckIdWrite,
|
| 1052 |
|
|
inboundAckId_i=>inboundAckIdRead,
|
| 1053 |
|
|
outstandingAckId_i=>outstandingAckIdRead,
|
| 1054 |
|
|
outboundAckId_i=>outboundAckIdRead,
|
| 1055 |
|
|
configStb_o=>configStb, configWe_o=>configWe, configAddr_o=>configAddr,
|
| 1056 |
|
|
configData_o=>configDataWrite, configData_i=>configDataRead);
|
| 1057 |
|
|
|
| 1058 |
|
|
|
| 1059 |
|
|
end architecture;
|
| 1060 |
|
|
|
| 1061 |
|
|
|
| 1062 |
|
|
|
| 1063 |
|
|
-------------------------------------------------------------------------------
|
| 1064 |
|
|
--
|
| 1065 |
|
|
-------------------------------------------------------------------------------
|
| 1066 |
|
|
-- REMARK: Add support for testing partially complete frames, cut-through-routing...
|
| 1067 |
|
|
library ieee;
|
| 1068 |
|
|
use ieee.std_logic_1164.all;
|
| 1069 |
|
|
use ieee.numeric_std.all;
|
| 1070 |
|
|
library std;
|
| 1071 |
|
|
use std.textio.all;
|
| 1072 |
|
|
use work.rio_common.all;
|
| 1073 |
|
|
|
| 1074 |
|
|
|
| 1075 |
|
|
-------------------------------------------------------------------------------
|
| 1076 |
|
|
--
|
| 1077 |
|
|
-------------------------------------------------------------------------------
|
| 1078 |
|
|
entity TestPort is
|
| 1079 |
|
|
port(
|
| 1080 |
|
|
clk : in std_logic;
|
| 1081 |
|
|
areset_n : in std_logic;
|
| 1082 |
|
|
|
| 1083 |
|
|
frameValid_i : in std_logic;
|
| 1084 |
|
|
frameWrite_i : in RioFrame;
|
| 1085 |
|
|
frameComplete_o : out std_logic;
|
| 1086 |
|
|
|
| 1087 |
|
|
frameExpected_i : in std_logic;
|
| 1088 |
|
|
frameRead_i : in RioFrame;
|
| 1089 |
|
|
frameReceived_o : out std_logic;
|
| 1090 |
|
|
|
| 1091 |
|
|
readFrameEmpty_o : out std_logic;
|
| 1092 |
|
|
readFrame_i : in std_logic;
|
| 1093 |
|
|
readFrameRestart_i : in std_logic;
|
| 1094 |
|
|
readFrameAborted_o : out std_logic;
|
| 1095 |
|
|
readContentEmpty_o : out std_logic;
|
| 1096 |
|
|
readContent_i : in std_logic;
|
| 1097 |
|
|
readContentEnd_o : out std_logic;
|
| 1098 |
|
|
readContentData_o : out std_logic_vector(31 downto 0);
|
| 1099 |
|
|
|
| 1100 |
|
|
writeFrameFull_o : out std_logic;
|
| 1101 |
|
|
writeFrame_i : in std_logic;
|
| 1102 |
|
|
writeFrameAbort_i : in std_logic;
|
| 1103 |
|
|
writeContent_i : in std_logic;
|
| 1104 |
|
|
writeContentData_i : in std_logic_vector(31 downto 0));
|
| 1105 |
|
|
end entity;
|
| 1106 |
|
|
|
| 1107 |
|
|
|
| 1108 |
|
|
-------------------------------------------------------------------------------
|
| 1109 |
|
|
--
|
| 1110 |
|
|
-------------------------------------------------------------------------------
|
| 1111 |
|
|
architecture TestPortImpl of TestPort is
|
| 1112 |
|
|
begin
|
| 1113 |
|
|
|
| 1114 |
|
|
-----------------------------------------------------------------------------
|
| 1115 |
|
|
--
|
| 1116 |
|
|
-----------------------------------------------------------------------------
|
| 1117 |
|
|
FrameReader: process
|
| 1118 |
|
|
type StateType is (STATE_IDLE, STATE_WRITE);
|
| 1119 |
|
|
variable state : StateType;
|
| 1120 |
|
|
variable frameIndex : natural range 0 to 69;
|
| 1121 |
|
|
begin
|
| 1122 |
|
|
writeFrameFull_o <= '1';
|
| 1123 |
|
|
frameReceived_o <= '0';
|
| 1124 |
|
|
wait until areset_n = '1';
|
| 1125 |
|
|
|
| 1126 |
|
|
state := STATE_IDLE;
|
| 1127 |
|
|
|
| 1128 |
|
|
loop
|
| 1129 |
|
|
wait until clk'event and clk = '1';
|
| 1130 |
|
|
|
| 1131 |
|
|
case state is
|
| 1132 |
|
|
|
| 1133 |
|
|
when STATE_IDLE =>
|
| 1134 |
|
|
frameReceived_o <= '0';
|
| 1135 |
|
|
if (frameExpected_i = '1') then
|
| 1136 |
|
|
writeFrameFull_o <= '0';
|
| 1137 |
|
|
state := STATE_WRITE;
|
| 1138 |
|
|
frameIndex := 0;
|
| 1139 |
|
|
else
|
| 1140 |
|
|
writeFrameFull_o <= '1';
|
| 1141 |
|
|
end if;
|
| 1142 |
|
|
assert writeFrame_i = '0' report "Unexpected frame." severity error;
|
| 1143 |
|
|
assert writeFrameAbort_i = '0' report "Unexpected frame abort." severity error;
|
| 1144 |
|
|
assert writeContent_i = '0' report "Unexpected data." severity error;
|
| 1145 |
|
|
|
| 1146 |
|
|
when STATE_WRITE =>
|
| 1147 |
|
|
if (writeContent_i = '1') then
|
| 1148 |
|
|
-- Writing content.
|
| 1149 |
|
|
if (frameIndex < frameRead_i.length) then
|
| 1150 |
|
|
assert writeContentData_i = frameRead_i.payload(frameIndex)
|
| 1151 |
|
|
report "Unexpected frame content received:" &
|
| 1152 |
|
|
" index=" & integer'image(frameIndex) &
|
| 1153 |
|
|
" expected=" & integer'image(to_integer(unsigned(frameRead_i.payload(frameIndex)))) &
|
| 1154 |
|
|
" got=" & integer'image(to_integer(unsigned(writeContentData_i)))
|
| 1155 |
|
|
severity error;
|
| 1156 |
|
|
|
| 1157 |
|
|
frameIndex := frameIndex + 1;
|
| 1158 |
|
|
else
|
| 1159 |
|
|
report "Unexpected frame content received:" &
|
| 1160 |
|
|
" index=" & integer'image(frameIndex) &
|
| 1161 |
|
|
" expected=" & integer'image(to_integer(unsigned(frameRead_i.payload(frameIndex)))) &
|
| 1162 |
|
|
" got=" & integer'image(to_integer(unsigned(writeContentData_i)))
|
| 1163 |
|
|
severity error;
|
| 1164 |
|
|
|
| 1165 |
|
|
frameIndex := frameIndex + 1;
|
| 1166 |
|
|
end if;
|
| 1167 |
|
|
else
|
| 1168 |
|
|
-- Not writing any content.
|
| 1169 |
|
|
end if;
|
| 1170 |
|
|
|
| 1171 |
|
|
if (writeFrame_i = '1') then
|
| 1172 |
|
|
-- Writing a complete frame.
|
| 1173 |
|
|
assert frameIndex = frameRead_i.length report "Unexpected frame length received." severity error;
|
| 1174 |
|
|
state := STATE_IDLE;
|
| 1175 |
|
|
frameReceived_o <= '1';
|
| 1176 |
|
|
writeFrameFull_o <= '1';
|
| 1177 |
|
|
else
|
| 1178 |
|
|
-- Not writing any frame.
|
| 1179 |
|
|
end if;
|
| 1180 |
|
|
|
| 1181 |
|
|
if (writeFrameAbort_i = '1') then
|
| 1182 |
|
|
-- The frame should be aborted.
|
| 1183 |
|
|
frameIndex := 0;
|
| 1184 |
|
|
else
|
| 1185 |
|
|
-- Not aborting any frame.
|
| 1186 |
|
|
end if;
|
| 1187 |
|
|
end case;
|
| 1188 |
|
|
end loop;
|
| 1189 |
|
|
end process;
|
| 1190 |
|
|
|
| 1191 |
|
|
-----------------------------------------------------------------------------
|
| 1192 |
|
|
--
|
| 1193 |
|
|
-----------------------------------------------------------------------------
|
| 1194 |
|
|
-- REMARK: add support for these signals...
|
| 1195 |
|
|
-- readFrameEmpty_i : in std_logic;
|
| 1196 |
|
|
-- readFrameAborted_i : in std_logic;
|
| 1197 |
|
|
FrameSender: process
|
| 1198 |
|
|
type StateType is (STATE_IDLE, STATE_READ);
|
| 1199 |
|
|
variable state : StateType;
|
| 1200 |
|
|
variable frameIndex : natural range 0 to 69;
|
| 1201 |
|
|
begin
|
| 1202 |
|
|
readFrameEmpty_o <= '1';
|
| 1203 |
|
|
readFrameAborted_o <= '0';
|
| 1204 |
|
|
readContentEmpty_o <= '1';
|
| 1205 |
|
|
readContentEnd_o <= '1';
|
| 1206 |
|
|
readContentData_o <= (others => 'U');
|
| 1207 |
|
|
frameComplete_o <= '0';
|
| 1208 |
|
|
wait until areset_n = '1';
|
| 1209 |
|
|
|
| 1210 |
|
|
state := STATE_IDLE;
|
| 1211 |
|
|
|
| 1212 |
|
|
loop
|
| 1213 |
|
|
wait until clk'event and clk = '1';
|
| 1214 |
|
|
|
| 1215 |
|
|
case state is
|
| 1216 |
|
|
|
| 1217 |
|
|
when STATE_IDLE =>
|
| 1218 |
|
|
frameComplete_o <= '0';
|
| 1219 |
|
|
if (frameValid_i = '1') then
|
| 1220 |
|
|
state := STATE_READ;
|
| 1221 |
|
|
frameIndex := 0;
|
| 1222 |
|
|
readContentEmpty_o <= '0';
|
| 1223 |
|
|
readFrameEmpty_o <= '0';
|
| 1224 |
|
|
else
|
| 1225 |
|
|
readContentEmpty_o <= '1';
|
| 1226 |
|
|
end if;
|
| 1227 |
|
|
|
| 1228 |
|
|
when STATE_READ =>
|
| 1229 |
|
|
if (readFrameRestart_i = '1') then
|
| 1230 |
|
|
readContentEnd_o <= '0';
|
| 1231 |
|
|
frameIndex := 0;
|
| 1232 |
|
|
else
|
| 1233 |
|
|
-- Not restarting a frame.
|
| 1234 |
|
|
end if;
|
| 1235 |
|
|
|
| 1236 |
|
|
if (readContent_i = '1') then
|
| 1237 |
|
|
if (frameIndex < frameWrite_i.length) then
|
| 1238 |
|
|
readContentData_o <= frameWrite_i.payload(frameIndex);
|
| 1239 |
|
|
readContentEnd_o <= '0';
|
| 1240 |
|
|
frameIndex := frameIndex + 1;
|
| 1241 |
|
|
elsif (frameIndex = frameWrite_i.length) then
|
| 1242 |
|
|
readContentEnd_o <= '1';
|
| 1243 |
|
|
else
|
| 1244 |
|
|
report "Reading empty frame." severity error;
|
| 1245 |
|
|
end if;
|
| 1246 |
|
|
else
|
| 1247 |
|
|
-- Not reading data.
|
| 1248 |
|
|
end if;
|
| 1249 |
|
|
|
| 1250 |
|
|
if (readFrame_i = '1') then
|
| 1251 |
|
|
state := STATE_IDLE;
|
| 1252 |
|
|
assert frameIndex = frameWrite_i.length report "Unread frame data discarded." severity error;
|
| 1253 |
|
|
frameComplete_o <= '1';
|
| 1254 |
|
|
readFrameEmpty_o <= '1';
|
| 1255 |
|
|
readContentEmpty_o <= '1';
|
| 1256 |
|
|
readContentData_o <= (others => 'U');
|
| 1257 |
|
|
else
|
| 1258 |
|
|
-- Not reading a frame.
|
| 1259 |
|
|
end if;
|
| 1260 |
|
|
|
| 1261 |
|
|
end case;
|
| 1262 |
|
|
end loop;
|
| 1263 |
|
|
end process;
|
| 1264 |
|
|
|
| 1265 |
|
|
end architecture;
|
