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magro732 |
-------------------------------------------------------------------------------
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--
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-- RapidIO IP Library Core
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--
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-- This file is part of the RapidIO IP library project
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-- http://www.opencores.org/cores/rio/
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--
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-- Description
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-- Contains commonly used types, functions, procedures and entities used in
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-- the RapidIO IP library project.
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--
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-- To Do:
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-- -
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--
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-- Author(s):
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-- - Magnus Rosenius, magro732@opencores.org
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2013 Authors and OPENCORES.ORG
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- RioCommon library.
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use std.textio.all;
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-------------------------------------------------------------------------------
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-- RioCommon package description.
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-------------------------------------------------------------------------------
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package rio_common is
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-----------------------------------------------------------------------------
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-- Commonly used types.
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-----------------------------------------------------------------------------
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type Array1 is array (natural range <>) of
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std_logic;
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type Array2 is array (natural range <>) of
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std_logic_vector(1 downto 0);
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type Array3 is array (natural range <>) of
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std_logic_vector(2 downto 0);
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type Array4 is array (natural range <>) of
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std_logic_vector(3 downto 0);
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type Array5 is array (natural range <>) of
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std_logic_vector(4 downto 0);
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type Array8 is array (natural range <>) of
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std_logic_vector(7 downto 0);
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type Array9 is array (natural range <>) of
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std_logic_vector(8 downto 0);
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type Array10 is array (natural range <>) of
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std_logic_vector(9 downto 0);
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type Array16 is array (natural range <>) of
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std_logic_vector(15 downto 0);
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type Array32 is array (natural range <>) of
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std_logic_vector(31 downto 0);
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type Array34 is array (natural range <>) of
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std_logic_vector(33 downto 0);
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-----------------------------------------------------------------------------
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-- Commonly used constants.
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-----------------------------------------------------------------------------
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-- Symbol types between the serial and the PCS layer.
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constant SYMBOL_IDLE : std_logic_vector(1 downto 0) := "00";
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constant SYMBOL_CONTROL : std_logic_vector(1 downto 0) := "01";
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constant SYMBOL_ERROR : std_logic_vector(1 downto 0) := "10";
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constant SYMBOL_DATA : std_logic_vector(1 downto 0) := "11";
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-- STYPE0 constants.
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constant STYPE0_PACKET_ACCEPTED : std_logic_vector(2 downto 0) := "000";
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constant STYPE0_PACKET_RETRY : std_logic_vector(2 downto 0) := "001";
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constant STYPE0_PACKET_NOT_ACCEPTED : std_logic_vector(2 downto 0) := "010";
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constant STYPE0_RESERVED : std_logic_vector(2 downto 0) := "011";
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constant STYPE0_STATUS : std_logic_vector(2 downto 0) := "100";
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constant STYPE0_VC_STATUS : std_logic_vector(2 downto 0) := "101";
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constant STYPE0_LINK_RESPONSE : std_logic_vector(2 downto 0) := "110";
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constant STYPE0_IMPLEMENTATION_DEFINED : std_logic_vector(2 downto 0) := "111";
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-- STYPE1 constants.
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constant STYPE1_START_OF_PACKET : std_logic_vector(2 downto 0) := "000";
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constant STYPE1_STOMP : std_logic_vector(2 downto 0) := "001";
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constant STYPE1_END_OF_PACKET : std_logic_vector(2 downto 0) := "010";
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constant STYPE1_RESTART_FROM_RETRY : std_logic_vector(2 downto 0) := "011";
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constant STYPE1_LINK_REQUEST : std_logic_vector(2 downto 0) := "100";
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constant STYPE1_MULTICAST_EVENT : std_logic_vector(2 downto 0) := "101";
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constant STYPE1_RESERVED : std_logic_vector(2 downto 0) := "110";
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constant STYPE1_NOP : std_logic_vector(2 downto 0) := "111";
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-- FTYPE constants.
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constant FTYPE_REQUEST_CLASS : std_logic_vector(3 downto 0) := "0010";
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constant FTYPE_WRITE_CLASS : std_logic_vector(3 downto 0) := "0101";
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constant FTYPE_STREAMING_WRITE_CLASS : std_logic_vector(3 downto 0) := "0110";
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constant FTYPE_MAINTENANCE_CLASS : std_logic_vector(3 downto 0) := "1000";
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constant FTYPE_RESPONSE_CLASS : std_logic_vector(3 downto 0) := "1101";
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constant FTYPE_DOORBELL_CLASS : std_logic_vector(3 downto 0) := "1010";
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constant FTYPE_MESSAGE_CLASS : std_logic_vector(3 downto 0) := "0010";
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-- TTYPE Constants
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constant TTYPE_MAINTENANCE_READ_REQUEST : std_logic_vector(3 downto 0) := "0000";
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constant TTYPE_MAINTENANCE_WRITE_REQUEST : std_logic_vector(3 downto 0) := "0001";
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constant TTYPE_MAINTENANCE_READ_RESPONSE : std_logic_vector(3 downto 0) := "0010";
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constant TTYPE_MAINTENANCE_WRITE_RESPONSE : std_logic_vector(3 downto 0) := "0011";
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constant TTYPE_NREAD_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
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constant TTYPE_NWRITE_TRANSACTION : std_logic_vector(3 downto 0) := "0100";
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constant LINK_REQUEST_CMD_RESET_DEVICE : std_logic_vector(2 downto 0) := "011";
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constant LINK_REQUEST_CMD_INPUT_STATUS : std_logic_vector(2 downto 0) := "100";
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constant PACKET_NOT_ACCEPTED_CAUSE_UNEXPECTED_ACKID : std_logic_vector(4 downto 0) := "00001";
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constant PACKET_NOT_ACCEPTED_CAUSE_CONTROL_CRC : std_logic_vector(4 downto 0) := "00010";
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constant PACKET_NOT_ACCEPTED_CAUSE_NON_MAINTENANCE_STOPPED : std_logic_vector(4 downto 0) := "00011";
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constant PACKET_NOT_ACCEPTED_CAUSE_PACKET_CRC : std_logic_vector(4 downto 0) := "00100";
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constant PACKET_NOT_ACCEPTED_CAUSE_INVALID_CHARACTER : std_logic_vector(4 downto 0) := "00101";
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constant PACKET_NOT_ACCEPTED_CAUSE_NO_RESOURCES : std_logic_vector(4 downto 0) := "00110";
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constant PACKET_NOT_ACCEPTED_CAUSE_LOSS_DESCRAMBLER : std_logic_vector(4 downto 0) := "00111";
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constant PACKET_NOT_ACCEPTED_CAUSE_GENERAL_ERROR : std_logic_vector(4 downto 0) := "11111";
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-----------------------------------------------------------------------------
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-- Types used in simulations.
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-----------------------------------------------------------------------------
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type ByteArray is array (natural range <>) of
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std_logic_vector(7 downto 0);
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type HalfwordArray is array (natural range <>) of
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std_logic_vector(15 downto 0);
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type WordArray is array (natural range <>) of
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std_logic_vector(31 downto 0);
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type DoublewordArray is array (natural range <>) of
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std_logic_vector(63 downto 0);
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-- Type defining a RapidIO frame.
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type RioFrame is record
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length : natural range 0 to 69;
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payload : WordArray(0 to 68);
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end record;
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type RioFrameArray is array (natural range <>) of RioFrame;
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-- Type defining a RapidIO payload.
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type RioPayload is record
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length : natural range 0 to 133;
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data : HalfwordArray(0 to 132);
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end record;
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-----------------------------------------------------------------------------
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-- Crc5 calculation function.
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-- ITU, polynom=0x15.
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-----------------------------------------------------------------------------
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function Crc5(constant data : in std_logic_vector(18 downto 0);
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constant crc : in std_logic_vector(4 downto 0))
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return std_logic_vector;
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---------------------------------------------------------------------------
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-- Create a RapidIO physical layer control symbol.
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---------------------------------------------------------------------------
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function RioControlSymbolCreate(
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constant stype0 : in std_logic_vector(2 downto 0);
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constant parameter0 : in std_logic_vector(4 downto 0);
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constant parameter1 : in std_logic_vector(4 downto 0);
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constant stype1 : in std_logic_vector(2 downto 0);
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constant cmd : in std_logic_vector(2 downto 0))
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return std_logic_vector;
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-----------------------------------------------------------------------------
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-- Crc16 calculation function.
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-- CITT, polynom=0x1021.
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-----------------------------------------------------------------------------
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function Crc16(constant data : in std_logic_vector(15 downto 0);
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constant crc : in std_logic_vector(15 downto 0))
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return std_logic_vector;
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---------------------------------------------------------------------------
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-- Create a randomly initialized data array.
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---------------------------------------------------------------------------
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procedure CreateRandomPayload(
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variable payload : out HalfwordArray(0 to 132);
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variable seed1 : inout positive;
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variable seed2 : inout positive);
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procedure CreateRandomPayload(
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variable payload : out DoublewordArray(0 to 31);
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variable seed1 : inout positive;
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variable seed2 : inout positive);
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---------------------------------------------------------------------------
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-- Create a generic RapidIO frame.
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---------------------------------------------------------------------------
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function RioFrameCreate(
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constant ackId : in std_logic_vector(4 downto 0);
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constant vc : in std_logic;
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constant crf : in std_logic;
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constant prio : in std_logic_vector(1 downto 0);
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constant tt : in std_logic_vector(1 downto 0);
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constant ftype : in std_logic_vector(3 downto 0);
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constant sourceId : in std_logic_vector(15 downto 0);
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constant destId : in std_logic_vector(15 downto 0);
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constant payload : in RioPayload)
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return RioFrame;
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---------------------------------------------------------------------------
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-- Create a NWRITE RapidIO frame.
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---------------------------------------------------------------------------
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function RioNwrite(
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constant wrsize : in std_logic_vector(3 downto 0);
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constant tid : in std_logic_vector(7 downto 0);
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constant address : in std_logic_vector(28 downto 0);
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constant wdptr : in std_logic;
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constant xamsbs : in std_logic_vector(1 downto 0);
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constant dataLength : in natural range 1 to 32;
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constant data : in DoublewordArray(0 to 31))
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return RioPayload;
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---------------------------------------------------------------------------
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-- Create a NREAD RapidIO frame.
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---------------------------------------------------------------------------
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function RioNread(
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constant rdsize : in std_logic_vector(3 downto 0);
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constant tid : in std_logic_vector(7 downto 0);
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constant address : in std_logic_vector(28 downto 0);
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constant wdptr : in std_logic;
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constant xamsbs : in std_logic_vector(1 downto 0))
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return RioPayload;
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---------------------------------------------------------------------------
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-- Create a RESPONSE RapidIO frame.
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---------------------------------------------------------------------------
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function RioResponse(
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constant status : in std_logic_vector(3 downto 0);
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constant tid : in std_logic_vector(7 downto 0);
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constant dataLength : in natural range 0 to 32;
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constant data : in DoublewordArray(0 to 31))
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return RioPayload;
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---------------------------------------------------------------------------
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-- Create a Maintenance RapidIO frame.
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---------------------------------------------------------------------------
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function RioMaintenance(
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constant transaction : in std_logic_vector(3 downto 0);
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constant size : in std_logic_vector(3 downto 0);
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constant tid : in std_logic_vector(7 downto 0);
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constant hopCount : in std_logic_vector(7 downto 0);
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constant configOffset : in std_logic_vector(20 downto 0);
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constant wdptr : in std_logic;
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constant dataLength : in natural range 0 to 8;
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constant data : in DoublewordArray(0 to 7))
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return RioPayload;
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-----------------------------------------------------------------------------
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-- Function to convert a std_logic_vector to a string.
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-----------------------------------------------------------------------------
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function byteToString(constant byte : std_logic_vector(7 downto 0))
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return string;
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---------------------------------------------------------------------------
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-- Procedure to print to report file and output
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---------------------------------------------------------------------------
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procedure PrintR( constant str : string );
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---------------------------------------------------------------------------
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-- Procedure to print to spec file
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---------------------------------------------------------------------------
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procedure PrintS( constant str : string );
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---------------------------------------------------------------------------
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-- Procedure to Assert Expression
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---------------------------------------------------------------------------
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procedure AssertE( constant exp: boolean; constant str : string );
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---------------------------------------------------------------------------
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-- Procedure to Print Error
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---------------------------------------------------------------------------
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procedure PrintE( constant str : string );
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---------------------------------------------------------------------------
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-- Procedure to end a test.
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---------------------------------------------------------------------------
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procedure TestEnd;
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end package;
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-------------------------------------------------------------------------------
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| 306 |
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-- RioCommon package body description.
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| 307 |
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-------------------------------------------------------------------------------
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package body rio_common is
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-----------------------------------------------------------------------------
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| 310 |
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-- Crc5 calculation function.
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| 311 |
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-- ITU, polynom=0x15.
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-----------------------------------------------------------------------------
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function Crc5(constant data : in std_logic_vector(18 downto 0);
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constant crc : in std_logic_vector(4 downto 0))
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return std_logic_vector is
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type crcTableType is array (0 to 31) of std_logic_vector(7 downto 0);
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constant crcTable : crcTableType := (
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| 318 |
|
|
x"00", x"15", x"1f", x"0a", x"0b", x"1e", x"14", x"01",
|
| 319 |
|
|
x"16", x"03", x"09", x"1c", x"1d", x"08", x"02", x"17",
|
| 320 |
|
|
x"19", x"0c", x"06", x"13", x"12", x"07", x"0d", x"18",
|
| 321 |
|
|
x"0f", x"1a", x"10", x"05", x"04", x"11", x"1b", x"0e" );
|
| 322 |
|
|
variable index : natural range 0 to 31;
|
| 323 |
|
|
variable result : std_logic_vector(4 downto 0);
|
| 324 |
|
|
begin
|
| 325 |
|
|
result := crc;
|
| 326 |
|
|
index := to_integer(unsigned(data(18 downto 14) xor result));
|
| 327 |
|
|
result := crcTable(index)(4 downto 0);
|
| 328 |
|
|
index := to_integer(unsigned(data(13 downto 9) xor result));
|
| 329 |
|
|
result := crcTable(index)(4 downto 0);
|
| 330 |
|
|
index := to_integer(unsigned(data(8 downto 4) xor result));
|
| 331 |
|
|
result := crcTable(index)(4 downto 0);
|
| 332 |
|
|
index := to_integer(unsigned((data(3 downto 0) & '0') xor result));
|
| 333 |
|
|
return crcTable(index)(4 downto 0);
|
| 334 |
|
|
end Crc5;
|
| 335 |
|
|
|
| 336 |
|
|
---------------------------------------------------------------------------
|
| 337 |
|
|
-- Create a RapidIO physical layer control symbol.
|
| 338 |
|
|
---------------------------------------------------------------------------
|
| 339 |
|
|
function RioControlSymbolCreate(
|
| 340 |
|
|
constant stype0 : in std_logic_vector(2 downto 0);
|
| 341 |
|
|
constant parameter0 : in std_logic_vector(4 downto 0);
|
| 342 |
|
|
constant parameter1 : in std_logic_vector(4 downto 0);
|
| 343 |
|
|
constant stype1 : in std_logic_vector(2 downto 0);
|
| 344 |
|
|
constant cmd : in std_logic_vector(2 downto 0))
|
| 345 |
|
|
return std_logic_vector is
|
| 346 |
|
|
variable returnValue : std_logic_vector(31 downto 0);
|
| 347 |
|
|
variable symbolData : std_logic_vector(18 downto 0);
|
| 348 |
|
|
begin
|
| 349 |
|
|
symbolData(18 downto 16) := stype0;
|
| 350 |
|
|
symbolData(15 downto 11) := parameter0;
|
| 351 |
|
|
symbolData(10 downto 6) := parameter1;
|
| 352 |
|
|
symbolData(5 downto 3) := stype1;
|
| 353 |
|
|
symbolData(2 downto 0) := cmd;
|
| 354 |
|
|
|
| 355 |
|
|
returnValue(31 downto 13) := symbolData;
|
| 356 |
|
|
returnValue(12 downto 8) := Crc5(symbolData, "11111");
|
| 357 |
|
|
returnValue(7 downto 0) := x"00";
|
| 358 |
|
|
|
| 359 |
|
|
return returnValue;
|
| 360 |
|
|
end function;
|
| 361 |
|
|
|
| 362 |
|
|
-----------------------------------------------------------------------------
|
| 363 |
|
|
-- Crc16 calculation function.
|
| 364 |
|
|
-- CITT, polynom=0x1021.
|
| 365 |
|
|
-----------------------------------------------------------------------------
|
| 366 |
|
|
function Crc16(constant data : in std_logic_vector(15 downto 0);
|
| 367 |
|
|
constant crc : in std_logic_vector(15 downto 0))
|
| 368 |
|
|
return std_logic_vector is
|
| 369 |
|
|
type crcTableType is array (0 to 255) of std_logic_vector(15 downto 0);
|
| 370 |
|
|
constant crcTable : crcTableType := (
|
| 371 |
|
|
x"0000", x"1021", x"2042", x"3063", x"4084", x"50a5", x"60c6", x"70e7",
|
| 372 |
|
|
x"8108", x"9129", x"a14a", x"b16b", x"c18c", x"d1ad", x"e1ce", x"f1ef",
|
| 373 |
|
|
x"1231", x"0210", x"3273", x"2252", x"52b5", x"4294", x"72f7", x"62d6",
|
| 374 |
|
|
x"9339", x"8318", x"b37b", x"a35a", x"d3bd", x"c39c", x"f3ff", x"e3de",
|
| 375 |
|
|
x"2462", x"3443", x"0420", x"1401", x"64e6", x"74c7", x"44a4", x"5485",
|
| 376 |
|
|
x"a56a", x"b54b", x"8528", x"9509", x"e5ee", x"f5cf", x"c5ac", x"d58d",
|
| 377 |
|
|
x"3653", x"2672", x"1611", x"0630", x"76d7", x"66f6", x"5695", x"46b4",
|
| 378 |
|
|
x"b75b", x"a77a", x"9719", x"8738", x"f7df", x"e7fe", x"d79d", x"c7bc",
|
| 379 |
|
|
x"48c4", x"58e5", x"6886", x"78a7", x"0840", x"1861", x"2802", x"3823",
|
| 380 |
|
|
x"c9cc", x"d9ed", x"e98e", x"f9af", x"8948", x"9969", x"a90a", x"b92b",
|
| 381 |
|
|
x"5af5", x"4ad4", x"7ab7", x"6a96", x"1a71", x"0a50", x"3a33", x"2a12",
|
| 382 |
|
|
x"dbfd", x"cbdc", x"fbbf", x"eb9e", x"9b79", x"8b58", x"bb3b", x"ab1a",
|
| 383 |
|
|
x"6ca6", x"7c87", x"4ce4", x"5cc5", x"2c22", x"3c03", x"0c60", x"1c41",
|
| 384 |
|
|
x"edae", x"fd8f", x"cdec", x"ddcd", x"ad2a", x"bd0b", x"8d68", x"9d49",
|
| 385 |
|
|
x"7e97", x"6eb6", x"5ed5", x"4ef4", x"3e13", x"2e32", x"1e51", x"0e70",
|
| 386 |
|
|
x"ff9f", x"efbe", x"dfdd", x"cffc", x"bf1b", x"af3a", x"9f59", x"8f78",
|
| 387 |
|
|
x"9188", x"81a9", x"b1ca", x"a1eb", x"d10c", x"c12d", x"f14e", x"e16f",
|
| 388 |
|
|
x"1080", x"00a1", x"30c2", x"20e3", x"5004", x"4025", x"7046", x"6067",
|
| 389 |
|
|
x"83b9", x"9398", x"a3fb", x"b3da", x"c33d", x"d31c", x"e37f", x"f35e",
|
| 390 |
|
|
x"02b1", x"1290", x"22f3", x"32d2", x"4235", x"5214", x"6277", x"7256",
|
| 391 |
|
|
x"b5ea", x"a5cb", x"95a8", x"8589", x"f56e", x"e54f", x"d52c", x"c50d",
|
| 392 |
|
|
x"34e2", x"24c3", x"14a0", x"0481", x"7466", x"6447", x"5424", x"4405",
|
| 393 |
|
|
x"a7db", x"b7fa", x"8799", x"97b8", x"e75f", x"f77e", x"c71d", x"d73c",
|
| 394 |
|
|
x"26d3", x"36f2", x"0691", x"16b0", x"6657", x"7676", x"4615", x"5634",
|
| 395 |
|
|
x"d94c", x"c96d", x"f90e", x"e92f", x"99c8", x"89e9", x"b98a", x"a9ab",
|
| 396 |
|
|
x"5844", x"4865", x"7806", x"6827", x"18c0", x"08e1", x"3882", x"28a3",
|
| 397 |
|
|
x"cb7d", x"db5c", x"eb3f", x"fb1e", x"8bf9", x"9bd8", x"abbb", x"bb9a",
|
| 398 |
|
|
x"4a75", x"5a54", x"6a37", x"7a16", x"0af1", x"1ad0", x"2ab3", x"3a92",
|
| 399 |
|
|
x"fd2e", x"ed0f", x"dd6c", x"cd4d", x"bdaa", x"ad8b", x"9de8", x"8dc9",
|
| 400 |
|
|
x"7c26", x"6c07", x"5c64", x"4c45", x"3ca2", x"2c83", x"1ce0", x"0cc1",
|
| 401 |
|
|
x"ef1f", x"ff3e", x"cf5d", x"df7c", x"af9b", x"bfba", x"8fd9", x"9ff8",
|
| 402 |
|
|
x"6e17", x"7e36", x"4e55", x"5e74", x"2e93", x"3eb2", x"0ed1", x"1ef0" );
|
| 403 |
|
|
variable index : natural range 0 to 255;
|
| 404 |
|
|
variable result : std_logic_vector(15 downto 0);
|
| 405 |
|
|
begin
|
| 406 |
|
|
result := crc;
|
| 407 |
|
|
index := to_integer(unsigned(data(15 downto 8) xor result(15 downto 8)));
|
| 408 |
|
|
result := crcTable(index) xor (result(7 downto 0) & x"00");
|
| 409 |
|
|
index := to_integer(unsigned(data(7 downto 0) xor result(15 downto 8)));
|
| 410 |
|
|
result := crcTable(index) xor (result(7 downto 0) & x"00");
|
| 411 |
|
|
return result;
|
| 412 |
|
|
end Crc16;
|
| 413 |
|
|
|
| 414 |
|
|
---------------------------------------------------------------------------
|
| 415 |
|
|
-- Create a randomly initialized data array.
|
| 416 |
|
|
---------------------------------------------------------------------------
|
| 417 |
|
|
procedure CreateRandomPayload(
|
| 418 |
|
|
variable payload : out HalfwordArray(0 to 132);
|
| 419 |
|
|
variable seed1 : inout positive;
|
| 420 |
|
|
variable seed2 : inout positive) is
|
| 421 |
|
|
variable rand: real;
|
| 422 |
|
|
variable int_rand: integer;
|
| 423 |
|
|
variable stim: std_logic_vector(7 downto 0);
|
| 424 |
|
|
begin
|
| 425 |
|
|
for i in payload'range loop
|
| 426 |
|
|
uniform(seed1, seed2, rand);
|
| 427 |
|
|
int_rand := integer(trunc(rand*256.0));
|
| 428 |
|
|
payload(i)(7 downto 0) := std_logic_vector(to_unsigned(int_rand, 8));
|
| 429 |
|
|
uniform(seed1, seed2, rand);
|
| 430 |
|
|
int_rand := integer(trunc(rand*256.0));
|
| 431 |
|
|
payload(i)(15 downto 8) := std_logic_vector(to_unsigned(int_rand, 8));
|
| 432 |
|
|
end loop;
|
| 433 |
|
|
end procedure;
|
| 434 |
|
|
|
| 435 |
|
|
procedure CreateRandomPayload(
|
| 436 |
|
|
variable payload : out DoublewordArray(0 to 31);
|
| 437 |
|
|
variable seed1 : inout positive;
|
| 438 |
|
|
variable seed2 : inout positive) is
|
| 439 |
|
|
variable rand: real;
|
| 440 |
|
|
variable int_rand: integer;
|
| 441 |
|
|
variable stim: std_logic_vector(7 downto 0);
|
| 442 |
|
|
begin
|
| 443 |
|
|
for i in payload'range loop
|
| 444 |
|
|
uniform(seed1, seed2, rand);
|
| 445 |
|
|
int_rand := integer(trunc(rand*256.0));
|
| 446 |
|
|
payload(i)(7 downto 0) := std_logic_vector(to_unsigned(int_rand, 8));
|
| 447 |
|
|
uniform(seed1, seed2, rand);
|
| 448 |
|
|
int_rand := integer(trunc(rand*256.0));
|
| 449 |
|
|
payload(i)(15 downto 8) := std_logic_vector(to_unsigned(int_rand, 8));
|
| 450 |
|
|
uniform(seed1, seed2, rand);
|
| 451 |
|
|
int_rand := integer(trunc(rand*256.0));
|
| 452 |
|
|
payload(i)(23 downto 16) := std_logic_vector(to_unsigned(int_rand, 8));
|
| 453 |
|
|
uniform(seed1, seed2, rand);
|
| 454 |
|
|
int_rand := integer(trunc(rand*256.0));
|
| 455 |
|
|
payload(i)(31 downto 24) := std_logic_vector(to_unsigned(int_rand, 8));
|
| 456 |
|
|
uniform(seed1, seed2, rand);
|
| 457 |
|
|
int_rand := integer(trunc(rand*256.0));
|
| 458 |
|
|
payload(i)(39 downto 32) := std_logic_vector(to_unsigned(int_rand, 8));
|
| 459 |
|
|
uniform(seed1, seed2, rand);
|
| 460 |
|
|
int_rand := integer(trunc(rand*256.0));
|
| 461 |
|
|
payload(i)(47 downto 40) := std_logic_vector(to_unsigned(int_rand, 8));
|
| 462 |
|
|
uniform(seed1, seed2, rand);
|
| 463 |
|
|
int_rand := integer(trunc(rand*256.0));
|
| 464 |
|
|
payload(i)(55 downto 48) := std_logic_vector(to_unsigned(int_rand, 8));
|
| 465 |
|
|
uniform(seed1, seed2, rand);
|
| 466 |
|
|
int_rand := integer(trunc(rand*256.0));
|
| 467 |
|
|
payload(i)(63 downto 56) := std_logic_vector(to_unsigned(int_rand, 8));
|
| 468 |
|
|
end loop;
|
| 469 |
|
|
end procedure;
|
| 470 |
|
|
---------------------------------------------------------------------------
|
| 471 |
|
|
-- Create a generic RapidIO frame.
|
| 472 |
|
|
---------------------------------------------------------------------------
|
| 473 |
|
|
function RioFrameCreate(
|
| 474 |
|
|
constant ackId : in std_logic_vector(4 downto 0);
|
| 475 |
|
|
constant vc : in std_logic;
|
| 476 |
|
|
constant crf : in std_logic;
|
| 477 |
|
|
constant prio : in std_logic_vector(1 downto 0);
|
| 478 |
|
|
constant tt : in std_logic_vector(1 downto 0);
|
| 479 |
|
|
constant ftype : in std_logic_vector(3 downto 0);
|
| 480 |
|
|
constant sourceId : in std_logic_vector(15 downto 0);
|
| 481 |
|
|
constant destId : in std_logic_vector(15 downto 0);
|
| 482 |
|
|
constant payload : in RioPayload) return RioFrame is
|
| 483 |
|
|
variable frame : RioFrame;
|
| 484 |
|
|
variable result : HalfwordArray(0 to 137);
|
| 485 |
|
|
variable crc : std_logic_vector(15 downto 0) := x"ffff";
|
| 486 |
|
|
begin
|
| 487 |
|
|
-- Add the header and addresses.
|
| 488 |
|
|
result(0) := ackId & "0" & vc & crf & prio & tt & ftype;
|
| 489 |
|
|
result(1) := destId;
|
| 490 |
|
|
result(2) := sourceId;
|
| 491 |
|
|
|
| 492 |
|
|
-- Update the calculated CRC with the header contents.
|
| 493 |
|
|
crc := Crc16("00000" & result(0)(10 downto 0), crc);
|
| 494 |
|
|
crc := Crc16(result(1), crc);
|
| 495 |
|
|
crc := Crc16(result(2), crc);
|
| 496 |
|
|
|
| 497 |
|
|
-- Check if a single CRC should be added or two.
|
| 498 |
|
|
if (payload.length <= 37) then
|
| 499 |
|
|
-- Single CRC.
|
| 500 |
|
|
for i in 0 to payload.length-1 loop
|
| 501 |
|
|
result(i+3) := payload.data(i);
|
| 502 |
|
|
crc := Crc16(payload.data(i), crc);
|
| 503 |
|
|
end loop;
|
| 504 |
|
|
result(payload.length+3) := crc;
|
| 505 |
|
|
|
| 506 |
|
|
-- Check if paddning is needed to make the payload even 32-bit.
|
| 507 |
|
|
if ((payload.length mod 2) = 1) then
|
| 508 |
|
|
result(payload.length+4) := x"0000";
|
| 509 |
|
|
frame.length := (payload.length+5) / 2;
|
| 510 |
|
|
else
|
| 511 |
|
|
frame.length := (payload.length+4) / 2;
|
| 512 |
|
|
end if;
|
| 513 |
|
|
else
|
| 514 |
|
|
-- Double CRC.
|
| 515 |
|
|
for i in 0 to 36 loop
|
| 516 |
|
|
result(i+3) := payload.data(i);
|
| 517 |
|
|
crc := Crc16(payload.data(i), crc);
|
| 518 |
|
|
end loop;
|
| 519 |
|
|
|
| 520 |
|
|
-- Add in-the-middle crc.
|
| 521 |
|
|
result(40) := crc;
|
| 522 |
|
|
crc := Crc16(crc, crc);
|
| 523 |
|
|
|
| 524 |
|
|
for i in 37 to payload.length-1 loop
|
| 525 |
|
|
result(i+4) := payload.data(i);
|
| 526 |
|
|
crc := Crc16(payload.data(i), crc);
|
| 527 |
|
|
end loop;
|
| 528 |
|
|
result(payload.length+4) := crc;
|
| 529 |
|
|
|
| 530 |
|
|
-- Check if paddning is needed to make the payload even 32-bit.
|
| 531 |
|
|
if ((payload.length mod 2) = 0) then
|
| 532 |
|
|
result(payload.length+5) := x"0000";
|
| 533 |
|
|
frame.length := (payload.length+6) / 2;
|
| 534 |
|
|
else
|
| 535 |
|
|
frame.length := (payload.length+5) / 2;
|
| 536 |
|
|
end if;
|
| 537 |
|
|
end if;
|
| 538 |
|
|
|
| 539 |
|
|
-- Update the result length.
|
| 540 |
|
|
for i in 0 to frame.length-1 loop
|
| 541 |
|
|
frame.payload(i) := result(2*i) & result(2*i+1);
|
| 542 |
|
|
end loop;
|
| 543 |
|
|
|
| 544 |
|
|
return frame;
|
| 545 |
|
|
end function;
|
| 546 |
|
|
|
| 547 |
|
|
-----------------------------------------------------------------------------
|
| 548 |
|
|
--
|
| 549 |
|
|
-----------------------------------------------------------------------------
|
| 550 |
|
|
function RioNwrite(
|
| 551 |
|
|
constant wrsize : in std_logic_vector(3 downto 0);
|
| 552 |
|
|
constant tid : in std_logic_vector(7 downto 0);
|
| 553 |
|
|
constant address : in std_logic_vector(28 downto 0);
|
| 554 |
|
|
constant wdptr : in std_logic;
|
| 555 |
|
|
constant xamsbs : in std_logic_vector(1 downto 0);
|
| 556 |
|
|
constant dataLength : in natural range 1 to 32;
|
| 557 |
|
|
constant data : in DoublewordArray(0 to 31))
|
| 558 |
|
|
return RioPayload is
|
| 559 |
|
|
variable payload : RioPayload;
|
| 560 |
|
|
begin
|
| 561 |
|
|
payload.data(0)(15 downto 12) := "0100";
|
| 562 |
|
|
payload.data(0)(11 downto 8) := wrsize;
|
| 563 |
|
|
payload.data(0)(7 downto 0) := tid;
|
| 564 |
|
|
|
| 565 |
|
|
payload.data(1) := address(28 downto 13);
|
| 566 |
|
|
|
| 567 |
|
|
payload.data(2)(15 downto 3) := address(12 downto 0);
|
| 568 |
|
|
payload.data(2)(2) := wdptr;
|
| 569 |
|
|
payload.data(2)(1 downto 0) := xamsbs;
|
| 570 |
|
|
|
| 571 |
|
|
for i in 0 to dataLength-1 loop
|
| 572 |
|
|
payload.data(3+4*i) := data(i)(63 downto 48);
|
| 573 |
|
|
payload.data(4+4*i) := data(i)(47 downto 32);
|
| 574 |
|
|
payload.data(5+4*i) := data(i)(31 downto 16);
|
| 575 |
|
|
payload.data(6+4*i) := data(i)(15 downto 0);
|
| 576 |
|
|
end loop;
|
| 577 |
|
|
|
| 578 |
|
|
payload.length := 3 + 4*dataLength;
|
| 579 |
|
|
|
| 580 |
|
|
return payload;
|
| 581 |
|
|
end function;
|
| 582 |
|
|
|
| 583 |
|
|
-----------------------------------------------------------------------------
|
| 584 |
|
|
--
|
| 585 |
|
|
-----------------------------------------------------------------------------
|
| 586 |
|
|
function RioNread(
|
| 587 |
|
|
constant rdsize : in std_logic_vector(3 downto 0);
|
| 588 |
|
|
constant tid : in std_logic_vector(7 downto 0);
|
| 589 |
|
|
constant address : in std_logic_vector(28 downto 0);
|
| 590 |
|
|
constant wdptr : in std_logic;
|
| 591 |
|
|
constant xamsbs : in std_logic_vector(1 downto 0))
|
| 592 |
|
|
return RioPayload is
|
| 593 |
|
|
variable payload : RioPayload;
|
| 594 |
|
|
begin
|
| 595 |
|
|
payload.data(0)(15 downto 12) := "0100";
|
| 596 |
|
|
payload.data(0)(11 downto 8) := rdsize;
|
| 597 |
|
|
payload.data(0)(7 downto 0) := tid;
|
| 598 |
|
|
|
| 599 |
|
|
payload.data(1) := address(28 downto 13);
|
| 600 |
|
|
|
| 601 |
|
|
payload.data(2)(15 downto 3) := address(12 downto 0);
|
| 602 |
|
|
payload.data(2)(2) := wdptr;
|
| 603 |
|
|
payload.data(2)(1 downto 0) := xamsbs;
|
| 604 |
|
|
|
| 605 |
|
|
payload.length := 3;
|
| 606 |
|
|
|
| 607 |
|
|
return payload;
|
| 608 |
|
|
end function;
|
| 609 |
|
|
|
| 610 |
|
|
---------------------------------------------------------------------------
|
| 611 |
|
|
-- Create a RESPONSE RapidIO frame.
|
| 612 |
|
|
---------------------------------------------------------------------------
|
| 613 |
|
|
function RioResponse(
|
| 614 |
|
|
constant status : in std_logic_vector(3 downto 0);
|
| 615 |
|
|
constant tid : in std_logic_vector(7 downto 0);
|
| 616 |
|
|
constant dataLength : in natural range 0 to 32;
|
| 617 |
|
|
constant data : in DoublewordArray(0 to 31))
|
| 618 |
|
|
return RioPayload is
|
| 619 |
|
|
variable payload : RioPayload;
|
| 620 |
|
|
begin
|
| 621 |
|
|
payload.data(0)(11 downto 8) := status;
|
| 622 |
|
|
payload.data(0)(7 downto 0) := tid;
|
| 623 |
|
|
|
| 624 |
|
|
if (dataLength = 0) then
|
| 625 |
|
|
payload.data(0)(15 downto 12) := "0000";
|
| 626 |
|
|
payload.length := 1;
|
| 627 |
|
|
else
|
| 628 |
|
|
payload.data(0)(15 downto 12) := "1000";
|
| 629 |
|
|
|
| 630 |
|
|
for i in 0 to dataLength-1 loop
|
| 631 |
|
|
payload.data(1+4*i) := data(i)(63 downto 48);
|
| 632 |
|
|
payload.data(2+4*i) := data(i)(47 downto 32);
|
| 633 |
|
|
payload.data(3+4*i) := data(i)(31 downto 16);
|
| 634 |
|
|
payload.data(4+4*i) := data(i)(15 downto 0);
|
| 635 |
|
|
end loop;
|
| 636 |
|
|
|
| 637 |
|
|
payload.length := 1 + 4*dataLength;
|
| 638 |
|
|
end if;
|
| 639 |
|
|
|
| 640 |
|
|
return payload;
|
| 641 |
|
|
end function;
|
| 642 |
|
|
|
| 643 |
|
|
---------------------------------------------------------------------------
|
| 644 |
|
|
-- Create a Maintenance RapidIO frame.
|
| 645 |
|
|
---------------------------------------------------------------------------
|
| 646 |
|
|
function RioMaintenance(
|
| 647 |
|
|
constant transaction : in std_logic_vector(3 downto 0);
|
| 648 |
|
|
constant size : in std_logic_vector(3 downto 0);
|
| 649 |
|
|
constant tid : in std_logic_vector(7 downto 0);
|
| 650 |
|
|
constant hopCount : in std_logic_vector(7 downto 0);
|
| 651 |
|
|
constant configOffset : in std_logic_vector(20 downto 0);
|
| 652 |
|
|
constant wdptr : in std_logic;
|
| 653 |
|
|
constant dataLength : in natural range 0 to 8;
|
| 654 |
|
|
constant data : in DoublewordArray(0 to 7))
|
| 655 |
|
|
return RioPayload is
|
| 656 |
|
|
variable payload : RioPayload;
|
| 657 |
|
|
begin
|
| 658 |
|
|
payload.data(0)(15 downto 12) := transaction;
|
| 659 |
|
|
payload.data(0)(11 downto 8) := size;
|
| 660 |
|
|
payload.data(0)(7 downto 0) := tid;
|
| 661 |
|
|
|
| 662 |
|
|
payload.data(1)(15 downto 8) := hopCount;
|
| 663 |
|
|
payload.data(1)(7 downto 0) := configOffset(20 downto 13);
|
| 664 |
|
|
|
| 665 |
|
|
payload.data(2)(15 downto 3) := configOffset(12 downto 0);
|
| 666 |
|
|
payload.data(2)(2) := wdptr;
|
| 667 |
|
|
payload.data(2)(1 downto 0) := "00";
|
| 668 |
|
|
|
| 669 |
|
|
if (dataLength = 0) then
|
| 670 |
|
|
payload.length := 3;
|
| 671 |
|
|
else
|
| 672 |
|
|
for i in 0 to dataLength-1 loop
|
| 673 |
|
|
payload.data(3+4*i) := data(i)(63 downto 48);
|
| 674 |
|
|
payload.data(4+4*i) := data(i)(47 downto 32);
|
| 675 |
|
|
payload.data(5+4*i) := data(i)(31 downto 16);
|
| 676 |
|
|
payload.data(6+4*i) := data(i)(15 downto 0);
|
| 677 |
|
|
end loop;
|
| 678 |
|
|
|
| 679 |
|
|
payload.length := 3 + 4*dataLength;
|
| 680 |
|
|
end if;
|
| 681 |
|
|
|
| 682 |
|
|
return payload;
|
| 683 |
|
|
end function;
|
| 684 |
|
|
|
| 685 |
|
|
-----------------------------------------------------------------------------
|
| 686 |
|
|
-- Function to convert a std_logic_vector to a string.
|
| 687 |
|
|
-----------------------------------------------------------------------------
|
| 688 |
|
|
function byteToString(constant byte : std_logic_vector(7 downto 0))
|
| 689 |
|
|
return string is
|
| 690 |
|
|
constant table : string(1 to 16) := "0123456789abcdef";
|
| 691 |
|
|
variable returnValue : string(1 to 2);
|
| 692 |
|
|
begin
|
| 693 |
|
|
returnValue(1) := table(to_integer(unsigned(byte(7 downto 4))) + 1);
|
| 694 |
|
|
returnValue(2) := table(to_integer(unsigned(byte(3 downto 0))) + 1);
|
| 695 |
|
|
return returnValue;
|
| 696 |
|
|
end function;
|
| 697 |
|
|
|
| 698 |
|
|
---------------------------------------------------------------------------
|
| 699 |
|
|
-- Procedure to print test report
|
| 700 |
|
|
---------------------------------------------------------------------------
|
| 701 |
|
|
procedure PrintR( constant str : string ) is
|
| 702 |
|
|
file reportFile : text;
|
| 703 |
|
|
variable reportLine, outputLine : line;
|
| 704 |
|
|
variable fStatus: FILE_OPEN_STATUS;
|
| 705 |
|
|
begin
|
| 706 |
|
|
--Write report note to wave/transcript window
|
| 707 |
|
|
report str severity NOTE;
|
| 708 |
|
|
end PrintR;
|
| 709 |
|
|
|
| 710 |
|
|
---------------------------------------------------------------------------
|
| 711 |
|
|
-- Procedure to print test spec
|
| 712 |
|
|
---------------------------------------------------------------------------
|
| 713 |
|
|
procedure PrintS( constant str : string ) is
|
| 714 |
|
|
file specFile : text;
|
| 715 |
|
|
variable specLine, outputLine : line;
|
| 716 |
|
|
variable fStatus: FILE_OPEN_STATUS;
|
| 717 |
|
|
begin
|
| 718 |
|
|
--Write to spec file
|
| 719 |
|
|
file_open(fStatus, specFile, "testspec.txt", append_mode);
|
| 720 |
|
|
write(specLine, string'(str));
|
| 721 |
|
|
writeline (specFile, specLine);
|
| 722 |
|
|
file_close(specFile);
|
| 723 |
|
|
end PrintS;
|
| 724 |
|
|
|
| 725 |
|
|
---------------------------------------------------------------------------
|
| 726 |
|
|
-- Procedure to Assert Expression
|
| 727 |
|
|
---------------------------------------------------------------------------
|
| 728 |
|
|
procedure AssertE( constant exp: boolean; constant str : string ) is
|
| 729 |
|
|
file reportFile : text;
|
| 730 |
|
|
variable reportLine, outputLine : line;
|
| 731 |
|
|
variable fStatus: FILE_OPEN_STATUS;
|
| 732 |
|
|
begin
|
| 733 |
|
|
if (not exp) then
|
| 734 |
|
|
--Write to STD_OUTPUT
|
| 735 |
|
|
report(str) severity error;
|
| 736 |
|
|
else
|
| 737 |
|
|
PrintR("Status: Passed");
|
| 738 |
|
|
PrintS("Status: Passed");
|
| 739 |
|
|
end if;
|
| 740 |
|
|
end AssertE;
|
| 741 |
|
|
|
| 742 |
|
|
---------------------------------------------------------------------------
|
| 743 |
|
|
-- Procedure to Print Error
|
| 744 |
|
|
---------------------------------------------------------------------------
|
| 745 |
|
|
procedure PrintE( constant str : string ) is
|
| 746 |
|
|
file reportFile : text;
|
| 747 |
|
|
variable reportLine, outputLine : line;
|
| 748 |
|
|
variable fStatus: FILE_OPEN_STATUS;
|
| 749 |
|
|
begin
|
| 750 |
|
|
--Write to STD_OUTPUT
|
| 751 |
|
|
report str severity error;
|
| 752 |
|
|
end PrintE;
|
| 753 |
|
|
|
| 754 |
|
|
---------------------------------------------------------------------------
|
| 755 |
|
|
-- Procedure to end a test.
|
| 756 |
|
|
---------------------------------------------------------------------------
|
| 757 |
|
|
procedure TestEnd is
|
| 758 |
|
|
begin
|
| 759 |
|
|
assert false report "Test complete." severity failure;
|
| 760 |
|
|
wait;
|
| 761 |
|
|
end TestEnd;
|
| 762 |
|
|
|
| 763 |
|
|
end rio_common;
|
| 764 |
|
|
|
| 765 |
|
|
|
| 766 |
|
|
|
| 767 |
|
|
-------------------------------------------------------------------------------
|
| 768 |
|
|
-- Crc16CITT
|
| 769 |
|
|
-- A CRC-16 calculator following the implementation proposed in the 2.2
|
| 770 |
|
|
-- standard.
|
| 771 |
|
|
-------------------------------------------------------------------------------
|
| 772 |
|
|
library ieee;
|
| 773 |
|
|
use ieee.std_logic_1164.all;
|
| 774 |
|
|
|
| 775 |
|
|
|
| 776 |
|
|
-------------------------------------------------------------------------------
|
| 777 |
|
|
-- Entity for Crc16CITT.
|
| 778 |
|
|
-------------------------------------------------------------------------------
|
| 779 |
|
|
entity Crc16CITT is
|
| 780 |
|
|
port(
|
| 781 |
|
|
d_i : in std_logic_vector(15 downto 0);
|
| 782 |
|
|
crc_i : in std_logic_vector(15 downto 0);
|
| 783 |
|
|
crc_o : out std_logic_vector(15 downto 0));
|
| 784 |
|
|
end entity;
|
| 785 |
|
|
|
| 786 |
|
|
|
| 787 |
|
|
-------------------------------------------------------------------------------
|
| 788 |
|
|
-- Architecture for Crc16CITT.
|
| 789 |
|
|
-------------------------------------------------------------------------------
|
| 790 |
|
|
architecture Crc16Impl of Crc16CITT is
|
| 791 |
|
|
signal d : std_logic_vector(0 to 15);
|
| 792 |
|
|
signal c : std_logic_vector(0 to 15);
|
| 793 |
|
|
signal e : std_logic_vector(0 to 15);
|
| 794 |
|
|
signal cc : std_logic_vector(0 to 15);
|
| 795 |
|
|
begin
|
| 796 |
|
|
|
| 797 |
|
|
-- Reverse the bit vector indexes to make them the same as in the standard.
|
| 798 |
|
|
d(15) <= d_i(0); d(14) <= d_i(1); d(13) <= d_i(2); d(12) <= d_i(3);
|
| 799 |
|
|
d(11) <= d_i(4); d(10) <= d_i(5); d(9) <= d_i(6); d(8) <= d_i(7);
|
| 800 |
|
|
d(7) <= d_i(8); d(6) <= d_i(9); d(5) <= d_i(10); d(4) <= d_i(11);
|
| 801 |
|
|
d(3) <= d_i(12); d(2) <= d_i(13); d(1) <= d_i(14); d(0) <= d_i(15);
|
| 802 |
|
|
|
| 803 |
|
|
-- Reverse the bit vector indexes to make them the same as in the standard.
|
| 804 |
|
|
c(15) <= crc_i(0); c(14) <= crc_i(1); c(13) <= crc_i(2); c(12) <= crc_i(3);
|
| 805 |
|
|
c(11) <= crc_i(4); c(10) <= crc_i(5); c(9) <= crc_i(6); c(8) <= crc_i(7);
|
| 806 |
|
|
c(7) <= crc_i(8); c(6) <= crc_i(9); c(5) <= crc_i(10); c(4) <= crc_i(11);
|
| 807 |
|
|
c(3) <= crc_i(12); c(2) <= crc_i(13); c(1) <= crc_i(14); c(0) <= crc_i(15);
|
| 808 |
|
|
|
| 809 |
|
|
-- Calculate the resulting crc.
|
| 810 |
|
|
e <= c xor d;
|
| 811 |
|
|
cc(0) <= e(4) xor e(5) xor e(8) xor e(12);
|
| 812 |
|
|
cc(1) <= e(5) xor e(6) xor e(9) xor e(13);
|
| 813 |
|
|
cc(2) <= e(6) xor e(7) xor e(10) xor e(14);
|
| 814 |
|
|
cc(3) <= e(0) xor e(7) xor e(8) xor e(11) xor e(15);
|
| 815 |
|
|
cc(4) <= e(0) xor e(1) xor e(4) xor e(5) xor e(9);
|
| 816 |
|
|
cc(5) <= e(1) xor e(2) xor e(5) xor e(6) xor e(10);
|
| 817 |
|
|
cc(6) <= e(0) xor e(2) xor e(3) xor e(6) xor e(7) xor e(11);
|
| 818 |
|
|
cc(7) <= e(0) xor e(1) xor e(3) xor e(4) xor e(7) xor e(8) xor e(12);
|
| 819 |
|
|
cc(8) <= e(0) xor e(1) xor e(2) xor e(4) xor e(5) xor e(8) xor e(9) xor e(13);
|
| 820 |
|
|
cc(9) <= e(1) xor e(2) xor e(3) xor e(5) xor e(6) xor e(9) xor e(10) xor e(14);
|
| 821 |
|
|
cc(10) <= e(2) xor e(3) xor e(4) xor e(6) xor e(7) xor e(10) xor e(11) xor e(15);
|
| 822 |
|
|
cc(11) <= e(0) xor e(3) xor e(7) xor e(11);
|
| 823 |
|
|
cc(12) <= e(0) xor e(1) xor e(4) xor e(8) xor e(12);
|
| 824 |
|
|
cc(13) <= e(1) xor e(2) xor e(5) xor e(9) xor e(13);
|
| 825 |
|
|
cc(14) <= e(2) xor e(3) xor e(6) xor e(10) xor e(14);
|
| 826 |
|
|
cc(15) <= e(3) xor e(4) xor e(7) xor e(11) xor e(15);
|
| 827 |
|
|
|
| 828 |
|
|
-- Reverse the bit vector indexes to make them the same as in the standard.
|
| 829 |
|
|
crc_o(15) <= cc(0); crc_o(14) <= cc(1); crc_o(13) <= cc(2); crc_o(12) <= cc(3);
|
| 830 |
|
|
crc_o(11) <= cc(4); crc_o(10) <= cc(5); crc_o(9) <= cc(6); crc_o(8) <= cc(7);
|
| 831 |
|
|
crc_o(7) <= cc(8); crc_o(6) <= cc(9); crc_o(5) <= cc(10); crc_o(4) <= cc(11);
|
| 832 |
|
|
crc_o(3) <= cc(12); crc_o(2) <= cc(13); crc_o(1) <= cc(14); crc_o(0) <= cc(15);
|
| 833 |
|
|
|
| 834 |
|
|
end architecture;
|
| 835 |
|
|
|
| 836 |
|
|
|
| 837 |
|
|
|
| 838 |
|
|
-------------------------------------------------------------------------------
|
| 839 |
|
|
-- MemoryDualPort
|
| 840 |
|
|
-- Generic synchronous memory with one read/write port and one read port.
|
| 841 |
|
|
-------------------------------------------------------------------------------
|
| 842 |
|
|
|
| 843 |
|
|
library ieee;
|
| 844 |
|
|
use ieee.std_logic_1164.all;
|
| 845 |
|
|
use ieee.numeric_std.all;
|
| 846 |
|
|
|
| 847 |
|
|
|
| 848 |
|
|
-------------------------------------------------------------------------------
|
| 849 |
|
|
-- Entity for MemoryDualPort.
|
| 850 |
|
|
-------------------------------------------------------------------------------
|
| 851 |
|
|
entity MemoryDualPort is
|
| 852 |
|
|
generic(
|
| 853 |
|
|
ADDRESS_WIDTH : natural := 1;
|
| 854 |
|
|
DATA_WIDTH : natural := 1);
|
| 855 |
|
|
port(
|
| 856 |
|
|
clkA_i : in std_logic;
|
| 857 |
|
|
enableA_i : in std_logic;
|
| 858 |
|
|
writeEnableA_i : in std_logic;
|
| 859 |
|
|
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
| 860 |
|
|
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
| 861 |
|
|
dataA_o : out std_logic_vector(DATA_WIDTH-1 downto 0);
|
| 862 |
|
|
|
| 863 |
|
|
clkB_i : in std_logic;
|
| 864 |
|
|
enableB_i : in std_logic;
|
| 865 |
|
|
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
| 866 |
|
|
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
| 867 |
|
|
end entity;
|
| 868 |
|
|
|
| 869 |
|
|
|
| 870 |
|
|
-------------------------------------------------------------------------------
|
| 871 |
|
|
-- Architecture for MemoryDualPort.
|
| 872 |
|
|
-------------------------------------------------------------------------------
|
| 873 |
|
|
architecture MemoryDualPortImpl of MemoryDualPort is
|
| 874 |
|
|
type MemoryType is array (natural range <>) of
|
| 875 |
|
|
std_logic_vector(DATA_WIDTH-1 downto 0);
|
| 876 |
|
|
|
| 877 |
|
|
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
|
| 878 |
|
|
|
| 879 |
|
|
begin
|
| 880 |
|
|
process(clkA_i)
|
| 881 |
|
|
begin
|
| 882 |
|
|
if (clkA_i'event and clkA_i = '1') then
|
| 883 |
|
|
if (enableA_i = '1') then
|
| 884 |
|
|
if (writeEnableA_i = '1') then
|
| 885 |
|
|
memory(to_integer(unsigned(addressA_i))) <= dataA_i;
|
| 886 |
|
|
end if;
|
| 887 |
|
|
|
| 888 |
|
|
dataA_o <= memory(to_integer(unsigned(addressA_i)));
|
| 889 |
|
|
end if;
|
| 890 |
|
|
end if;
|
| 891 |
|
|
end process;
|
| 892 |
|
|
|
| 893 |
|
|
process(clkB_i)
|
| 894 |
|
|
begin
|
| 895 |
|
|
if (clkB_i'event and clkB_i = '1') then
|
| 896 |
|
|
if (enableB_i = '1') then
|
| 897 |
|
|
dataB_o <= memory(to_integer(unsigned(addressB_i)));
|
| 898 |
|
|
end if;
|
| 899 |
|
|
end if;
|
| 900 |
|
|
end process;
|
| 901 |
|
|
|
| 902 |
|
|
end architecture;
|
| 903 |
|
|
|
| 904 |
|
|
|
| 905 |
|
|
|
| 906 |
|
|
-------------------------------------------------------------------------------
|
| 907 |
|
|
-- MemorySimpleDualPort
|
| 908 |
|
|
-- Generic synchronous memory with one write port and one read port.
|
| 909 |
|
|
-------------------------------------------------------------------------------
|
| 910 |
|
|
|
| 911 |
|
|
library ieee;
|
| 912 |
|
|
use ieee.std_logic_1164.all;
|
| 913 |
|
|
use ieee.numeric_std.all;
|
| 914 |
|
|
|
| 915 |
|
|
|
| 916 |
|
|
-------------------------------------------------------------------------------
|
| 917 |
|
|
-- Entity for MemorySimpleDualPort.
|
| 918 |
|
|
-------------------------------------------------------------------------------
|
| 919 |
|
|
entity MemorySimpleDualPort is
|
| 920 |
|
|
generic(
|
| 921 |
|
|
ADDRESS_WIDTH : natural := 1;
|
| 922 |
|
|
DATA_WIDTH : natural := 1);
|
| 923 |
|
|
port(
|
| 924 |
|
|
clkA_i : in std_logic;
|
| 925 |
|
|
enableA_i : in std_logic;
|
| 926 |
|
|
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
| 927 |
|
|
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
| 928 |
|
|
|
| 929 |
|
|
clkB_i : in std_logic;
|
| 930 |
|
|
enableB_i : in std_logic;
|
| 931 |
|
|
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
| 932 |
|
|
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
| 933 |
|
|
end entity;
|
| 934 |
|
|
|
| 935 |
|
|
|
| 936 |
|
|
-------------------------------------------------------------------------------
|
| 937 |
|
|
-- Architecture for MemorySimpleDualPort.
|
| 938 |
|
|
-------------------------------------------------------------------------------
|
| 939 |
|
|
architecture MemorySimpleDualPortImpl of MemorySimpleDualPort is
|
| 940 |
|
|
type MemoryType is array (natural range <>) of
|
| 941 |
|
|
std_logic_vector(DATA_WIDTH-1 downto 0);
|
| 942 |
|
|
|
| 943 |
|
|
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
|
| 944 |
|
|
|
| 945 |
|
|
begin
|
| 946 |
|
|
process(clkA_i)
|
| 947 |
|
|
begin
|
| 948 |
|
|
if (clkA_i'event and clkA_i = '1') then
|
| 949 |
|
|
if (enableA_i = '1') then
|
| 950 |
|
|
memory(to_integer(unsigned(addressA_i))) <= dataA_i;
|
| 951 |
|
|
end if;
|
| 952 |
|
|
end if;
|
| 953 |
|
|
end process;
|
| 954 |
|
|
|
| 955 |
|
|
process(clkB_i)
|
| 956 |
|
|
begin
|
| 957 |
|
|
if (clkB_i'event and clkB_i = '1') then
|
| 958 |
|
|
if (enableB_i = '1') then
|
| 959 |
|
|
dataB_o <= memory(to_integer(unsigned(addressB_i)));
|
| 960 |
|
|
end if;
|
| 961 |
|
|
end if;
|
| 962 |
|
|
end process;
|
| 963 |
|
|
|
| 964 |
|
|
end architecture;
|
| 965 |
|
|
|
| 966 |
|
|
|
| 967 |
|
|
|
| 968 |
|
|
-------------------------------------------------------------------------------
|
| 969 |
|
|
-- MemorySinglePort
|
| 970 |
|
|
-- Generic synchronous memory with one read/write port.
|
| 971 |
|
|
-------------------------------------------------------------------------------
|
| 972 |
|
|
|
| 973 |
|
|
library ieee;
|
| 974 |
|
|
use ieee.std_logic_1164.all;
|
| 975 |
|
|
use ieee.numeric_std.all;
|
| 976 |
|
|
|
| 977 |
|
|
|
| 978 |
|
|
-------------------------------------------------------------------------------
|
| 979 |
|
|
-- Entity for MemorySinglePort.
|
| 980 |
|
|
-------------------------------------------------------------------------------
|
| 981 |
|
|
entity MemorySinglePort is
|
| 982 |
|
|
generic(
|
| 983 |
|
|
ADDRESS_WIDTH : natural := 1;
|
| 984 |
|
|
DATA_WIDTH : natural := 1);
|
| 985 |
|
|
port(
|
| 986 |
|
|
clk_i : in std_logic;
|
| 987 |
|
|
enable_i : in std_logic;
|
| 988 |
|
|
writeEnable_i : in std_logic;
|
| 989 |
|
|
address_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
| 990 |
|
|
data_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
| 991 |
|
|
data_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
| 992 |
|
|
end entity;
|
| 993 |
|
|
|
| 994 |
|
|
|
| 995 |
|
|
-------------------------------------------------------------------------------
|
| 996 |
|
|
-- Architecture for MemorySinglePort.
|
| 997 |
|
|
-------------------------------------------------------------------------------
|
| 998 |
|
|
architecture MemorySinglePortImpl of MemorySinglePort is
|
| 999 |
|
|
type MemoryType is array (natural range <>) of
|
| 1000 |
|
|
std_logic_vector(DATA_WIDTH-1 downto 0);
|
| 1001 |
|
|
|
| 1002 |
|
|
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1);
|
| 1003 |
|
|
|
| 1004 |
|
|
begin
|
| 1005 |
|
|
process(clk_i)
|
| 1006 |
|
|
begin
|
| 1007 |
|
|
if (clk_i'event and clk_i = '1') then
|
| 1008 |
|
|
if (enable_i = '1') then
|
| 1009 |
|
|
if (writeEnable_i = '1') then
|
| 1010 |
|
|
memory(to_integer(unsigned(address_i))) <= data_i;
|
| 1011 |
|
|
end if;
|
| 1012 |
|
|
|
| 1013 |
|
|
data_o <= memory(to_integer(unsigned(address_i)));
|
| 1014 |
|
|
end if;
|
| 1015 |
|
|
end if;
|
| 1016 |
|
|
end process;
|
| 1017 |
|
|
|
| 1018 |
|
|
end architecture;
|
| 1019 |
|
|
|
| 1020 |
|
|
|
| 1021 |
|
|
|
| 1022 |
|
|
|
| 1023 |
|
|
-------------------------------------------------------------------------------
|
| 1024 |
|
|
-- MemorySimpleDualPortAsync
|
| 1025 |
|
|
-- Generic memory with one synchronous write port and one asynchronous read port.
|
| 1026 |
|
|
-------------------------------------------------------------------------------
|
| 1027 |
|
|
|
| 1028 |
|
|
library ieee;
|
| 1029 |
|
|
use ieee.std_logic_1164.all;
|
| 1030 |
|
|
use ieee.numeric_std.all;
|
| 1031 |
|
|
|
| 1032 |
|
|
|
| 1033 |
|
|
-------------------------------------------------------------------------------
|
| 1034 |
|
|
-- Entity for MemorySimpleDualPortAsync.
|
| 1035 |
|
|
-------------------------------------------------------------------------------
|
| 1036 |
|
|
entity MemorySimpleDualPortAsync is
|
| 1037 |
|
|
generic(
|
| 1038 |
|
|
ADDRESS_WIDTH : natural := 1;
|
| 1039 |
|
|
DATA_WIDTH : natural := 1;
|
| 1040 |
|
|
INIT_VALUE : std_logic := 'U');
|
| 1041 |
|
|
port(
|
| 1042 |
|
|
clkA_i : in std_logic;
|
| 1043 |
|
|
enableA_i : in std_logic;
|
| 1044 |
|
|
addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
| 1045 |
|
|
dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
| 1046 |
|
|
|
| 1047 |
|
|
addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
|
| 1048 |
|
|
dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
|
| 1049 |
|
|
end entity;
|
| 1050 |
|
|
|
| 1051 |
|
|
|
| 1052 |
|
|
-------------------------------------------------------------------------------
|
| 1053 |
|
|
-- Architecture for MemorySimpleDualPortAsync.
|
| 1054 |
|
|
-------------------------------------------------------------------------------
|
| 1055 |
|
|
architecture MemorySimpleDualPortAsyncImpl of MemorySimpleDualPortAsync is
|
| 1056 |
|
|
type MemoryType is array (natural range <>) of
|
| 1057 |
|
|
std_logic_vector(DATA_WIDTH-1 downto 0);
|
| 1058 |
|
|
|
| 1059 |
|
|
signal memory : MemoryType(0 to (2**ADDRESS_WIDTH)-1) := (others=>(others=>INIT_VALUE));
|
| 1060 |
|
|
|
| 1061 |
|
|
begin
|
| 1062 |
|
|
process(clkA_i)
|
| 1063 |
|
|
begin
|
| 1064 |
|
|
if (clkA_i'event and clkA_i = '1') then
|
| 1065 |
|
|
if (enableA_i = '1') then
|
| 1066 |
|
|
memory(to_integer(unsigned(addressA_i))) <= dataA_i;
|
| 1067 |
|
|
end if;
|
| 1068 |
|
|
end if;
|
| 1069 |
|
|
end process;
|
| 1070 |
|
|
|
| 1071 |
|
|
dataB_o <= memory(to_integer(unsigned(addressB_i)));
|
| 1072 |
|
|
|
| 1073 |
|
|
end architecture;
|
| 1074 |
|
|
|
| 1075 |
|
|
|
| 1076 |
|
|
|
| 1077 |
25 |
magro732 |
-------------------------------------------------------------------------------
|
| 1078 |
|
|
-- RioFifo1
|
| 1079 |
|
|
-- Simple fifo which is one entry deep.
|
| 1080 |
|
|
-------------------------------------------------------------------------------
|
| 1081 |
|
|
library ieee;
|
| 1082 |
|
|
use ieee.std_logic_1164.all;
|
| 1083 |
2 |
magro732 |
|
| 1084 |
|
|
|
| 1085 |
25 |
magro732 |
-------------------------------------------------------------------------------
|
| 1086 |
|
|
-- Entity for RioFifo1.
|
| 1087 |
|
|
-------------------------------------------------------------------------------
|
| 1088 |
|
|
entity RioFifo1 is
|
| 1089 |
|
|
generic(
|
| 1090 |
|
|
WIDTH : natural);
|
| 1091 |
|
|
port(
|
| 1092 |
|
|
clk : in std_logic;
|
| 1093 |
|
|
areset_n : in std_logic;
|
| 1094 |
|
|
|
| 1095 |
|
|
empty_o : out std_logic;
|
| 1096 |
|
|
read_i : in std_logic;
|
| 1097 |
|
|
data_o : out std_logic_vector(WIDTH-1 downto 0);
|
| 1098 |
|
|
|
| 1099 |
|
|
full_o : out std_logic;
|
| 1100 |
|
|
write_i : in std_logic;
|
| 1101 |
|
|
data_i : in std_logic_vector(WIDTH-1 downto 0));
|
| 1102 |
|
|
end entity;
|
| 1103 |
|
|
|
| 1104 |
|
|
|
| 1105 |
|
|
-------------------------------------------------------------------------------
|
| 1106 |
|
|
-- Architecture for RioFifo1.
|
| 1107 |
|
|
-------------------------------------------------------------------------------
|
| 1108 |
|
|
architecture RioFifo1Impl of RioFifo1 is
|
| 1109 |
|
|
signal empty : std_logic;
|
| 1110 |
|
|
signal full : std_logic;
|
| 1111 |
|
|
begin
|
| 1112 |
|
|
|
| 1113 |
|
|
empty_o <= empty;
|
| 1114 |
|
|
full_o <= full;
|
| 1115 |
|
|
|
| 1116 |
|
|
process(areset_n, clk)
|
| 1117 |
|
|
begin
|
| 1118 |
|
|
if (areset_n = '0') then
|
| 1119 |
|
|
empty <= '1';
|
| 1120 |
|
|
full <= '0';
|
| 1121 |
|
|
data_o <= (others => '0');
|
| 1122 |
|
|
elsif (clk'event and clk = '1') then
|
| 1123 |
|
|
if (empty = '1') then
|
| 1124 |
|
|
if (write_i = '1') then
|
| 1125 |
|
|
empty <= '0';
|
| 1126 |
|
|
full <= '1';
|
| 1127 |
|
|
data_o <= data_i;
|
| 1128 |
|
|
end if;
|
| 1129 |
|
|
else
|
| 1130 |
|
|
if (read_i = '1') then
|
| 1131 |
|
|
empty <= '1';
|
| 1132 |
|
|
full <= '0';
|
| 1133 |
|
|
end if;
|
| 1134 |
|
|
end if;
|
| 1135 |
|
|
end if;
|
| 1136 |
|
|
end process;
|
| 1137 |
|
|
|
| 1138 |
|
|
end architecture;
|
