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[/] [rio/] [trunk/] [rtl/] [vhdl/] [RioPacketBuffer.vhd] - Blame information for rev 52

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1 3 magro732
-------------------------------------------------------------------------------
2
-- 
3
-- RapidIO IP Library Core
4
-- 
5
-- This file is part of the RapidIO IP library project
6
-- http://www.opencores.org/cores/rio/
7
-- 
8
-- Description
9
-- Containing RapidIO packet buffering functionallity. Two different entities
10
-- are implemented, one with transmission window support and one without.
11
-- 
12
-- To Do:
13
-- -
14
-- 
15
-- Author(s): 
16
-- - Magnus Rosenius, magro732@opencores.org 
17
-- 
18
-------------------------------------------------------------------------------
19
-- 
20
-- Copyright (C) 2013 Authors and OPENCORES.ORG 
21
-- 
22
-- This source file may be used and distributed without 
23
-- restriction provided that this copyright statement is not 
24
-- removed from the file and that any derivative work contains 
25
-- the original copyright notice and the associated disclaimer. 
26
-- 
27
-- This source file is free software; you can redistribute it 
28
-- and/or modify it under the terms of the GNU Lesser General 
29
-- Public License as published by the Free Software Foundation; 
30
-- either version 2.1 of the License, or (at your option) any 
31
-- later version. 
32
-- 
33
-- This source is distributed in the hope that it will be 
34
-- useful, but WITHOUT ANY WARRANTY; without even the implied 
35
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR 
36
-- PURPOSE. See the GNU Lesser General Public License for more 
37
-- details. 
38
-- 
39
-- You should have received a copy of the GNU Lesser General 
40
-- Public License along with this source; if not, download it 
41
-- from http://www.opencores.org/lgpl.shtml 
42
-- 
43
-------------------------------------------------------------------------------
44
 
45
 
46
-------------------------------------------------------------------------------
47
-- RioPacketBuffer
48
-------------------------------------------------------------------------------
49
 
50
library ieee;
51
use ieee.std_logic_1164.all;
52
use ieee.numeric_std.all;
53
use work.rio_common.all;
54
 
55
 
56
-------------------------------------------------------------------------------
57
-- Entity for RioPacketBuffer.
58 20 magro732
--
59
-- Generic variables
60
-- -----------------
61
-- SIZE_ADDRESS_WIDTH - The number of frames in powers of two.
62
-- CONTENT_ADDRESS_WIDTH - The total number of entries in the memory that can
63
-- be used to store packet data.
64
-- CONTENT_WIDTH - The width of the data to store as packet content in the memory.
65
-- MAX_PACKET_SIZE - The number of entries that must be available for a new
66
-- complete full sized packet to be received. This option is present to ensure
67
-- that it is always possible to move a packet to the storage without being
68
-- surprised that the storage is suddenly empty.
69 3 magro732
-------------------------------------------------------------------------------
70
entity RioPacketBuffer is
71 7 magro732
  generic(
72
    SIZE_ADDRESS_WIDTH : natural := 6;
73 20 magro732
    CONTENT_ADDRESS_WIDTH : natural := 8;
74
    CONTENT_WIDTH : natural := 32;
75
    MAX_PACKET_SIZE : natural := 69);
76 3 magro732
  port(
77
    clk : in std_logic;
78
    areset_n : in std_logic;
79
 
80
    inboundWriteFrameFull_o : out std_logic;
81
    inboundWriteFrame_i : in std_logic;
82
    inboundWriteFrameAbort_i : in std_logic;
83
    inboundWriteContent_i : in std_logic;
84 20 magro732
    inboundWriteContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
85 3 magro732
    inboundReadFrameEmpty_o : out std_logic;
86
    inboundReadFrame_i : in std_logic;
87
    inboundReadFrameRestart_i : in std_logic;
88
    inboundReadFrameAborted_o : out std_logic;
89 20 magro732
    inboundReadFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
90 3 magro732
    inboundReadContentEmpty_o : out std_logic;
91
    inboundReadContent_i : in std_logic;
92
    inboundReadContentEnd_o : out std_logic;
93 20 magro732
    inboundReadContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0);
94 3 magro732
 
95
    outboundWriteFrameFull_o : out std_logic;
96
    outboundWriteFrame_i : in std_logic;
97
    outboundWriteFrameAbort_i : in std_logic;
98
    outboundWriteContent_i : in std_logic;
99 20 magro732
    outboundWriteContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
100 3 magro732
    outboundReadFrameEmpty_o : out std_logic;
101
    outboundReadFrame_i : in std_logic;
102
    outboundReadFrameRestart_i : in std_logic;
103
    outboundReadFrameAborted_o : out std_logic;
104 20 magro732
    outboundReadFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
105 3 magro732
    outboundReadContentEmpty_o : out std_logic;
106
    outboundReadContent_i : in std_logic;
107
    outboundReadContentEnd_o : out std_logic;
108 20 magro732
    outboundReadContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
109 3 magro732
end entity;
110
 
111
 
112
-------------------------------------------------------------------------------
113
-- Architecture for RioPacketBuffer.
114
-------------------------------------------------------------------------------
115
architecture RioPacketBufferImpl of RioPacketBuffer is
116
 
117
  component PacketBufferContinous is
118 7 magro732
    generic(
119
      SIZE_ADDRESS_WIDTH : natural;
120 20 magro732
      CONTENT_ADDRESS_WIDTH : natural;
121
      CONTENT_WIDTH : natural;
122
      MAX_PACKET_SIZE : natural);
123 7 magro732
    port(
124
      clk : in std_logic;
125
      areset_n : in std_logic;
126 3 magro732
 
127 7 magro732
      writeFrameFull_o : out std_logic;
128
      writeFrame_i : in std_logic;
129
      writeFrameAbort_i : in std_logic;
130
      writeContent_i : in std_logic;
131 20 magro732
      writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
132 3 magro732
 
133 7 magro732
      readFrameEmpty_o : out std_logic;
134
      readFrame_i : in std_logic;
135
      readFrameRestart_i : in std_logic;
136
      readFrameAborted_o : out std_logic;
137 20 magro732
      readFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
138 7 magro732
      readContentEmpty_o : out std_logic;
139
      readContent_i : in std_logic;
140
      readContentEnd_o : out std_logic;
141 20 magro732
      readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
142 3 magro732
  end component;
143
 
144
begin
145
 
146
  -----------------------------------------------------------------------------
147
  -- Outbound frame buffers.
148
  -----------------------------------------------------------------------------
149
  OutboundPacketBuffer: PacketBufferContinous
150 7 magro732
    generic map(
151
      SIZE_ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH,
152 20 magro732
      CONTENT_ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH,
153
      CONTENT_WIDTH=>CONTENT_WIDTH,
154
      MAX_PACKET_SIZE=>MAX_PACKET_SIZE)
155 3 magro732
    port map(
156
      clk=>clk,
157
      areset_n=>areset_n,
158
      writeFrameFull_o=>outboundWriteFrameFull_o,
159
      writeFrame_i=>outboundWriteFrame_i, writeFrameAbort_i=>outboundWriteFrameAbort_i,
160
      writeContent_i=>outboundWriteContent_i, writeContentData_i=>outboundWriteContentData_i,
161
 
162
      readFrameEmpty_o=>outboundReadFrameEmpty_o,
163
      readFrame_i=>outboundReadFrame_i, readFrameRestart_i=>outboundReadFrameRestart_i,
164
      readFrameAborted_o=>outboundReadFrameAborted_o,
165 20 magro732
      readFrameSize_o=>outboundReadFrameSize_o,
166 3 magro732
      readContentEmpty_o=>outboundReadContentEmpty_o,
167
      readContent_i=>outboundReadContent_i, readContentEnd_o=>outboundReadContentEnd_o,
168
      readContentData_o=>outboundReadContentData_o);
169
 
170
  -----------------------------------------------------------------------------
171
  -- Inbound frame buffers.
172
  -----------------------------------------------------------------------------
173
  InboundPacketBuffer: PacketBufferContinous
174 7 magro732
    generic map(
175
      SIZE_ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH,
176 20 magro732
      CONTENT_ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH,
177
      CONTENT_WIDTH=>CONTENT_WIDTH,
178
      MAX_PACKET_SIZE=>MAX_PACKET_SIZE)
179 3 magro732
    port map(
180
      clk=>clk,
181
      areset_n=>areset_n,
182
      writeFrameFull_o=>inboundWriteFrameFull_o,
183
      writeFrame_i=>inboundWriteFrame_i, writeFrameAbort_i=>inboundWriteFrameAbort_i,
184
      writeContent_i=>inboundWriteContent_i, writeContentData_i=>inboundWriteContentData_i,
185
 
186
      readFrameEmpty_o=>inboundReadFrameEmpty_o,
187
      readFrame_i=>inboundReadFrame_i, readFrameRestart_i=>inboundReadFrameRestart_i,
188
      readFrameAborted_o=>inboundReadFrameAborted_o,
189 20 magro732
      readFrameSize_o=>inboundReadFrameSize_o,
190 3 magro732
      readContentEmpty_o=>inboundReadContentEmpty_o,
191
      readContent_i=>inboundReadContent_i, readContentEnd_o=>inboundReadContentEnd_o,
192
      readContentData_o=>inboundReadContentData_o);
193
 
194
end architecture;
195
 
196
 
197
 
198
 
199
-------------------------------------------------------------------------------
200
-- RioPacketBufferWindow
201
-------------------------------------------------------------------------------
202
 
203
library ieee;
204
use ieee.std_logic_1164.all;
205
use ieee.numeric_std.all;
206
use work.rio_common.all;
207
 
208
 
209
-------------------------------------------------------------------------------
210
-- Entity for RioPacketBufferWindow.
211
-------------------------------------------------------------------------------
212
entity RioPacketBufferWindow is
213 7 magro732
  generic(
214
    SIZE_ADDRESS_WIDTH : natural := 6;
215 20 magro732
    CONTENT_ADDRESS_WIDTH : natural := 8;
216
    CONTENT_WIDTH : natural := 32;
217
    MAX_PACKET_SIZE : natural := 69);
218 3 magro732
  port(
219
    clk : in std_logic;
220
    areset_n : in std_logic;
221
 
222
    inboundWriteFrameFull_o : out std_logic;
223
    inboundWriteFrame_i : in std_logic;
224
    inboundWriteFrameAbort_i : in std_logic;
225
    inboundWriteContent_i : in std_logic;
226 20 magro732
    inboundWriteContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
227 3 magro732
    inboundReadFrameEmpty_o : out std_logic;
228
    inboundReadFrame_i : in std_logic;
229
    inboundReadFrameRestart_i : in std_logic;
230
    inboundReadFrameAborted_o : out std_logic;
231
    inboundReadContentEmpty_o : out std_logic;
232
    inboundReadContent_i : in std_logic;
233
    inboundReadContentEnd_o : out std_logic;
234 20 magro732
    inboundReadContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0);
235 3 magro732
 
236
    outboundWriteFrameFull_o : out std_logic;
237
    outboundWriteFrame_i : in std_logic;
238
    outboundWriteFrameAbort_i : in std_logic;
239
    outboundWriteContent_i : in std_logic;
240 20 magro732
    outboundWriteContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
241 3 magro732
    outboundReadFrameEmpty_o : out std_logic;
242
    outboundReadFrame_i : in std_logic;
243
    outboundReadFrameRestart_i : in std_logic;
244
    outboundReadFrameAborted_o : out std_logic;
245
    outboundReadWindowEmpty_o : out std_logic;
246
    outboundReadWindowReset_i : in std_logic;
247
    outboundReadWindowNext_i : in std_logic;
248
    outboundReadContentEmpty_o : out std_logic;
249
    outboundReadContent_i : in std_logic;
250
    outboundReadContentEnd_o : out std_logic;
251 20 magro732
    outboundReadContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
252 3 magro732
end entity;
253
 
254
 
255
-------------------------------------------------------------------------------
256
-- Architecture for RioPacketBufferWindow.
257
-------------------------------------------------------------------------------
258
architecture RioPacketBufferWindowImpl of RioPacketBufferWindow is
259
 
260
  component PacketBufferContinous is
261 7 magro732
    generic(
262
      SIZE_ADDRESS_WIDTH : natural;
263 20 magro732
      CONTENT_ADDRESS_WIDTH : natural;
264
      CONTENT_WIDTH : natural;
265
      MAX_PACKET_SIZE : natural);
266 7 magro732
    port(
267
      clk : in std_logic;
268
      areset_n : in std_logic;
269 3 magro732
 
270 7 magro732
      writeFrameFull_o : out std_logic;
271
      writeFrame_i : in std_logic;
272
      writeFrameAbort_i : in std_logic;
273
      writeContent_i : in std_logic;
274 20 magro732
      writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
275 3 magro732
 
276 7 magro732
      readFrameEmpty_o : out std_logic;
277
      readFrame_i : in std_logic;
278
      readFrameRestart_i : in std_logic;
279
      readFrameAborted_o : out std_logic;
280 20 magro732
      readFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
281 7 magro732
 
282
      readContentEmpty_o : out std_logic;
283
      readContent_i : in std_logic;
284
      readContentEnd_o : out std_logic;
285 20 magro732
      readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
286 3 magro732
  end component;
287
 
288
  component PacketBufferContinousWindow is
289 7 magro732
    generic(
290
      SIZE_ADDRESS_WIDTH : natural;
291 20 magro732
      CONTENT_ADDRESS_WIDTH : natural;
292
      CONTENT_WIDTH : natural;
293
      MAX_PACKET_SIZE : natural);
294 7 magro732
    port(
295
      clk : in std_logic;
296
      areset_n : in std_logic;
297 3 magro732
 
298 7 magro732
      writeFrameFull_o : out std_logic;
299
      writeFrame_i : in std_logic;
300
      writeFrameAbort_i : in std_logic;
301
      writeContent_i : in std_logic;
302 20 magro732
      writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
303 3 magro732
 
304 7 magro732
      readFrameEmpty_o : out std_logic;
305
      readFrame_i : in std_logic;
306
      readFrameRestart_i : in std_logic;
307
      readFrameAborted_o : out std_logic;
308
 
309
      readWindowEmpty_o : out std_logic;
310
      readWindowReset_i : in std_logic;
311
      readWindowNext_i : in std_logic;
312
 
313
      readContentEmpty_o : out std_logic;
314
      readContent_i : in std_logic;
315
      readContentEnd_o : out std_logic;
316 20 magro732
      readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
317 3 magro732
  end component;
318
 
319
begin
320
 
321
  -----------------------------------------------------------------------------
322
  -- Outbound frame buffers.
323
  -----------------------------------------------------------------------------
324
  OutboundPacketBuffer: PacketBufferContinousWindow
325 7 magro732
    generic map(
326
      SIZE_ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH,
327 20 magro732
      CONTENT_ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH,
328
      CONTENT_WIDTH=>CONTENT_WIDTH,
329
      MAX_PACKET_SIZE=>MAX_PACKET_SIZE)
330 3 magro732
    port map(
331
      clk=>clk,
332
      areset_n=>areset_n,
333
      writeFrameFull_o=>outboundWriteFrameFull_o,
334
      writeFrame_i=>outboundWriteFrame_i, writeFrameAbort_i=>outboundWriteFrameAbort_i,
335
      writeContent_i=>outboundWriteContent_i, writeContentData_i=>outboundWriteContentData_i,
336
 
337
      readFrameEmpty_o=>outboundReadFrameEmpty_o,
338
      readFrame_i=>outboundReadFrame_i, readFrameRestart_i=>outboundReadFrameRestart_i,
339
      readFrameAborted_o=>outboundReadFrameAborted_o,
340
      readWindowEmpty_o=>outboundReadWindowEmpty_o,
341
      readWindowReset_i=>outboundReadWindowReset_i,
342
      readWindowNext_i=>outboundReadWindowNext_i,
343
      readContentEmpty_o=>outboundReadContentEmpty_o,
344
      readContent_i=>outboundReadContent_i, readContentEnd_o=>outboundReadContentEnd_o,
345
      readContentData_o=>outboundReadContentData_o);
346
 
347
  -----------------------------------------------------------------------------
348
  -- Inbound frame buffers.
349
  -----------------------------------------------------------------------------
350
  InboundPacketBuffer: PacketBufferContinous
351 7 magro732
    generic map(
352
      SIZE_ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH,
353 20 magro732
      CONTENT_ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH,
354
      CONTENT_WIDTH=>CONTENT_WIDTH,
355
      MAX_PACKET_SIZE=>MAX_PACKET_SIZE)
356 3 magro732
    port map(
357
      clk=>clk,
358
      areset_n=>areset_n,
359
      writeFrameFull_o=>inboundWriteFrameFull_o,
360
      writeFrame_i=>inboundWriteFrame_i, writeFrameAbort_i=>inboundWriteFrameAbort_i,
361
      writeContent_i=>inboundWriteContent_i, writeContentData_i=>inboundWriteContentData_i,
362
 
363
      readFrameEmpty_o=>inboundReadFrameEmpty_o,
364
      readFrame_i=>inboundReadFrame_i, readFrameRestart_i=>inboundReadFrameRestart_i,
365
      readFrameAborted_o=>inboundReadFrameAborted_o,
366 20 magro732
      readFrameSize_o=>open,
367 3 magro732
      readContentEmpty_o=>inboundReadContentEmpty_o,
368
      readContent_i=>inboundReadContent_i, readContentEnd_o=>inboundReadContentEnd_o,
369
      readContentData_o=>inboundReadContentData_o);
370
 
371
end architecture;
372
 
373
 
374
 
375
 
376
-------------------------------------------------------------------------------
377
-- PacketBufferContinous
378
-- This component stores data in chuncks and stores the size of them. The full
379
-- memory can be used, except for one word, or a specified (using generic)
380
-- maximum number of frames.
381
-------------------------------------------------------------------------------
382
 
383
library ieee;
384
use ieee.std_logic_1164.all;
385
use ieee.numeric_std.all;
386
 
387
 
388
-------------------------------------------------------------------------------
389
-- Entity for PacketBufferContinous.
390
-------------------------------------------------------------------------------
391
entity PacketBufferContinous is
392
  generic(
393 7 magro732
    SIZE_ADDRESS_WIDTH : natural;
394 20 magro732
    CONTENT_ADDRESS_WIDTH : natural;
395
    CONTENT_WIDTH : natural;
396
    MAX_PACKET_SIZE : natural);
397 3 magro732
  port(
398
    clk : in std_logic;
399
    areset_n : in std_logic;
400
 
401
    writeFrameFull_o : out std_logic;
402
    writeFrame_i : in std_logic;
403
    writeFrameAbort_i : in std_logic;
404
    writeContent_i : in std_logic;
405 20 magro732
    writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
406 3 magro732
 
407
    readFrameEmpty_o : out std_logic;
408
    readFrame_i : in std_logic;
409
    readFrameRestart_i : in std_logic;
410
    readFrameAborted_o : out std_logic;
411 20 magro732
    readFrameSize_o : out std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0);
412 3 magro732
 
413
    readContentEmpty_o : out std_logic;
414
    readContent_i : in std_logic;
415
    readContentEnd_o : out std_logic;
416 20 magro732
    readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
417 3 magro732
end entity;
418
 
419
 
420
-------------------------------------------------------------------------------
421
-- Architecture for PacketBufferContinous.
422
-------------------------------------------------------------------------------
423
architecture PacketBufferContinousImpl of PacketBufferContinous is
424
 
425
  component MemorySimpleDualPortAsync is
426
    generic(
427
      ADDRESS_WIDTH : natural := 1;
428
      DATA_WIDTH : natural := 1);
429
    port(
430
      clkA_i : in std_logic;
431
      enableA_i : in std_logic;
432
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
433
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
434
 
435
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
436
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
437
  end component;
438
 
439
  component MemorySimpleDualPort is
440
    generic(
441
      ADDRESS_WIDTH : natural := 1;
442
      DATA_WIDTH : natural := 1);
443
    port(
444
      clkA_i : in std_logic;
445
      enableA_i : in std_logic;
446
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
447
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
448
 
449
      clkB_i : in std_logic;
450
      enableB_i : in std_logic;
451
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
452
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
453
  end component;
454
 
455
  -- The number of available word positions left in the memory.
456
  signal available : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
457
 
458
  -- The position to place new frames.
459
  signal backIndex, backIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
460
 
461
  -- The position to remove old frames.
462
  signal frontIndex, frontIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
463
 
464
  -- The size of the current frame.
465
  signal readFrameEnd_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
466
 
467
  -- The start of unread content.
468
  signal memoryStart_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
469
 
470
  -- The current reading position.
471
  signal memoryRead_p, memoryReadNext_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
472
 
473
  -- The end of unread content.
474
  signal memoryEnd_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
475
 
476
  -- The current writing position.
477
  signal memoryWrite_p, memoryWriteNext_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
478
 
479
  -- Memory output signal containing the position of a frame.
480
  signal framePositionReadData : std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
481
begin
482
 
483
  -----------------------------------------------------------------------------
484
  -- Internal signal assignments.
485
  -----------------------------------------------------------------------------
486
 
487
  available <= not (memoryEnd_p - memoryStart_p);
488
 
489
  backIndexNext <= backIndex + 1;
490
  frontIndexNext <= frontIndex + 1;
491
 
492
  memoryWriteNext_p <= memoryWrite_p + 1;
493
  memoryReadNext_p <= memoryRead_p + 1;
494
 
495
  -----------------------------------------------------------------------------
496
  -- Writer logic.
497
  -----------------------------------------------------------------------------
498
 
499
  writeFrameFull_o <= '1' when ((backIndexNext = frontIndex) or
500 20 magro732
                                (available < MAX_PACKET_SIZE)) else '0';
501 3 magro732
 
502
  Writer: process(clk, areset_n)
503
  begin
504
    if (areset_n = '0') then
505
      backIndex <= (others=>'0');
506
 
507
      memoryEnd_p <= (others=>'0');
508
      memoryWrite_p <= (others=>'0');
509
    elsif (clk'event and clk = '1') then
510
 
511
      if (writeFrameAbort_i = '1') then
512
        memoryWrite_p <= memoryEnd_p;
513
      elsif (writeContent_i = '1') then
514
        memoryWrite_p <= memoryWriteNext_p;
515
      end if;
516
 
517
      if(writeFrame_i = '1') then
518
        memoryEnd_p <= memoryWrite_p;
519
        backIndex <= backIndexNext;
520
      end if;
521
 
522
    end if;
523
  end process;
524
 
525
  -----------------------------------------------------------------------------
526
  -- Frame cancellation logic.
527
  -----------------------------------------------------------------------------
528
 
529
  process(clk, areset_n)
530
  begin
531
    if (areset_n = '0') then
532
      readFrameAborted_o <= '0';
533
    elsif (clk'event and clk = '1') then
534
 
535
      if ((frontIndex = backIndex) and
536
          ((writeFrameAbort_i = '1') and (readFrameRestart_i = '0'))) then
537
        readFrameAborted_o <= '1';
538
      elsif ((writeFrameAbort_i = '0') and (readFrameRestart_i = '1')) then
539
        readFrameAborted_o <= '0';
540
      end if;
541
 
542
    end if;
543
  end process;
544
 
545
  -----------------------------------------------------------------------------
546
  -- Reader logic.
547
  -----------------------------------------------------------------------------
548
 
549
  readFrameEmpty_o <= '1' when (frontIndex = backIndex) else '0';
550
  readContentEmpty_o <= '1' when ((frontIndex = backIndex) and
551
                                  (memoryWrite_p = memoryRead_p)) else '0';
552 20 magro732
  readFrameSize_o <= std_logic_vector(readFrameEnd_p - memoryStart_p);
553 3 magro732
 
554
  Reader: process(clk, areset_n)
555
  begin
556
    if (areset_n = '0') then
557
      frontIndex <= (others=>'0');
558
 
559
      memoryStart_p <= (others=>'0');
560
      memoryRead_p <= (others=>'0');
561
 
562
      readContentEnd_o <= '0';
563
    elsif (clk'event and clk = '1') then
564
 
565
      -- REMARK: Break apart into registers to avoid priority ladder???
566
      if(readFrameRestart_i = '1') then
567
        memoryRead_p <= memoryStart_p;
568
      elsif(readContent_i = '1') then
569
        if(memoryRead_p = readFrameEnd_p) then
570
          readContentEnd_o <= '1';
571
        else
572
          readContentEnd_o <= '0';
573
          memoryRead_p <= memoryReadNext_p;
574
        end if;
575
      elsif(readFrame_i = '1') then
576
        memoryStart_p <= readFrameEnd_p;
577
        frontIndex <= frontIndexNext;
578
        memoryRead_p <= readFrameEnd_p;
579
      end if;
580
 
581
    end if;
582
  end process;
583
 
584
  -----------------------------------------------------------------------------
585
  -- Frame positioning memory signals.
586
  -----------------------------------------------------------------------------
587
 
588
  readFrameEnd_p <= unsigned(framePositionReadData);
589
 
590
  -- Memory to keep frame starting/ending positions in.
591
  FramePosition: MemorySimpleDualPortAsync
592
    generic map(ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH, DATA_WIDTH=>CONTENT_ADDRESS_WIDTH)
593
    port map(
594
      clkA_i=>clk, enableA_i=>writeFrame_i,
595
      addressA_i=>std_logic_vector(backIndex), dataA_i=>std_logic_vector(memoryWrite_p),
596
      addressB_i=>std_logic_vector(frontIndex), dataB_o=>framePositionReadData);
597
 
598
  -----------------------------------------------------------------------------
599
  -- Frame content memory signals.
600
  -----------------------------------------------------------------------------
601
 
602
  -- Memory to keep frame content in.
603
  -- REMARK: Use paritybits here as well to make sure the frame data does not
604
  -- become corrupt???
605
  FrameContent: MemorySimpleDualPort
606 20 magro732
    generic map(ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH, DATA_WIDTH=>CONTENT_WIDTH)
607 3 magro732
    port map(
608
      clkA_i=>clk, enableA_i=>writeContent_i,
609
      addressA_i=>std_logic_vector(memoryWrite_p), dataA_i=>writeContentData_i,
610
      clkB_i=>clk, enableB_i=>readContent_i,
611
      addressB_i=>std_logic_vector(memoryRead_p), dataB_o=>readContentData_o);
612
 
613
end architecture;
614
 
615
 
616
 
617
-------------------------------------------------------------------------------
618
-- PacketBufferContinousWindow
619
-- This component stores data in chuncks and stores the size of them. The full
620
-- memory can be used, except for one word, or a specified (using generic)
621
-- maximum number of frames.
622
-------------------------------------------------------------------------------
623
 
624
library ieee;
625
use ieee.std_logic_1164.all;
626
use ieee.numeric_std.all;
627
 
628
 
629
-------------------------------------------------------------------------------
630
-- Entity for PacketBufferContinousWindow.
631
-------------------------------------------------------------------------------
632
entity PacketBufferContinousWindow is
633
  generic(
634 7 magro732
    SIZE_ADDRESS_WIDTH : natural;
635 20 magro732
    CONTENT_ADDRESS_WIDTH : natural;
636
    CONTENT_WIDTH : natural;
637
    MAX_PACKET_SIZE : natural);
638 3 magro732
  port(
639
    clk : in std_logic;
640
    areset_n : in std_logic;
641
 
642
    writeFrameFull_o : out std_logic;
643
    writeFrame_i : in std_logic;
644
    writeFrameAbort_i : in std_logic;
645
    writeContent_i : in std_logic;
646 20 magro732
    writeContentData_i : in std_logic_vector(CONTENT_WIDTH-1 downto 0);
647 3 magro732
 
648
    readFrameEmpty_o : out std_logic;
649
    readFrame_i : in std_logic;
650
    readFrameRestart_i : in std_logic;
651
    readFrameAborted_o : out std_logic;
652
 
653
    readWindowEmpty_o : out std_logic;
654
    readWindowReset_i : in std_logic;
655
    readWindowNext_i : in std_logic;
656
 
657
    readContentEmpty_o : out std_logic;
658
    readContent_i : in std_logic;
659
    readContentEnd_o : out std_logic;
660 20 magro732
    readContentData_o : out std_logic_vector(CONTENT_WIDTH-1 downto 0));
661 3 magro732
end entity;
662
 
663
 
664
-------------------------------------------------------------------------------
665
-- Architecture for PacketBufferContinousWindow.
666
-------------------------------------------------------------------------------
667
architecture PacketBufferContinousWindowImpl of PacketBufferContinousWindow is
668
 
669
  component MemorySimpleDualPortAsync is
670
    generic(
671
      ADDRESS_WIDTH : natural := 1;
672
      DATA_WIDTH : natural := 1);
673
    port(
674
      clkA_i : in std_logic;
675
      enableA_i : in std_logic;
676
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
677
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
678
 
679
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
680
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
681
  end component;
682
 
683
  component MemorySimpleDualPort is
684
    generic(
685
      ADDRESS_WIDTH : natural := 1;
686
      DATA_WIDTH : natural := 1);
687
    port(
688
      clkA_i : in std_logic;
689
      enableA_i : in std_logic;
690
      addressA_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
691
      dataA_i : in std_logic_vector(DATA_WIDTH-1 downto 0);
692
 
693
      clkB_i : in std_logic;
694
      enableB_i : in std_logic;
695
      addressB_i : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
696
      dataB_o : out std_logic_vector(DATA_WIDTH-1 downto 0));
697
  end component;
698
 
699
  -- The number of available word positions left in the memory.
700
  signal available : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
701
 
702
  signal backIndex, backIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
703
  signal frontIndex, frontIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
704
  signal windowIndex, windowIndexNext : unsigned(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
705
 
706
  -- The size of the current frame.
707
  signal readFrameEnd_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
708
 
709
  -- The start of unread content.
710
  signal memoryStart_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
711
 
712
  -- The start of unread window content.
713
  signal memoryStartWindow_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
714
 
715
  -- The current reading position.
716
  signal memoryRead_p, memoryReadNext_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
717
 
718
  -- The end of unread content.
719
  signal memoryEnd_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
720
 
721
  -- The current writing position.
722
  signal memoryWrite_p, memoryWriteNext_p : unsigned(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
723
 
724
  signal framePositionReadAddress : std_logic_vector(SIZE_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
725
  signal framePositionReadData : std_logic_vector(CONTENT_ADDRESS_WIDTH-1 downto 0) := (others=>'0');
726
begin
727
 
728
  -----------------------------------------------------------------------------
729
  -- Internal signal assignments.
730
  -----------------------------------------------------------------------------
731
 
732
  available <= not (memoryEnd_p - memoryStart_p);
733
 
734
  backIndexNext <= backIndex + 1;
735
  frontIndexNext <= frontIndex + 1;
736
  windowIndexNext <= windowIndex + 1;
737
 
738
  memoryWriteNext_p <= memoryWrite_p + 1;
739
  memoryReadNext_p <= memoryRead_p + 1;
740
 
741
  -----------------------------------------------------------------------------
742
  -- Writer logic.
743
  -----------------------------------------------------------------------------
744
 
745
  writeFrameFull_o <= '1' when ((backIndexNext = frontIndex) or
746 20 magro732
                                (available < MAX_PACKET_SIZE)) else '0';
747 3 magro732
 
748
  Writer: process(clk, areset_n)
749
  begin
750
    if (areset_n = '0') then
751
      backIndex <= (others=>'0');
752
 
753
      memoryEnd_p <= (others=>'0');
754
      memoryWrite_p <= (others=>'0');
755
    elsif (clk'event and clk = '1') then
756
 
757
      if (writeFrameAbort_i = '1') then
758
        memoryWrite_p <= memoryEnd_p;
759
      elsif (writeContent_i = '1') then
760
        memoryWrite_p <= memoryWriteNext_p;
761
      end if;
762
 
763
      if(writeFrame_i = '1') then
764
        memoryEnd_p <= memoryWrite_p;
765
        backIndex <= backIndexNext;
766
      end if;
767
 
768
    end if;
769
  end process;
770
 
771
  -----------------------------------------------------------------------------
772
  -- Frame cancellation logic.
773
  -----------------------------------------------------------------------------
774
 
775
  process(clk, areset_n)
776
  begin
777
    if (areset_n = '0') then
778
      readFrameAborted_o <= '0';
779
    elsif (clk'event and clk = '1') then
780
 
781
      if ((windowIndex = backIndex) and
782
          ((writeFrameAbort_i = '1') and (readFrameRestart_i = '0'))) then
783
        readFrameAborted_o <= '1';
784
      elsif ((writeFrameAbort_i = '0') and (readFrameRestart_i = '1')) then
785
        readFrameAborted_o <= '0';
786
      end if;
787
 
788
    end if;
789
  end process;
790
 
791
  -----------------------------------------------------------------------------
792
  -- Reader logic.
793
  -----------------------------------------------------------------------------
794
 
795
  readFrameEmpty_o <= '1' when (frontIndex = backIndex) else '0';
796
  readWindowEmpty_o <= '1' when (windowIndex = backIndex) else '0';
797
  readContentEmpty_o <= '1' when ((windowIndex = backIndex) and
798
                                  (memoryWrite_p = memoryRead_p)) else '0';
799
 
800
  Reader: process(clk, areset_n)
801
  begin
802
    if (areset_n = '0') then
803
      frontIndex <= (others=>'0');
804
      windowIndex <= (others=>'0');
805
 
806
      memoryStart_p <= (others=>'0');
807
      memoryStartWindow_p <= (others=>'0');
808
      memoryRead_p <= (others=>'0');
809
 
810
      readContentEnd_o <= '0';
811
    elsif (clk'event and clk = '1') then
812
 
813
      -- REMARK: Break apart into registers to avoid priority ladder???
814
      if(readFrameRestart_i = '1') then
815
        memoryRead_p <= memoryStartWindow_p;
816
      elsif(readContent_i = '1') then
817
        if(memoryRead_p = readFrameEnd_p) then
818
          readContentEnd_o <= '1';
819
        else
820
          readContentEnd_o <= '0';
821
          memoryRead_p <= memoryReadNext_p;
822
        end if;
823
      elsif(readFrame_i = '1') then
824
        memoryStart_p <= readFrameEnd_p;
825
        frontIndex <= frontIndexNext;
826
      elsif(readWindowReset_i = '1') then
827
        memoryStartWindow_p <= memoryStart_p;
828
        windowIndex <= frontIndex;
829
        memoryRead_p <= memoryStart_p;
830
      elsif(readWindowNext_i = '1') then
831
        memoryStartWindow_p <= readFrameEnd_p;
832
        windowIndex <= windowIndexNext;
833
        memoryRead_p <= readFrameEnd_p;
834
      end if;
835
 
836
    end if;
837
  end process;
838
 
839
  -----------------------------------------------------------------------------
840
  -- Frame positioning memory signals.
841
  -----------------------------------------------------------------------------
842
 
843
  -- Assign the address from both frontIndex and windowIndex to be able to
844
  -- share the memory between the two different types of accesses. This assumes
845
  -- that the window is not accessed at the same time as the other signal.
846
  framePositionReadAddress <= std_logic_vector(frontIndex) when (readFrame_i = '1') else
847
                              std_logic_vector(windowIndex);
848
  readFrameEnd_p <= unsigned(framePositionReadData);
849
 
850
  -- Memory to keep frame starting/ending positions in.
851
  FramePosition: MemorySimpleDualPortAsync
852
    generic map(ADDRESS_WIDTH=>SIZE_ADDRESS_WIDTH, DATA_WIDTH=>CONTENT_ADDRESS_WIDTH)
853
    port map(
854
      clkA_i=>clk, enableA_i=>writeFrame_i,
855
      addressA_i=>std_logic_vector(backIndex), dataA_i=>std_logic_vector(memoryWrite_p),
856
      addressB_i=>framePositionReadAddress, dataB_o=>framePositionReadData);
857
 
858
  -----------------------------------------------------------------------------
859
  -- Frame content memory signals.
860
  -----------------------------------------------------------------------------
861
 
862
  -- Memory to keep frame content in.
863
  -- REMARK: Use paritybits here as well to make sure the frame data does not
864
  -- become corrupt???
865
  FrameContent: MemorySimpleDualPort
866 20 magro732
    generic map(ADDRESS_WIDTH=>CONTENT_ADDRESS_WIDTH, DATA_WIDTH=>CONTENT_WIDTH)
867 3 magro732
    port map(
868
      clkA_i=>clk, enableA_i=>writeContent_i,
869
      addressA_i=>std_logic_vector(memoryWrite_p), dataA_i=>writeContentData_i,
870
      clkB_i=>clk, enableB_i=>readContent_i,
871
      addressB_i=>std_logic_vector(memoryRead_p), dataB_o=>readContentData_o);
872
 
873
end architecture;

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