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//---------------------------------------------------------------------------
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// RISC 16F84 "light" core
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//
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// This file is part of the "risc_16F84" project.
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// http://www.opencores.org/cores/risc_16F84
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//
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//
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// Description: See description below (which suffices for IP core
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// specification document.)
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//
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// Copyright (C) 1999 Sumio Morioka (original VHDL design version)
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// Copyright (C) 2001 John Clayton and OPENCORES.ORG (this Verilog version)
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//
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// NOTE: This source code is free for educational/hobby use only. It cannot
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// be used for commercial purposes without the consent of Microchip
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// Technology incorporated.
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source.
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// If not, download it from http://www.opencores.org/lgpl.shtml
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//
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//---------------------------------------------------------------------------
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//
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// Author: John Clayton
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// Date : January 29, 2002
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//
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// (NOTE: Date formatted as day/month/year.)
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// Update: 29/01/02 copied this file from memory_sizer.v (pared down).
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// Translated the module and signal declarations.
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// Transformed the instruction wires to lowercase.
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// Transformed the addressing wires to lowercase.
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// Update: 31/01/02 Translated the instruction decoder.
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// Update: 5/02/02 Determined that stack is simply a circular buffer of
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// 8 locations, 13 bits per location. Started translating
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// "main_efsm" process. Added all code from piccore.vhd
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// into this file for eventual translation. Concluded that
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// "stack_full_node" is not needed.
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// Update: 6/02/02 Translated the "ram_i_node" if/else precedural assignment.
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// Update: 7/02/02 Changed all := to <=, changed all '0' to 0 and '1' to 1.
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// Replaced all " downto " with ":".
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// Finished translating QRESET state.
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// Update: 20/02/02 Replaced all instances of Qreset with QRESET_PP. Also
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// replaced other state designations with their new names.
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// Finished translating Q1, Q2 states.
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// Update: 22/02/02 Translated section 2-4-1-1 (aluout register)
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// Update: 27/02/02 Replaced all "or" with "||" in if statements
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// Replaced all "and" with "&&" in if statements.
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// Replaced all "not" with "~" in if statements.
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// Finished translating Q3,Q4 states.
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// Translated output signal assignments at end of code.
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// Translated interrupt trigger processes.
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// Update: 28/02/02 Finished translation of WDT and TMR0 prescaler.
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// Trimmed line length to 80 characters throughout.
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// Prepared to attempt initial syntax checking.
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// Cleaned up some naming conventions, and verified that
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// all I/O pins have _i or _o appended in the body of the
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// code.
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// Update: 03/04/02 Changed "progdata_i" to "prog_dat_i" Also changed
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// "progadr_o" to "prog_adr_o"
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// Update: 04/04/02 Created new file "risc16f84_lite.v" This file is reduced
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// and simplified from the original "risc16f84.v" file.
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// Specifically, I am removing EEPROM support, and
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// consolidating porta and portb I/O pins so that they
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// are bidirectional.
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// Update: 04/26/02 Fixed bug in aluout_reg logic, so that AND/OR type of
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// instructions now use bitwise operators (they were wrongly
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// coded using logical operators!)
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// Update: 05/01/02 Fixed another bug -- the rrf and rlf instructions were
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// coded incorrectly.
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// Update: 03/05/02 Fixed another bug -- the carry bit was incorrect (the
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// problem was discovered while performing SUBWF X,W where
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// W contained 0 and X contained 1. (1-0). The logic for
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// the carry bit appears to have been incorrect even in
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// the original VHDL code by Sumio Morioka.
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// Update: 10/30/02 Fixed syntax error pointed out by Cheol-Kyoo Lee, who got
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// the source code from opencores.com. Removed semicolon
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// from "endcase" statements.
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//
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// Description
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//---------------------------------------------------------------------------
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// This logic module implements a small RISC microcontroller, with functions
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// and instruction set very similar to those of the Microchip 16F84 chip.
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// This work is a translation (from VHDL to Verilog) of the "CQPIC" design
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// published in 1999 by Sumio Morioka of Japan, and published in the December
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// 1999 issue of "Transistor Gijutsu Magazine." The translation was performed
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// by John Clayton, without the use of any translation tools.
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//
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// Original version used as basis for translation: CQPIC version 1.00b
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// (December 10, 2000)
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//---------------------------------------------------------------------------
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`define STATEBIT_SIZE 3 // Size of state machine register (bits)
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module risc16f84_lite (
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prog_dat_i, // [13:0] ROM read data
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prog_adr_o, // [12:0] ROM address
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ram_dat_i, // [7:0] RAM read data
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ram_dat_o, // [7:0] RAM write data
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ram_adr_o, // [8:0] RAM address; ram_adr[8:7] indicates RAM-BANK
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readram_o, // RAM read strobe (H active)
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writeram_o, // RAM write strobe (H active)
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porta_io, // [4:0] PORT-A
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portb_io, // [7:0] PORT-B
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rbpu_o, // PORT_B pull-up enable (usually not used)
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int0_i, // PORT-B(0) INT
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int4_i, // PORT-B(4) INT
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int5_i, // PORT-B(5) INT
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int6_i, // PORT-B(6) INT
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int7_i, // PORT-B(7) INT
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t0cki_i, // T0CKI (PORT-A(4))
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wdt_ena_i, // WDT enable (H active)
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wdt_clk_i, // WDT clock
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wdt_full_o, // WDT-full indicator (H active)
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powerdown_o, // SLEEP-mode; if H, you can stop system clock clk_i
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startclk_o, // WAKEUP; if H, turn on clk_i for leaving sleep-mode
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pon_rst_n_i, // Power-on reset (L active)
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mclr_n_i, // Normal reset (L active)
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clk_i, // Clock input
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clk_o // Clock output (clk_i/4)
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);
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// You can change the following parameters as you would like
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parameter STACK_SIZE_PP = 8; // Size of PC stack
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parameter LOG2_STACK_SIZE_PP = 3; // Log_2(stack_size)
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parameter WDT_SIZE_PP = 255; // Size of watch dog timer (WDT)
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parameter WDT_BITS_PP = 8; // Bits needed for watch dog timer (WDT)
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// State definitions for state machine, provided as parameters to allow
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// for redefinition of state values by the instantiator if desired.
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parameter QRESET_PP = 3'b100; // reset state
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parameter Q1_PP = 3'b000; // state Q1
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parameter Q2_PP = 3'b001; // state Q2
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parameter Q3_PP = 3'b011; // state Q3
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parameter Q4_PP = 3'b010; // state Q4
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// I/O declarations
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// program ROM data bus/address bus
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input [13:0] prog_dat_i; // ROM read data
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output [12:0] prog_adr_o; // ROM address
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// data RAM data bus/address bus/control signals
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input [7:0] ram_dat_i; // RAM read data
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output [7:0] ram_dat_o; // RAM write data
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output [8:0] ram_adr_o; // RAM address; ram_adr[8:7] indicates RAM-BANK
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output readram_o; // RAM read strobe (H active)
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output writeram_o; // RAM write strobe (H active)
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// I/O ports
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inout [4:0] porta_io; // PORT-A
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inout [7:0] portb_io; // PORT-B
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output rbpu_o; // PORT_B pull-up enable (usually not used)
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// PORT-B interrupt input
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input int0_i; // PORT-B(0) INT
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input int4_i; // PORT-B(4) INT
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input int5_i; // PORT-B(5) INT
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input int6_i; // PORT-B(6) INT
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input int7_i; // PORT-B(7) INT
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// TMR0 Control
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input t0cki_i; // T0CKI (PORT-A(4))
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// Watch Dog Timer Control
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input wdt_ena_i; // WDT enable (H active)
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input wdt_clk_i; // WDT clock
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output wdt_full_o; // WDT-full indicator (H active)
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// CPU clock stop/start indicators
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output powerdown_o; // SLEEP-mode; if H, then you can
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// stop the system clock clk_i
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output startclk_o; // WAKEUP; if H, you should turn on
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// clock clk_i for waking up from sleep-mode
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// CPU reset
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input pon_rst_n_i; // Power-on reset (LOW active)
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input mclr_n_i; // Normal reset (LOW active)
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// CPU clock
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input clk_i; // Clock input
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output clk_o; // Clock output (clk_i/4)
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// Internal signal declarations
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// User registers
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reg [7:0] w_reg; // W
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reg [7:0] tmr0_reg; // TMR0
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reg [12:0] pc_reg; // PCH/PCL
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reg [7:0] status_reg; // STATUS
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reg [7:0] fsr_reg; // FSR
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reg [4:0] porta_i_sync_reg; // PORTA IN (synchronizer)
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reg [4:0] porta_o_reg; // PORTA OUT
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reg [7:0] portb_i_sync_reg; // PORTB IN (synchronizer)
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reg [7:0] portb_o_reg; // PORTB OUT
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reg [4:0] pclath_reg; // PCLATH
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reg [7:0] intcon_reg; // INTCON
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reg [7:0] option_reg; // OPTION
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reg [4:0] trisa_reg; // TRISA
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reg [7:0] trisb_reg; // TRISB
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// Internal registers for controlling instruction execution
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reg [13:0] inst_reg; // Hold fetched op-code/operand
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reg [7:0] aluinp1_reg; // data source (1 of 2)
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reg [7:0] aluinp2_reg; // data source (2 of 2)
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reg c_in; // Used with ALU data sources.
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reg [7:0] aluout_reg; // result of calculation
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reg exec_op_reg; // if L (i.e. GOTO instruction etc), stall exec.
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reg intstart_reg; // if H (i.e. interrupt), stall instr. exec.
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reg sleepflag_reg; // if H, sleeping.
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// Stack
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// stack (array of data-registers)
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reg [12:0] stack_reg [STACK_SIZE_PP-1:0];
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// stack pointer (binary encoded)
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reg [LOG2_STACK_SIZE_PP-1:0] stack_pnt_reg;
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// WDT register and its control
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reg [WDT_BITS_PP-1:0] wdt_reg; // WDT counter
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reg wdt_full_reg; // WDT->CPU; hold WDT-full signal until
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// CPU is reset
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reg wdt_full_node;
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wire wdt_init; // Initialize the WDT
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reg [2:0] wdt_full_sync_reg; // CPU; synchronizer for wdt_full_reg
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reg wdt_clr_reg; // CPU->WDT; request to zero-clear wdt_reg
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reg wdt_clr_reqhold_reg; // CPU; hold a clear-request if
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// previous request is still processing
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reg [1:0] wdt_clr_req_reg; // WDT; synchronizer for wdt_clr_reg
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wire wdt_clr_ack; // WDT->CPU; ack to wdt_clr_reg
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// (same with wdt_clr_req_reg(1))
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reg wdt_clr_ack_sync_reg; // CPU; synchronizer for wdt_clr_ack
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reg wdt_full_clr_reg; // CPU->WDT; request to clear wdt_full_reg
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reg [1:0] wdt_fullclr_req_reg; // WDT; synchronizer for wdt_full_clr_reg
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// TMR0 prescaler
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wire ps_clk; // clock for prescaler
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reg [7:0] pscale_reg; // prescaler (range 0 to 255)
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reg ps_full_reg; // clock for TMR0, from prescaler
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wire inc_tmr_clk; // clock for TMR0
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reg inc_tmr_hold_reg; // hold TMR0 increment request
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reg [7:0] rateval; // Temporary storage value within process
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// Interrupt registers/nodes
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reg [4:0] intrise_reg; // detect positive edge of PORT-B inputs
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reg [4:0] intdown_reg; // detect negative edge of PORT-B inputs
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// Interrupt triggers
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wire rb0_int;
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wire rb4_int;
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wire rb5_int;
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wire rb6_int;
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wire rb7_int;
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wire rbint; // RB4-7 interrupt trigger
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wire inte; // RB0 interrupt trigger
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reg [4:0] intclr_reg; // CPU; clear intrise_reg and intdown_reg
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wire intclr0; // Individual wires used in sensitivity lists
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wire intclr1; // since "simple variables" are OK,
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wire intclr2; // but apparently intclr_reg[0] is not a
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wire intclr3; // "simple variable or its negation."
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wire intclr4;
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// State register
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reg [`STATEBIT_SIZE-1:0] state_reg;
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// Result of decoding instruction -- only 1 is active at a time
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wire inst_addlw;
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wire inst_addwf;
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wire inst_andlw;
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wire inst_andwf;
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wire inst_bcf;
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wire inst_bsf;
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wire inst_btfsc;
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wire inst_btfss;
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wire inst_call;
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wire inst_clrf;
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wire inst_clrw;
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wire inst_clrwdt;
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wire inst_comf;
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wire inst_decf;
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wire inst_decfsz;
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wire inst_goto;
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wire inst_incf;
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wire inst_incfsz;
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wire inst_iorlw;
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wire inst_iorwf;
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wire inst_movlw;
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wire inst_movf;
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wire inst_movwf;
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wire inst_retfie;
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wire inst_retlw;
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wire inst_ret;
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wire inst_rlf;
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wire inst_rrf;
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wire inst_sleep;
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312 |
|
|
wire inst_sublw;
|
313 |
|
|
wire inst_subwf;
|
314 |
|
|
wire inst_swapf;
|
315 |
|
|
wire inst_xorlw;
|
316 |
|
|
wire inst_xorwf;
|
317 |
|
|
|
318 |
|
|
// Result of calculating RAM access address
|
319 |
|
|
wire [8:0] ram_adr_node; // RAM access address
|
320 |
|
|
|
321 |
|
|
// These wires indicate accesses to special registers...
|
322 |
|
|
// Only 1 is active at a time.
|
323 |
|
|
wire addr_tmr0;
|
324 |
|
|
wire addr_pcl;
|
325 |
|
|
wire addr_stat;
|
326 |
|
|
wire addr_fsr;
|
327 |
|
|
wire addr_porta;
|
328 |
|
|
wire addr_portb;
|
329 |
|
|
wire addr_pclath;
|
330 |
|
|
wire addr_intcon;
|
331 |
|
|
wire addr_option;
|
332 |
|
|
wire addr_trisa;
|
333 |
|
|
wire addr_trisb;
|
334 |
|
|
wire addr_sram;
|
335 |
|
|
|
336 |
|
|
// Other output registers (for removing hazards)
|
337 |
|
|
reg writeram_reg; // data-sram write strobe
|
338 |
|
|
reg [8:0] ram_adr_reg; // data-sram address
|
339 |
|
|
reg clk_o_reg; // clock output
|
340 |
|
|
|
341 |
|
|
// Synchronizers
|
342 |
|
|
reg inte_sync_reg;
|
343 |
|
|
reg rbint_sync_reg;
|
344 |
|
|
reg [1:0] inc_tmr_sync_reg;
|
345 |
|
|
reg mclr_sync_reg;
|
346 |
|
|
reg poweron_sync_reg;
|
347 |
|
|
|
348 |
|
|
// Signals used in "main_efsm" procedure
|
349 |
|
|
// (Intermediate nodes used for resource sharing.)
|
350 |
|
|
reg [7:0] ram_i_node; // result of reading RAM/Special registers
|
351 |
|
|
reg [12:0] inc_pc_node; // value of PC + 1
|
352 |
|
|
wire [7:0] mask_node; // bit mask for logical operations
|
353 |
|
|
reg [8:0] add_node; // result of 8bit addition
|
354 |
|
|
reg [4:0] addlow_node; // result of low-4bit addition
|
355 |
|
|
wire temp; // Placeholder wire
|
356 |
|
|
wire dtemp; // Placeholder wire
|
357 |
|
|
reg aluout_zero_node; // H if ALUOUT = 0
|
358 |
|
|
reg writew_node; // H if destination is W register
|
359 |
|
|
reg writeram_node; // H if destination is RAM/Special registers
|
360 |
|
|
reg int_node; // H if interrupt request comes
|
361 |
|
|
reg wdt_rst_node; // H if WDT-reset request comes
|
362 |
|
|
reg reset_cond; // H for any reset request (jump to QRESET_PP state)
|
363 |
|
|
|
364 |
|
|
//--------------------------------------------------------------------------
|
365 |
|
|
// Instantiations
|
366 |
|
|
//--------------------------------------------------------------------------
|
367 |
|
|
|
368 |
|
|
|
369 |
|
|
//--------------------------------------------------------------------------
|
370 |
|
|
// Functions & Tasks
|
371 |
|
|
//--------------------------------------------------------------------------
|
372 |
|
|
|
373 |
|
|
function [7:0] bitwise_tristate;
|
374 |
|
|
input [7:0] port;
|
375 |
|
|
input [7:0] tris;
|
376 |
|
|
integer k;
|
377 |
|
|
begin
|
378 |
|
|
for (k=0; k<8; k=k+1) bitwise_tristate[k] <= (tris[k])?1'bZ:port[k];
|
379 |
|
|
end
|
380 |
|
|
endfunction
|
381 |
|
|
|
382 |
|
|
|
383 |
|
|
//--------------------------------------------------------------------------
|
384 |
|
|
// Module code
|
385 |
|
|
//--------------------------------------------------------------------------
|
386 |
|
|
|
387 |
|
|
|
388 |
|
|
// CPU synchronizers
|
389 |
|
|
always @(posedge clk_i)
|
390 |
|
|
begin
|
391 |
|
|
inte_sync_reg <= inte;
|
392 |
|
|
rbint_sync_reg <= rbint;
|
393 |
|
|
wdt_clr_ack_sync_reg <= wdt_clr_ack;
|
394 |
|
|
mclr_sync_reg <= mclr_n_i;
|
395 |
|
|
poweron_sync_reg <= pon_rst_n_i;
|
396 |
|
|
inc_tmr_sync_reg[0] <= inc_tmr_clk;
|
397 |
|
|
inc_tmr_sync_reg[1] <= inc_tmr_sync_reg[0];
|
398 |
|
|
if (~poweron_sync_reg || ~mclr_sync_reg)
|
399 |
|
|
wdt_full_sync_reg <= 3'b0;
|
400 |
|
|
else
|
401 |
|
|
begin
|
402 |
|
|
wdt_full_sync_reg[0] <= wdt_full_reg;
|
403 |
|
|
wdt_full_sync_reg[1] <= wdt_full_sync_reg[0]; // (remove meta-stability)
|
404 |
|
|
wdt_full_sync_reg[2] <= wdt_full_sync_reg[1]; // (detect positive edge)
|
405 |
|
|
end
|
406 |
|
|
end
|
407 |
|
|
|
408 |
|
|
|
409 |
|
|
// Decode OPcode (see pp.54 of PIC16F84 data sheet)
|
410 |
|
|
// only 1 signal of the following signals will be '1'
|
411 |
|
|
assign inst_call = (inst_reg[13:11] == 3'b100 );
|
412 |
|
|
assign inst_goto = (inst_reg[13:11] == 3'b101 );
|
413 |
|
|
assign inst_bcf = (inst_reg[13:10] == 4'b0100 );
|
414 |
|
|
assign inst_bsf = (inst_reg[13:10] == 4'b0101 );
|
415 |
|
|
assign inst_btfsc = (inst_reg[13:10] == 4'b0110 );
|
416 |
|
|
assign inst_btfss = (inst_reg[13:10] == 4'b0111 );
|
417 |
|
|
assign inst_movlw = (inst_reg[13:10] == 4'b1100 );
|
418 |
|
|
assign inst_retlw = (inst_reg[13:10] == 4'b1101 );
|
419 |
|
|
assign inst_sublw = (inst_reg[13:9] == 5'b11110 );
|
420 |
|
|
assign inst_addlw = (inst_reg[13:9] == 5'b11111 );
|
421 |
|
|
assign inst_iorlw = (inst_reg[13:8] == 6'b111000 );
|
422 |
|
|
assign inst_andlw = (inst_reg[13:8] == 6'b111001 );
|
423 |
|
|
assign inst_xorlw = (inst_reg[13:8] == 6'b111010 );
|
424 |
|
|
assign inst_subwf = (inst_reg[13:8] == 6'b000010 );
|
425 |
|
|
assign inst_decf = (inst_reg[13:8] == 6'b000011 );
|
426 |
|
|
assign inst_iorwf = (inst_reg[13:8] == 6'b000100 );
|
427 |
|
|
assign inst_andwf = (inst_reg[13:8] == 6'b000101 );
|
428 |
|
|
assign inst_xorwf = (inst_reg[13:8] == 6'b000110 );
|
429 |
|
|
assign inst_addwf = (inst_reg[13:8] == 6'b000111 );
|
430 |
|
|
assign inst_movf = (inst_reg[13:8] == 6'b001000 );
|
431 |
|
|
assign inst_comf = (inst_reg[13:8] == 6'b001001 );
|
432 |
|
|
assign inst_incf = (inst_reg[13:8] == 6'b001010 );
|
433 |
|
|
assign inst_decfsz = (inst_reg[13:8] == 6'b001011 );
|
434 |
|
|
assign inst_rrf = (inst_reg[13:8] == 6'b001100 );
|
435 |
|
|
assign inst_rlf = (inst_reg[13:8] == 6'b001101 );
|
436 |
|
|
assign inst_swapf = (inst_reg[13:8] == 6'b001110 );
|
437 |
|
|
assign inst_incfsz = (inst_reg[13:8] == 6'b001111 );
|
438 |
|
|
assign inst_movwf = (inst_reg[13:7] == 7'b0000001 );
|
439 |
|
|
assign inst_clrw = (inst_reg[13:7] == 7'b0000010 );
|
440 |
|
|
assign inst_clrf = (inst_reg[13:7] == 7'b0000011 );
|
441 |
|
|
assign inst_ret = (inst_reg[13:0] == 14'b00000000001000);
|
442 |
|
|
assign inst_retfie = (inst_reg[13:0] == 14'b00000000001001);
|
443 |
|
|
assign inst_sleep = (inst_reg[13:0] == 14'b00000001100011);
|
444 |
|
|
assign inst_clrwdt = (inst_reg[13:0] == 14'b00000001100100);
|
445 |
|
|
|
446 |
|
|
|
447 |
|
|
// Calculate RAM access address (see pp.19 of PIC16F84 data sheet)
|
448 |
|
|
|
449 |
|
|
// if "d"=0, indirect addressing is used, so RAM address is BANK+FSR
|
450 |
|
|
// otherwise, RAM address is BANK+"d"
|
451 |
|
|
// (see pp.19 of PIC16F84 data sheet)
|
452 |
|
|
assign ram_adr_node = (inst_reg[6:0]==0)?{status_reg[7],fsr_reg[7:0]}:
|
453 |
|
|
{status_reg[6:5],inst_reg[6:0]};
|
454 |
|
|
|
455 |
|
|
// check if this is an access to external RAM or not
|
456 |
|
|
assign addr_sram = (ram_adr_node[6:0] > 7'b0001011); //0CH-7FH,8CH-FFH
|
457 |
|
|
|
458 |
|
|
// check if this is an access to special register or not
|
459 |
|
|
// only 1 signal of the following signals will be '1'
|
460 |
|
|
assign addr_tmr0 = (ram_adr_node[7:0] == 8'b00000001); // 01H
|
461 |
|
|
assign addr_pcl = (ram_adr_node[6:0] == 7'b0000010); // 02H, 82H
|
462 |
|
|
assign addr_stat = (ram_adr_node[6:0] == 7'b0000011); // 03H, 83H
|
463 |
|
|
assign addr_fsr = (ram_adr_node[6:0] == 7'b0000100); // 04H, 84H
|
464 |
|
|
assign addr_porta = (ram_adr_node[7:0] == 8'b00000101); // 05H
|
465 |
|
|
assign addr_portb = (ram_adr_node[7:0] == 8'b00000110); // 06H
|
466 |
|
|
assign addr_pclath = (ram_adr_node[6:0] == 7'b0001010); // 0AH, 8AH
|
467 |
|
|
assign addr_intcon = (ram_adr_node[6:0] == 7'b0001011); // 0BH, 8BH
|
468 |
|
|
assign addr_option = (ram_adr_node[7:0] == 8'b10000001); // 81H
|
469 |
|
|
assign addr_trisa = (ram_adr_node[7:0] == 8'b10000101); // 85H
|
470 |
|
|
assign addr_trisb = (ram_adr_node[7:0] == 8'b10000110); // 86H
|
471 |
|
|
|
472 |
|
|
// construct bit-mask for logical operations and bit tests
|
473 |
|
|
assign mask_node = 1 << inst_reg[9:7];
|
474 |
|
|
|
475 |
|
|
// MAIN EFSM: description of register value changes in each clock cycle
|
476 |
|
|
always @(posedge clk_i)
|
477 |
|
|
begin
|
478 |
|
|
// 1. Intermediate nodes for resource sharing
|
479 |
|
|
|
480 |
|
|
// This is a long if/else chain. Consider pulling in the decoded signals
|
481 |
|
|
// addr_tmr0 etc., and using a case statement instead?
|
482 |
|
|
// 1-1. Reading RAM/data sources (see pp.13 of PIC16F84 data sheet)
|
483 |
|
|
if (addr_sram) ram_i_node <= ram_dat_i; // data from ext. SRAM
|
484 |
|
|
else if (addr_tmr0) ram_i_node <= tmr0_reg; // data from tmr0
|
485 |
|
|
else if (addr_pcl) ram_i_node <= pc_reg[7:0]; // data from pcl
|
486 |
|
|
else if (addr_stat) ram_i_node <= status_reg; // data from status
|
487 |
|
|
else if (addr_fsr) ram_i_node <= fsr_reg; // data from fsr
|
488 |
|
|
else if (addr_porta)
|
489 |
|
|
begin
|
490 |
|
|
// Logic implements a 2:1 mux for each bit [4:0] of ram_i_node
|
491 |
|
|
ram_i_node[4:0] <= (
|
492 |
|
|
(~trisa_reg[4:0] & porta_o_reg[4:0])
|
493 |
|
|
|| ( trisa_reg[4:0] & porta_i_sync_reg[4:0])
|
494 |
|
|
);
|
495 |
|
|
ram_i_node[7:5] <= 3'b0;
|
496 |
|
|
end
|
497 |
|
|
else if (addr_portb)
|
498 |
|
|
begin
|
499 |
|
|
// Logic implements a 2:1 mux for each bit [7:0] of ram_i_node
|
500 |
|
|
ram_i_node[7:0] <= (
|
501 |
|
|
(~trisb_reg[7:0] & portb_o_reg[7:0])
|
502 |
|
|
|| ( trisb_reg[7:0] & portb_i_sync_reg[7:0])
|
503 |
|
|
);
|
504 |
|
|
end
|
505 |
|
|
else if (addr_pclath) ram_i_node <= {3'b0,pclath_reg}; // pclath (5bit)
|
506 |
|
|
else if (addr_intcon) ram_i_node <= intcon_reg; // data from intcon
|
507 |
|
|
else if (addr_option) ram_i_node <= option_reg; // data from option
|
508 |
|
|
else if (addr_trisa) ram_i_node <= {3'b0,trisa_reg}; // trisa (5bit)
|
509 |
|
|
else if (addr_trisb) ram_i_node <= trisb_reg; // data from trisb
|
510 |
|
|
else ram_i_node <= 0;
|
511 |
|
|
|
512 |
|
|
|
513 |
|
|
// 1-2. PC + 1
|
514 |
|
|
inc_pc_node <= pc_reg + 1;
|
515 |
|
|
|
516 |
|
|
|
517 |
|
|
// 1-3. Adder (ALU)
|
518 |
|
|
// full 8bit-addition, with carry in/out.
|
519 |
|
|
{add_node,temp} <= {1'b0,aluinp1_reg,1'b1}
|
520 |
|
|
+ {1'b0,aluinp2_reg,c_in};
|
521 |
|
|
// lower 4bit-addition
|
522 |
|
|
{addlow_node,dtemp} <= {1'b0,aluinp1_reg[3:0],1'b1}
|
523 |
|
|
+ {1'b0,aluinp2_reg[3:0],c_in};
|
524 |
|
|
|
525 |
|
|
// 1-4. Test if aluout = 0
|
526 |
|
|
aluout_zero_node <= (aluout_reg == 0)?1:0;
|
527 |
|
|
|
528 |
|
|
// 1-5. Determine destination
|
529 |
|
|
if (intstart_reg)
|
530 |
|
|
begin
|
531 |
|
|
writew_node <= 0;
|
532 |
|
|
writeram_node <= 0;
|
533 |
|
|
end
|
534 |
|
|
else if (inst_movwf || inst_bcf || inst_bsf || inst_clrf)
|
535 |
|
|
begin
|
536 |
|
|
writew_node <= 0;
|
537 |
|
|
writeram_node <= 1;
|
538 |
|
|
end
|
539 |
|
|
else if ( inst_movlw || inst_addlw || inst_sublw || inst_andlw
|
540 |
|
|
|| inst_iorlw || inst_xorlw || inst_retlw || inst_clrw)
|
541 |
|
|
begin
|
542 |
|
|
writew_node <= 1;
|
543 |
|
|
writeram_node <= 0;
|
544 |
|
|
end
|
545 |
|
|
else if ( inst_movf || inst_swapf || inst_addwf || inst_subwf
|
546 |
|
|
|| inst_andwf || inst_iorwf || inst_xorwf || inst_decf
|
547 |
|
|
|| inst_incf || inst_rlf || inst_rrf || inst_decfsz
|
548 |
|
|
|| inst_incfsz || inst_comf)
|
549 |
|
|
begin
|
550 |
|
|
writew_node <= ~inst_reg[7]; // ("d" field of fetched instruction)
|
551 |
|
|
writeram_node <= inst_reg[7]; // ("d" field of fetched instruction)
|
552 |
|
|
end
|
553 |
|
|
else
|
554 |
|
|
begin
|
555 |
|
|
writew_node <= 0;
|
556 |
|
|
writeram_node <= 0;
|
557 |
|
|
end
|
558 |
|
|
|
559 |
|
|
// 1-6. Interrupt request (see pp.17 of PIC16F84 data sheet)
|
560 |
|
|
int_node <= intcon_reg[7] // GIE
|
561 |
|
|
&& (
|
562 |
|
|
(intcon_reg[3] && intcon_reg[0]) // RBIE,RBIF
|
563 |
|
|
|| (intcon_reg[4] && intcon_reg[1]) // INTE,INTF
|
564 |
|
|
|| (intcon_reg[5] && intcon_reg[2]) // T0IE,T0IF
|
565 |
|
|
);
|
566 |
|
|
|
567 |
|
|
// 1-7. Reset conditions
|
568 |
|
|
wdt_rst_node <= wdt_full_sync_reg[1] && ~wdt_full_sync_reg[2]; // WDT
|
569 |
|
|
|
570 |
|
|
// (all of reset triggers)
|
571 |
|
|
if (~poweron_sync_reg || ~mclr_sync_reg || wdt_rst_node) reset_cond <= 1;
|
572 |
|
|
else reset_cond <= 0;
|
573 |
|
|
|
574 |
|
|
// 2. EFSM body
|
575 |
|
|
case (state_reg)
|
576 |
|
|
|
577 |
|
|
// 2-1. Reset state (see pp.14 and pp.42 of PIC16F84 data sheet)
|
578 |
|
|
QRESET_PP :
|
579 |
|
|
begin
|
580 |
|
|
pc_reg <= 0; // 0
|
581 |
|
|
status_reg[7:5] <= 3'b0;
|
582 |
|
|
pclath_reg <= 0; // 0
|
583 |
|
|
intcon_reg[7:1] <= 7'b0;
|
584 |
|
|
option_reg <= -1; // Set to all ones, like vhdl (others => 1)
|
585 |
|
|
trisa_reg <= -1; // Set to all ones, like vhdl (others => 1)
|
586 |
|
|
trisb_reg <= -1; // Set to all ones, like vhdl (others => 1)
|
587 |
|
|
tmr0_reg <= 0; // (specification: don't care)
|
588 |
|
|
exec_op_reg <= 0;
|
589 |
|
|
intclr_reg <= -1; // clear int
|
590 |
|
|
intstart_reg <= 0;
|
591 |
|
|
writeram_reg <= 0;
|
592 |
|
|
sleepflag_reg <= 0;
|
593 |
|
|
|
594 |
|
|
// (set /T0 and /PD properly; see pp.42 and pp.46 of data sheet)
|
595 |
|
|
if (~poweron_sync_reg) // Power-on Reset
|
596 |
|
|
begin
|
597 |
|
|
status_reg[4] <= 1; // /T0 = 1
|
598 |
|
|
status_reg[3] <= 1; // /PD = 1
|
599 |
|
|
stack_pnt_reg <= 0; // Reset stack pointer
|
600 |
|
|
end
|
601 |
|
|
else if (~mclr_sync_reg) // MCLR reset/MCLR wake up from sleep
|
602 |
|
|
begin
|
603 |
|
|
status_reg[4] <= 1; // /T0 = 1
|
604 |
|
|
// /PD = 1 if normal reset, /PD = 0 if wake up
|
605 |
|
|
status_reg[3] <= ~sleepflag_reg;
|
606 |
|
|
end
|
607 |
|
|
else if (wdt_rst_node) // WDT reset/WDT wake up from sleep
|
608 |
|
|
begin
|
609 |
|
|
status_reg[4] <= 0; // /T0 = 0
|
610 |
|
|
// /PD = 1 if normal reset, /PD = 0 if wake up
|
611 |
|
|
status_reg[3] <= ~sleepflag_reg;
|
612 |
|
|
end
|
613 |
|
|
|
614 |
|
|
// go to Q1 state if reset signal is de-asserted
|
615 |
|
|
if (~reset_cond) state_reg <= Q1_PP;
|
616 |
|
|
|
617 |
|
|
end // End of QRESET_PP state
|
618 |
|
|
|
619 |
|
|
|
620 |
|
|
// 2-2. Q1 cycle
|
621 |
|
|
Q1_PP :
|
622 |
|
|
begin
|
623 |
|
|
// 2-2-1. Clear external interrupt registers if GIE=0
|
624 |
|
|
if (intcon_reg[7]) intclr_reg <= 0;
|
625 |
|
|
else intclr_reg <= 1; // clear interrupt
|
626 |
|
|
|
627 |
|
|
// 2-2-2. Read I/O port
|
628 |
|
|
porta_i_sync_reg <= porta_io;
|
629 |
|
|
portb_i_sync_reg <= portb_io;
|
630 |
|
|
|
631 |
|
|
// 2-2-3. Read RAM read address, if not stalled
|
632 |
|
|
if (exec_op_reg && ~intstart_reg) ram_adr_reg <= ram_adr_node;
|
633 |
|
|
|
634 |
|
|
// 2-2-4. Check increment-TMR0 request
|
635 |
|
|
if (inc_tmr_sync_reg == 2'b01) inc_tmr_hold_reg <= 1;
|
636 |
|
|
|
637 |
|
|
// 2-2-5. Goto next cycle
|
638 |
|
|
if (reset_cond) state_reg <= QRESET_PP;
|
639 |
|
|
else
|
640 |
|
|
// if in the sleep mode, wait until wake-up trigger comes
|
641 |
|
|
if (sleepflag_reg && ~intstart_reg)
|
642 |
|
|
begin
|
643 |
|
|
if (inte_sync_reg || rbint_sync_reg)
|
644 |
|
|
begin
|
645 |
|
|
// if PORT-B interrupts come, then resume execution
|
646 |
|
|
// otherwise, if WDT reset/MCLR reset comes, then goto QRESET_PP
|
647 |
|
|
sleepflag_reg <= 0;
|
648 |
|
|
state_reg <= Q2_PP;
|
649 |
|
|
end
|
650 |
|
|
end
|
651 |
|
|
// if not in sleep mode, or if stalled, continue execution
|
652 |
|
|
else state_reg <= Q2_PP;
|
653 |
|
|
end // End of Q1 state
|
654 |
|
|
|
655 |
|
|
// 2-3. Q2 cycle
|
656 |
|
|
Q2_PP :
|
657 |
|
|
begin
|
658 |
|
|
// 2-3-1. Read data-RAM and substitute source values to alu-input regs
|
659 |
|
|
if (exec_op_reg && ~intstart_reg) // if NOT STALLED
|
660 |
|
|
begin
|
661 |
|
|
// 2-3-1-1. Set aluinp1 register (source #1)
|
662 |
|
|
if ( inst_movf || inst_swapf || inst_addwf || inst_subwf
|
663 |
|
|
|| inst_andwf || inst_iorwf || inst_xorwf || inst_decf
|
664 |
|
|
|| inst_incf || inst_rlf || inst_rrf || inst_bcf
|
665 |
|
|
|| inst_bsf || inst_btfsc || inst_btfss || inst_decfsz
|
666 |
|
|
|| inst_incfsz || inst_comf)
|
667 |
|
|
|
668 |
|
|
aluinp1_reg <= ram_i_node; // RAM/Special registers
|
669 |
|
|
else
|
670 |
|
|
if ( inst_movlw || inst_addlw || inst_sublw || inst_andlw
|
671 |
|
|
|| inst_iorlw || inst_xorlw || inst_retlw)
|
672 |
|
|
|
673 |
|
|
aluinp1_reg <= inst_reg[7:0]; // Immediate value ("k")
|
674 |
|
|
else
|
675 |
|
|
if ( inst_clrf || inst_clrw) aluinp1_reg <= 0; // 0
|
676 |
|
|
else aluinp1_reg <= w_reg; // W register
|
677 |
|
|
|
678 |
|
|
// 2-3-1-2. Set aluinp2 register (source #2)
|
679 |
|
|
if (inst_decf || inst_decfsz) aluinp2_reg <= -1; // for decr.
|
680 |
|
|
else if (inst_incf || inst_incfsz) aluinp2_reg <= 1; // for incr.
|
681 |
|
|
// -1 * W register (for subtract)
|
682 |
|
|
else if (inst_sublw || inst_subwf) aluinp2_reg <= ~w_reg + 1;
|
683 |
|
|
// operation of BCF: AND with inverted mask ("1..101..1")
|
684 |
|
|
// mask for BCF: value of only one position is 0
|
685 |
|
|
else if (inst_bcf) aluinp2_reg <= ~mask_node;
|
686 |
|
|
// operation of BSF: OR with mask_node ("0..010..0")
|
687 |
|
|
// operation of FSC and FSS: AND with mask_node, compare to 0
|
688 |
|
|
else if (inst_btfsc || inst_btfss || inst_bsf)
|
689 |
|
|
aluinp2_reg <= mask_node;
|
690 |
|
|
else aluinp2_reg <= w_reg; // W register
|
691 |
|
|
|
692 |
|
|
// 2-3-1-3. Set stack pointer register (pop stack)
|
693 |
|
|
if (inst_ret || inst_retlw || inst_retfie)
|
694 |
|
|
stack_pnt_reg <= stack_pnt_reg - 1; // cycles 3,2,1,0,7,6...
|
695 |
|
|
|
696 |
|
|
// 2-3-1-4. Set ram_adr register (set RAM write address)
|
697 |
|
|
ram_adr_reg <= ram_adr_node; // RAM write address
|
698 |
|
|
end
|
699 |
|
|
|
700 |
|
|
// 2-3-2. Change clock output
|
701 |
|
|
clk_o_reg <= 1;
|
702 |
|
|
|
703 |
|
|
// 2-3-3. Check increment-TMR0 request
|
704 |
|
|
if (inc_tmr_sync_reg == 2'b01) inc_tmr_hold_reg <= 1;
|
705 |
|
|
|
706 |
|
|
// 2-3-4. Goto next cycle
|
707 |
|
|
if (reset_cond) state_reg <= QRESET_PP;
|
708 |
|
|
else state_reg <= Q3_PP;
|
709 |
|
|
end // End of Q2 state
|
710 |
|
|
|
711 |
|
|
// 2-4. Q3 cycle
|
712 |
|
|
Q3_PP :
|
713 |
|
|
begin
|
714 |
|
|
// 2-4-1. Calculation and store result into alu-output register
|
715 |
|
|
if (exec_op_reg && ~intstart_reg) // if NOT STALLED
|
716 |
|
|
begin
|
717 |
|
|
// 2-4-1-1. Set aluout register
|
718 |
|
|
// Rotate left
|
719 |
|
|
if (inst_rlf)
|
720 |
|
|
aluout_reg <= {aluinp1_reg[6:0],status_reg[0]};
|
721 |
|
|
// Rotate right
|
722 |
|
|
else if (inst_rrf)
|
723 |
|
|
aluout_reg <= {status_reg[0],aluinp1_reg[7:1]};
|
724 |
|
|
// Swap nibbles
|
725 |
|
|
else if (inst_swapf)
|
726 |
|
|
aluout_reg <= {aluinp1_reg[3:0],aluinp1_reg[7:4]};
|
727 |
|
|
// Logical inversion
|
728 |
|
|
else if (inst_comf)
|
729 |
|
|
aluout_reg <= ~aluinp1_reg;
|
730 |
|
|
// Logical AND, bit clear/bit test
|
731 |
|
|
else if ( inst_andlw || inst_andwf || inst_bcf || inst_btfsc
|
732 |
|
|
|| inst_btfss)
|
733 |
|
|
aluout_reg <= (aluinp1_reg & aluinp2_reg);
|
734 |
|
|
// Logical OR, bit set
|
735 |
|
|
else if (inst_bsf || inst_iorlw || inst_iorwf)
|
736 |
|
|
aluout_reg <= (aluinp1_reg | aluinp2_reg);
|
737 |
|
|
// Logical XOR
|
738 |
|
|
else if (inst_xorlw || inst_xorwf)
|
739 |
|
|
aluout_reg <= (aluinp1_reg ^ aluinp2_reg);
|
740 |
|
|
// Addition, Subtraction, Increment, Decrement
|
741 |
|
|
else if ( inst_addlw || inst_addwf || inst_sublw || inst_subwf
|
742 |
|
|
|| inst_decf || inst_decfsz || inst_incf || inst_incfsz)
|
743 |
|
|
aluout_reg <= add_node[7:0];
|
744 |
|
|
// Pass through
|
745 |
|
|
else aluout_reg <= aluinp1_reg;
|
746 |
|
|
|
747 |
|
|
// 2-4-1-2. Set C flag and DC flag
|
748 |
|
|
if (inst_addlw || inst_addwf || inst_sublw || inst_subwf)
|
749 |
|
|
begin
|
750 |
|
|
status_reg[1] <= addlow_node[4]; // DC flag
|
751 |
|
|
status_reg[0] <= add_node[8]; // C flag
|
752 |
|
|
end
|
753 |
|
|
else if (inst_rlf) status_reg[0] <= aluinp1_reg[7]; // C flag
|
754 |
|
|
else if (inst_rrf) status_reg[0] <= aluinp1_reg[0]; // C flag
|
755 |
|
|
|
756 |
|
|
// 2-4-1-3. Set data-SRAM write enable (hazard-free)
|
757 |
|
|
if (writeram_node && addr_sram) writeram_reg <= 1;
|
758 |
|
|
else writeram_reg <= 0;
|
759 |
|
|
|
760 |
|
|
end
|
761 |
|
|
else writeram_reg <= 0; // If stalled
|
762 |
|
|
|
763 |
|
|
// 2-4-2. Check external interrupt and set int. flag, Incr. TMR0
|
764 |
|
|
if (~intstart_reg && intcon_reg[7]) // GIE
|
765 |
|
|
begin
|
766 |
|
|
// PORT-B0 INT
|
767 |
|
|
if (inte_sync_reg)
|
768 |
|
|
begin
|
769 |
|
|
intcon_reg[1] <= 1; // set INTF
|
770 |
|
|
intclr_reg[0] <= 1; // clear external int-registers
|
771 |
|
|
// (intrise_reg(0) and intdown_reg(0))
|
772 |
|
|
end
|
773 |
|
|
// PORT-B[4-7] INT
|
774 |
|
|
if (rbint_sync_reg)
|
775 |
|
|
begin
|
776 |
|
|
intcon_reg[0] <= 1; // set RBIF
|
777 |
|
|
intclr_reg[4:1] <= -1; // clear external int-registers
|
778 |
|
|
// (intrise_reg(4-1) and intdown_reg(4-1))
|
779 |
|
|
end
|
780 |
|
|
end
|
781 |
|
|
|
782 |
|
|
// Increment TMR0
|
783 |
|
|
if (inc_tmr_hold_reg || (inc_tmr_sync_reg == 2'b01)) // incr. trigger
|
784 |
|
|
begin
|
785 |
|
|
tmr0_reg <= tmr0_reg + 1; // increment
|
786 |
|
|
inc_tmr_hold_reg <= 0;
|
787 |
|
|
|
788 |
|
|
// if ~intstart and GIE and T0IE and timer full, then set T0IF
|
789 |
|
|
if (
|
790 |
|
|
~intstart_reg
|
791 |
|
|
&& intcon_reg[7]
|
792 |
|
|
&& intcon_reg[5]
|
793 |
|
|
&& (tmr0_reg == -1)
|
794 |
|
|
)
|
795 |
|
|
intcon_reg[2] <= 1; // set T0IF
|
796 |
|
|
end
|
797 |
|
|
|
798 |
|
|
// 2-4-3. Goto next cycle
|
799 |
|
|
if (reset_cond) state_reg <= QRESET_PP;
|
800 |
|
|
else state_reg <= Q4_PP;
|
801 |
|
|
|
802 |
|
|
end // End of Q3 state
|
803 |
|
|
|
804 |
|
|
|
805 |
|
|
// 2-5. Q4 cycle
|
806 |
|
|
Q4_PP :
|
807 |
|
|
begin
|
808 |
|
|
// 2-5-1. Fetch next program-instruction
|
809 |
|
|
inst_reg <= prog_dat_i;
|
810 |
|
|
|
811 |
|
|
if (~exec_op_reg && ~intstart_reg) // if STALLED
|
812 |
|
|
begin
|
813 |
|
|
pc_reg <= inc_pc_node; // increment PC
|
814 |
|
|
exec_op_reg <= 1; // end of stall
|
815 |
|
|
end
|
816 |
|
|
else // if NOT stalled
|
817 |
|
|
begin
|
818 |
|
|
// (note: if intstart_reg, only stack/pc-operations in this
|
819 |
|
|
// else-clause will be performed)
|
820 |
|
|
// 2-5-2. Store calculation result into destination,
|
821 |
|
|
// set PC and flags, and determine if execute next cycle.
|
822 |
|
|
|
823 |
|
|
// 2-5-2-1. Set W register, if not in stall cycle
|
824 |
|
|
// (~intstart_reg) and destination is W
|
825 |
|
|
|
826 |
|
|
// writew_node == 0 if intstart_reg...
|
827 |
|
|
if (writew_node) w_reg <= aluout_reg; // write W reg
|
828 |
|
|
|
829 |
|
|
// 2-5-2-2. Set data RAM/special registers,
|
830 |
|
|
// if not in stall cycle (~intstart_reg)
|
831 |
|
|
if (writeram_node)
|
832 |
|
|
begin
|
833 |
|
|
if (addr_stat)
|
834 |
|
|
begin
|
835 |
|
|
status_reg[7:5] <= aluout_reg[7:5]; // write IRP,RP1,RP0
|
836 |
|
|
// status(4),status(3)...unwritable, see below (/PD,/T0 part)
|
837 |
|
|
status_reg[1:0] <= aluout_reg[1:0]; // write DC,C
|
838 |
|
|
end
|
839 |
|
|
if (addr_fsr) fsr_reg <= aluout_reg; // write FSR
|
840 |
|
|
if (addr_porta) porta_o_reg <= aluout_reg[4:0]; // write PORT-A
|
841 |
|
|
if (addr_portb) portb_o_reg <= aluout_reg; // write PORT-B
|
842 |
|
|
if (addr_pclath) pclath_reg <= aluout_reg[4:0]; // write PCLATH
|
843 |
|
|
if (addr_intcon) intcon_reg[6:0] <= aluout_reg[6:0];
|
844 |
|
|
// write INTCON (except GIE)
|
845 |
|
|
// intcon(7)...see below (GIE part)
|
846 |
|
|
if (addr_option) option_reg <= aluout_reg; // write OPTION
|
847 |
|
|
if (addr_trisa) trisa_reg <= aluout_reg[4:0]; // write TRISA
|
848 |
|
|
if (addr_trisb) trisb_reg <= aluout_reg; // write TRISB
|
849 |
|
|
if (addr_tmr0) tmr0_reg <= aluout_reg; // write TMR0
|
850 |
|
|
end
|
851 |
|
|
|
852 |
|
|
// 2-5-2-3. Set/clear Z flag, if not in stall cycle (~intstart_reg)
|
853 |
|
|
if (~intstart_reg)
|
854 |
|
|
begin
|
855 |
|
|
if (addr_stat) status_reg[2] <= aluout_reg[2]; // (dest. is Z flag)
|
856 |
|
|
else if ( inst_addlw || inst_addwf || inst_andlw || inst_andwf
|
857 |
|
|
|| inst_clrf || inst_clrw || inst_comf || inst_decf
|
858 |
|
|
|| inst_incf || inst_movf || inst_sublw || inst_subwf
|
859 |
|
|
|| inst_xorlw || inst_xorwf || inst_iorlw || inst_iorwf )
|
860 |
|
|
status_reg[2] <= aluout_zero_node; // Z=1 if result == 0
|
861 |
|
|
end
|
862 |
|
|
|
863 |
|
|
// 2-5-2-4. Set PC and determine whether to execute next cycle or not
|
864 |
|
|
// After interrupt-stall cycle ends, jump to interrupt vector
|
865 |
|
|
if (intstart_reg)
|
866 |
|
|
begin
|
867 |
|
|
pc_reg <= 4; // (interrupt vector)
|
868 |
|
|
exec_op_reg <= 0; // the next cycle is a stall cycle
|
869 |
|
|
end
|
870 |
|
|
else if (inst_ret || inst_retlw || inst_retfie) // "return" instr.
|
871 |
|
|
begin
|
872 |
|
|
pc_reg <= stack_reg[stack_pnt_reg];
|
873 |
|
|
exec_op_reg <= 0; // the next cycle is stall cycle
|
874 |
|
|
end
|
875 |
|
|
else if (inst_goto || inst_call) // "goto/call" instructions
|
876 |
|
|
begin
|
877 |
|
|
// (see pp.18 of PIC16F84 data sheet)
|
878 |
|
|
pc_reg <= {pclath_reg[4:3],inst_reg[10:0]};
|
879 |
|
|
exec_op_reg <= 0;
|
880 |
|
|
end
|
881 |
|
|
else if ( ( (inst_btfsc || inst_decfsz || inst_incfsz)
|
882 |
|
|
&& aluout_zero_node)
|
883 |
|
|
|| (inst_btfss && ~aluout_zero_node)
|
884 |
|
|
) // bit_test instrcutions
|
885 |
|
|
begin
|
886 |
|
|
pc_reg <= inc_pc_node;
|
887 |
|
|
exec_op_reg <= 0;
|
888 |
|
|
// the next cycle is stall cycle, if test conditions are met.
|
889 |
|
|
end
|
890 |
|
|
else if (writeram_node && addr_pcl) // PCL is data-destination
|
891 |
|
|
begin
|
892 |
|
|
// (see pp.18 of PIC16F84 data sheet)
|
893 |
|
|
pc_reg <= pclath_reg[4:0] & aluout_reg;
|
894 |
|
|
exec_op_reg <= 0;
|
895 |
|
|
end
|
896 |
|
|
else
|
897 |
|
|
begin
|
898 |
|
|
// this check MUST be located AFTER the above if/else sentences
|
899 |
|
|
// check if interrupt trigger comes
|
900 |
|
|
if (~int_node) pc_reg <= inc_pc_node;
|
901 |
|
|
// if not, the next instr. fetch/exec. will be performed normally
|
902 |
|
|
else pc_reg <= pc_reg;
|
903 |
|
|
// if so, value of PC must be held
|
904 |
|
|
//(will be pushed onto stack at the end of next instruction cycle)
|
905 |
|
|
exec_op_reg <= 1;
|
906 |
|
|
end
|
907 |
|
|
|
908 |
|
|
// 2-5-2-5. Push current PC value into stack, if necessary
|
909 |
|
|
if (inst_call || intstart_reg)
|
910 |
|
|
// CALL instr. or End of interrupt-stall cycle
|
911 |
|
|
begin
|
912 |
|
|
stack_reg[stack_pnt_reg] <= pc_reg; // write PC value
|
913 |
|
|
stack_pnt_reg <= stack_pnt_reg + 1; // increment stack pointer
|
914 |
|
|
end
|
915 |
|
|
|
916 |
|
|
// 2-5-2-6. Set GIE bit in intcon register (intcon_reg(7))
|
917 |
|
|
if (~intstart_reg)
|
918 |
|
|
begin
|
919 |
|
|
if (int_node) // interrupt trigger comes
|
920 |
|
|
begin
|
921 |
|
|
intcon_reg[7] <= 0; // clear GIE
|
922 |
|
|
intstart_reg <= 1; // the next cycle is interrupt-stall cycle
|
923 |
|
|
end
|
924 |
|
|
else if (inst_retfie) // "return from interrupt" instruction
|
925 |
|
|
begin
|
926 |
|
|
intcon_reg[7] <= 1;
|
927 |
|
|
intstart_reg <= 0;
|
928 |
|
|
end
|
929 |
|
|
else if (writeram_node && addr_intcon) // destination is GIE
|
930 |
|
|
begin
|
931 |
|
|
intcon_reg[7] <= aluout_reg[7];
|
932 |
|
|
intstart_reg <= 0;
|
933 |
|
|
end
|
934 |
|
|
else intstart_reg <= 0;
|
935 |
|
|
end
|
936 |
|
|
else intstart_reg <= 0;
|
937 |
|
|
|
938 |
|
|
// 2-5-2-7. Set/clear /PD and /TO flags
|
939 |
|
|
if (~intstart_reg && inst_sleep && ~wdt_rst_node )
|
940 |
|
|
// SLEEP and no interrupt trigger
|
941 |
|
|
begin
|
942 |
|
|
sleepflag_reg <= 1;
|
943 |
|
|
status_reg[4:3] <= 2'b10; // SLEEP: /T0,/PD = 1,0
|
944 |
|
|
end
|
945 |
|
|
else if (~intstart_reg && inst_clrwdt)
|
946 |
|
|
// CLRWDT
|
947 |
|
|
status_reg[4:3] <= 2'b11; // CLRWDT: /T0,/PD = 1,1
|
948 |
|
|
|
949 |
|
|
end // (if not stalled)
|
950 |
|
|
|
951 |
|
|
// 2-5-3. Clear data-SRAM write enable (hazard-free)
|
952 |
|
|
writeram_reg <= 0;
|
953 |
|
|
|
954 |
|
|
// 2-5-4. Change clock output
|
955 |
|
|
clk_o_reg <= 0;
|
956 |
|
|
|
957 |
|
|
// 2-5-5. Check increment-TMR0 request
|
958 |
|
|
if (inc_tmr_sync_reg == 2'b01) inc_tmr_hold_reg <= 1;
|
959 |
|
|
|
960 |
|
|
// 2-5-6. Goto next cycle
|
961 |
|
|
if (reset_cond) state_reg <= QRESET_PP;
|
962 |
|
|
else state_reg <= Q1_PP;
|
963 |
|
|
end // End of Q4 state
|
964 |
|
|
|
965 |
|
|
// 2-6. Illegal states (NEVER REACHED in normal execution)
|
966 |
|
|
default : state_reg <= QRESET_PP; // goto reset state
|
967 |
|
|
endcase
|
968 |
|
|
end // End of process
|
969 |
|
|
|
970 |
|
|
|
971 |
|
|
// TMR0 pre-scaler (see pp.27 of PIC16F84 data sheet)
|
972 |
|
|
// select pre-scaler
|
973 |
|
|
assign ps_clk = option_reg[5]?(t0cki_i ^ option_reg[4]):clk_o_reg;
|
974 |
|
|
// option_reg(5):T0CS
|
975 |
|
|
// option_reg(4):T0SE
|
976 |
|
|
|
977 |
|
|
// pre-scaler body
|
978 |
|
|
always @(posedge ps_clk or negedge pon_rst_n_i)
|
979 |
|
|
begin
|
980 |
|
|
if (~pon_rst_n_i)
|
981 |
|
|
begin
|
982 |
|
|
pscale_reg <= 0;
|
983 |
|
|
ps_full_reg <= 0;
|
984 |
|
|
end
|
985 |
|
|
else // Must be ps_clk rising edge...
|
986 |
|
|
begin
|
987 |
|
|
case (option_reg[2:0]) // select prescaler-full value by PS2-0
|
988 |
|
|
3'b000 : rateval <= 1;
|
989 |
|
|
3'b001 : rateval <= 3;
|
990 |
|
|
3'b010 : rateval <= 7;
|
991 |
|
|
3'b011 : rateval <= 15;
|
992 |
|
|
3'b100 : rateval <= 31;
|
993 |
|
|
3'b101 : rateval <= 63;
|
994 |
|
|
3'b110 : rateval <= 127;
|
995 |
|
|
3'b111 : rateval <= 255;
|
996 |
|
|
default: rateval <= 1;
|
997 |
|
|
endcase
|
998 |
|
|
|
999 |
|
|
if (pscale_reg >= rateval)
|
1000 |
|
|
begin
|
1001 |
|
|
pscale_reg <= 0;
|
1002 |
|
|
ps_full_reg <= 1;
|
1003 |
|
|
end
|
1004 |
|
|
else
|
1005 |
|
|
begin
|
1006 |
|
|
pscale_reg <= pscale_reg + 1;
|
1007 |
|
|
ps_full_reg <= 0;
|
1008 |
|
|
end
|
1009 |
|
|
end
|
1010 |
|
|
end //process
|
1011 |
|
|
|
1012 |
|
|
// select TMR0-increment trigger
|
1013 |
|
|
assign inc_tmr_clk = option_reg[3]?ps_clk:ps_full_reg;
|
1014 |
|
|
// option_reg(3):PSA
|
1015 |
|
|
// ps_full_reg:output of pre-scaler
|
1016 |
|
|
|
1017 |
|
|
|
1018 |
|
|
assign wdt_init = ~pon_rst_n_i || ~mclr_n_i;
|
1019 |
|
|
// WDT timer body
|
1020 |
|
|
always @(posedge wdt_clk_i or posedge wdt_init)
|
1021 |
|
|
begin
|
1022 |
|
|
if (wdt_init) // (async reset)
|
1023 |
|
|
begin
|
1024 |
|
|
wdt_reg <= 0;
|
1025 |
|
|
wdt_full_reg <= 0;
|
1026 |
|
|
wdt_clr_req_reg <= 2'b0;
|
1027 |
|
|
wdt_fullclr_req_reg <= 2'b0;
|
1028 |
|
|
end
|
1029 |
|
|
else // Must be posedge wdt_clk_i at this point...
|
1030 |
|
|
begin
|
1031 |
|
|
// synchronizers
|
1032 |
|
|
// WDT-clear request (CLRWDT/SLEEP instruction)
|
1033 |
|
|
// (do not AND with sleepflag_reg, since WDT should be
|
1034 |
|
|
// cleared at SLEEP instruction)
|
1035 |
|
|
wdt_clr_req_reg[0] <= wdt_clr_reg;
|
1036 |
|
|
wdt_clr_req_reg[1] <= wdt_clr_req_reg[0];
|
1037 |
|
|
// WDT-full-clear request (after WDT reset)
|
1038 |
|
|
wdt_fullclr_req_reg[0] <= wdt_full_clr_reg && ~sleepflag_reg;
|
1039 |
|
|
wdt_fullclr_req_reg[1] <= wdt_fullclr_req_reg[0];
|
1040 |
|
|
|
1041 |
|
|
// timer/full reg
|
1042 |
|
|
if (wdt_reg >= WDT_SIZE_PP) wdt_full_node <= 1; // (intermediate node)
|
1043 |
|
|
else wdt_full_node <= 0; // (intermediate node)
|
1044 |
|
|
|
1045 |
|
|
// wdt_reg(counter) body
|
1046 |
|
|
if ((wdt_clr_req_reg == 2'b01) || ~wdt_ena_i) wdt_reg <= 0;
|
1047 |
|
|
else if (wdt_full_node) wdt_reg <= 0;
|
1048 |
|
|
else wdt_reg <= wdt_reg + 1;
|
1049 |
|
|
|
1050 |
|
|
// wdt_full_reg(interrupt trigger) body
|
1051 |
|
|
if ((wdt_fullclr_req_reg == 2'b01) || ~wdt_ena_i) wdt_full_reg <= 0;
|
1052 |
|
|
else if (wdt_full_node) wdt_full_reg <= 1;
|
1053 |
|
|
end
|
1054 |
|
|
end // process
|
1055 |
|
|
assign wdt_clr_ack = wdt_clr_req_reg[1]; // WDT-clear ack signal to CPU
|
1056 |
|
|
assign wdt_full_o = wdt_full_reg; // WDT-full int. trigger to CPU
|
1057 |
|
|
|
1058 |
|
|
|
1059 |
|
|
// WDT controller in CPU-clock line
|
1060 |
|
|
// (handshake-interface between WDT and CPU-EFSM)
|
1061 |
|
|
always @(posedge clk_i)
|
1062 |
|
|
begin
|
1063 |
|
|
if (~poweron_sync_reg || ~mclr_sync_reg)
|
1064 |
|
|
begin
|
1065 |
|
|
wdt_clr_reg <= 0; // WDT clear request register
|
1066 |
|
|
wdt_clr_reqhold_reg <= 0; // 1 when WDT clear request comes while another
|
1067 |
|
|
// clear request is still being processed.
|
1068 |
|
|
wdt_full_clr_reg <= 0; // WDT-full clear request register
|
1069 |
|
|
end
|
1070 |
|
|
else
|
1071 |
|
|
begin
|
1072 |
|
|
// WDT-clear/hold WDT-clear request
|
1073 |
|
|
// (handshake)
|
1074 |
|
|
if (wdt_clr_reg) // still processing clear-operation
|
1075 |
|
|
// if ack comes, take down the clear request
|
1076 |
|
|
if (wdt_clr_ack_sync_reg) wdt_clr_reg <= 0;
|
1077 |
|
|
else if ( wdt_clr_reqhold_reg
|
1078 |
|
|
|| ( (state_reg == Q4_PP)
|
1079 |
|
|
&& exec_op_reg && ~intstart_reg
|
1080 |
|
|
&& (inst_clrwdt || inst_sleep)) ) // clear request comes
|
1081 |
|
|
begin
|
1082 |
|
|
if (~wdt_clr_ack_sync_reg) // confirm if ack is 0
|
1083 |
|
|
begin
|
1084 |
|
|
wdt_clr_reg <= 1;
|
1085 |
|
|
wdt_clr_reqhold_reg <= 0;
|
1086 |
|
|
end
|
1087 |
|
|
// (wait until ack becomes 0)
|
1088 |
|
|
// else wdt_clr_reqhold_reg <= 1; NOTE: This line is "never reached!"
|
1089 |
|
|
end
|
1090 |
|
|
|
1091 |
|
|
// clear WDT-full (CPU reset request)
|
1092 |
|
|
// (handshake)
|
1093 |
|
|
if (wdt_full_clr_reg) wdt_full_clr_reg <= wdt_full_sync_reg[1];
|
1094 |
|
|
end
|
1095 |
|
|
end // process
|
1096 |
|
|
|
1097 |
|
|
|
1098 |
|
|
assign intclr0 = intclr_reg[0];
|
1099 |
|
|
assign intclr1 = intclr_reg[1];
|
1100 |
|
|
assign intclr2 = intclr_reg[2];
|
1101 |
|
|
assign intclr3 = intclr_reg[3];
|
1102 |
|
|
assign intclr4 = intclr_reg[4];
|
1103 |
|
|
|
1104 |
|
|
// Detect external interrupt requests
|
1105 |
|
|
// INT0 I/F
|
1106 |
|
|
always @(posedge int0_i or posedge intclr0)
|
1107 |
|
|
begin
|
1108 |
|
|
if (intclr0) intrise_reg[0] <= 0;
|
1109 |
|
|
else intrise_reg[0] <= 1; // catch positive edge
|
1110 |
|
|
end // process
|
1111 |
|
|
|
1112 |
|
|
always @(negedge int0_i or posedge intclr0)
|
1113 |
|
|
begin
|
1114 |
|
|
if (intclr0) intdown_reg[0] <= 0;
|
1115 |
|
|
else intdown_reg[0] <= 1; // catch negative edge
|
1116 |
|
|
end // process
|
1117 |
|
|
assign rb0_int = option_reg[6]?intrise_reg[0]:intdown_reg[0];
|
1118 |
|
|
|
1119 |
|
|
// INT4 I/F
|
1120 |
|
|
always @(posedge int4_i or posedge intclr1)
|
1121 |
|
|
begin
|
1122 |
|
|
if (intclr1) intrise_reg[1] <= 0;
|
1123 |
|
|
else intrise_reg[1] <= 1; // catch positive edge
|
1124 |
|
|
end // process
|
1125 |
|
|
|
1126 |
|
|
always @(negedge int4_i or posedge intclr1)
|
1127 |
|
|
begin
|
1128 |
|
|
if (intclr1) intdown_reg[1] <= 0;
|
1129 |
|
|
else intdown_reg[1] <= 1; // catch negative edge
|
1130 |
|
|
end // process
|
1131 |
|
|
assign rb4_int = intrise_reg[1] || intdown_reg[1];
|
1132 |
|
|
|
1133 |
|
|
// INT5 I/F
|
1134 |
|
|
always @(posedge int5_i or posedge intclr2)
|
1135 |
|
|
begin
|
1136 |
|
|
if (intclr2) intrise_reg[2] <= 0;
|
1137 |
|
|
else intrise_reg[2] <= 1; // catch positive edge
|
1138 |
|
|
end // process
|
1139 |
|
|
|
1140 |
|
|
always @(negedge int5_i or posedge intclr2)
|
1141 |
|
|
begin
|
1142 |
|
|
if (intclr2) intdown_reg[2] <= 0;
|
1143 |
|
|
else intdown_reg[2] <= 1; // catch negative edge
|
1144 |
|
|
end // process
|
1145 |
|
|
assign rb5_int = intrise_reg[2] || intdown_reg[2];
|
1146 |
|
|
|
1147 |
|
|
// INT6 I/F
|
1148 |
|
|
always @(posedge int6_i or posedge intclr3)
|
1149 |
|
|
begin
|
1150 |
|
|
if (intclr3) intrise_reg[3] <= 0;
|
1151 |
|
|
else intrise_reg[3] <= 1; // catch positive edge
|
1152 |
|
|
end // process
|
1153 |
|
|
|
1154 |
|
|
always @(negedge int7_i or posedge intclr3)
|
1155 |
|
|
begin
|
1156 |
|
|
if (intclr3) intdown_reg[3] <= 0;
|
1157 |
|
|
else intdown_reg[3] <= 1; // catch negative edge
|
1158 |
|
|
end // process
|
1159 |
|
|
assign rb6_int = intrise_reg[3] || intdown_reg[3];
|
1160 |
|
|
|
1161 |
|
|
// INT7 I/F
|
1162 |
|
|
always @(posedge int7_i or posedge intclr4)
|
1163 |
|
|
begin
|
1164 |
|
|
if (intclr4) intrise_reg[4] <= 0;
|
1165 |
|
|
else intrise_reg[4] <= 1; // catch positive edge
|
1166 |
|
|
end // process
|
1167 |
|
|
|
1168 |
|
|
always @(negedge int7_i or posedge intclr4)
|
1169 |
|
|
begin
|
1170 |
|
|
if (intclr4) intdown_reg[4] <= 0;
|
1171 |
|
|
else intdown_reg[4] <= 1; // catch negative edge
|
1172 |
|
|
end // process
|
1173 |
|
|
assign rb7_int = intrise_reg[4] || intdown_reg[4];
|
1174 |
|
|
|
1175 |
|
|
|
1176 |
|
|
// Decode INT triggers
|
1177 |
|
|
// (do not AND with GIE(intcon_reg(7)), since these signals are
|
1178 |
|
|
// also used for waking up from SLEEP)
|
1179 |
|
|
assign inte = intcon_reg[4] && rb0_int; // G0IE and raw-trigger signal
|
1180 |
|
|
assign rbint = intcon_reg[3] && (rb4_int || rb5_int || rb6_int || rb7_int); // RBIE and raw-trigger signal
|
1181 |
|
|
|
1182 |
|
|
// Circuit's output signals
|
1183 |
|
|
assign prog_adr_o = pc_reg; // program ROM address
|
1184 |
|
|
assign ram_adr_o = ram_adr_reg; // data RAM address
|
1185 |
|
|
assign ram_dat_o = aluout_reg; // data RAM write data
|
1186 |
|
|
assign readram_o = (state_reg[1:0] == Q2_PP[1:0]); // data RAM read enable
|
1187 |
|
|
//(1 when state_reg = Q2_PP)
|
1188 |
|
|
assign writeram_o = writeram_reg; // data RAM write enable
|
1189 |
|
|
|
1190 |
|
|
assign porta_io = bitwise_tristate(porta_o_reg, trisa_reg); // PORT-A
|
1191 |
|
|
assign portb_io = bitwise_tristate(portb_o_reg, trisb_reg); // PORT-B
|
1192 |
|
|
assign rbpu_o = option_reg[7]; // RBPU: pull-up enable
|
1193 |
|
|
|
1194 |
|
|
assign clk_o = clk_o_reg; // clock (clk_i/4) output
|
1195 |
|
|
|
1196 |
|
|
assign powerdown_o = sleepflag_reg; // CPU clock stop indicator
|
1197 |
|
|
assign startclk_o = inte || rbint || wdt_full_reg
|
1198 |
|
|
|| ~mclr_n_i || ~pon_rst_n_i;
|
1199 |
|
|
// CPU clock start indicator
|
1200 |
|
|
|
1201 |
|
|
|
1202 |
|
|
endmodule
|
1203 |
|
|
|
1204 |
|
|
|
1205 |
|
|
//`undef STATEBIT_SIZE
|