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[/] [risc5x/] [trunk/] [alubit.vhd] - Blame information for rev 3

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Line No. Rev Author Line
1 2 mikej
--
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-- Risc5x
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-- www.OpenCores.Org - November 2001
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--
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--
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-- This library is free software; you can distribute it and/or modify it
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-- under the terms of the GNU Lesser General Public License as published
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-- by the Free Software Foundation; either version 2.1 of the License, or
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-- (at your option) any later version.
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--
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-- This library is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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-- See the GNU Lesser General Public License for more details.
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--
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-- A RISC CPU core.
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--
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-- (c) Mike Johnson 2001. All Rights Reserved.
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-- mikej@opencores.org for support or any other issues.
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--
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-- Revision list
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--
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-- version 1.0 initial opencores release
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--
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_unsigned.all;
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entity ALUBIT is
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  generic (
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    WIDTH         : in  natural := 8
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    );
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  port (
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    A             : in  std_logic_vector(WIDTH-1 downto 0);
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    B             : in  std_logic_vector(WIDTH-1 downto 0);
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    OP            : in  std_logic_vector(1 downto 0);
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    DOUT          : out std_logic_vector(WIDTH-1 downto 0)
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    );
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end;
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--
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-- USE THIS ARCHITECTURE FOR XILINX
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--
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use work.pkg_xilinx_prims.all;
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_unsigned.all;
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architecture VIRTEX of ALUBIT is
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  function loc(i : integer) return integer is
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  begin
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    return (((WIDTH+1)/2)-1) - i/2;
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  end loc;
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begin -- architecture
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  ram_bit : for i in 0 to WIDTH-1 generate
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  attribute RLOC of u_lut  : label is "R" & integer'image(loc(i)) & "C0.S1";
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  attribute INIT of u_lut : label is "56E8";
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  begin
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    u_lut:  LUT4
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      --pragma translate_off
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      generic map (
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        INIT => str2slv(u_lut'INIT)
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        )
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      --pragma translate_on
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      port map (
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        I0 => A(i),
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        I1 => B(i),
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        I2 => OP(0),
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        I3 => OP(1),
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        O  => DOUT(i));
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  end generate;
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end VIRTEX;
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--pragma translate_off
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_arith.all;
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  use ieee.std_logic_unsigned.all;
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architecture RTL of ALUBIT is
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begin -- architecture
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  p_bit_comb : process(A,B,OP)
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  begin
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    DOUT <= (others => '0');
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    case OP is
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      when "00" => DOUT <= (A and B);
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      when "01" => DOUT <= (A  or B);
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      when "10" => DOUT <= (A xor B);
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      when "11" => DOUT <= (  not A);
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      when others => null;
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    end case;
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  end process;
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end RTL;
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--pragma translate_on
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