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mikej |
--
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-- Risc5x
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-- www.OpenCores.Org - November 2001
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--
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--
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-- This library is free software; you can distribute it and/or modify it
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-- under the terms of the GNU Lesser General Public License as published
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-- by the Free Software Foundation; either version 2.1 of the License, or
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-- (at your option) any later version.
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--
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-- This library is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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-- See the GNU Lesser General Public License for more details.
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--
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-- A RISC CPU core.
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--
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-- (c) Mike Johnson 2001. All Rights Reserved.
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-- mikej@opencores.org for support or any other issues.
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--
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-- Revision list
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--
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-- version 1.1 bug fix: Used wrong bank select bits in direct addressing mode
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-- INDF register returns 0 when indirectly read
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-- FSR bit 8 always set
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-- (cpu.vhd file changed)
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--
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-- version 1.0 initial opencores release
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--
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Risc5x is a small RISC CPU written in VHDL that is compatible with the 12 bit
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opcode PIC family. Single cycle operation normally, two cycles when the program
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counter is modified. Clock speeds of over 40Mhz are possible when using the
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Xilinx Virtex optimisations.
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This program ( hexconv.cpp ) may be used to read in a .HEX program file
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and outputs directives to the Xilinx build tools to initialise the program
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ram correctly.
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Usage :
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hexconv sourcefile.hex outputs to screen
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hexconv sourcefile.hex > temp.ucf outputs to file temp.ucf
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this will generate 16 x 6 statements like this :
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INST PRAMS_0_INST INIT_00 = 00000000000000000000000000000000000000000000000000000000E9A7B9E4;
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copy these to your RISC5X_XIL.UCF file. Job done.
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The program source has a commented out section which will produce "attribute
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init" statements which may be used in the VHDL code directly. Replace the prams
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generate in RISC5X_XIL.vhd with the following. The advantage of this technique
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is you can see the correct init's in the EDIF file, and if you have a block ram
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simulation model that you can pass INIT generics to, then you can simulate it.
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prams : if true generate
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attribute INIT_00 of inst0 : label is "00000000000000000000000000000000000000000000000000000000E9A7B9E4";
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begin
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inst0 : ramb4_s2_s2
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port map (
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dob => pdata(1 downto 0),
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dib => "00",
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doa => pram_dout(1 downto 0),
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dia => pram_din(1 downto 0),
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);
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inst1 : ramb4_s2_s2
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port map (
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dob => pdata(3 downto 2),
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doa => pram_dout(3 downto 2),
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dia => pram_din(3 downto 2),
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);
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end generate;
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Legal Stuff
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This core is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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You are responsible for any legal issues arising from the use of this core.
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The source files may be used and distributed without restriction provided that
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all copyright statements are not removed from the files and that any derivative
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work contains the original copyright notices and the associated disclaimer.
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PIC is a trademark of Microchip Technology Inc.
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Any questions or interest in customisation /locked / other cores (16x8x?) etc
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feel free to mail.
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mikej@opencores.org
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Cheers
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Mike.
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