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[/] [risc5x/] [trunk/] [pkg_prims.vhd] - Blame information for rev 5

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Line No. Rev Author Line
1 2 mikej 
--
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-- Risc5x
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-- www.OpenCores.Org - November 2001
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--
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--
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-- This library is free software; you can distribute it and/or modify it
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-- under the terms of the GNU Lesser General Public License as published
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-- by the Free Software Foundation; either version 2.1 of the License, or
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-- (at your option) any later version.
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--
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-- This library is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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-- See the GNU Lesser General Public License for more details.
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--
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-- A RISC CPU core.
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--
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-- (c) Mike Johnson 2001. All Rights Reserved.
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-- mikej@opencores.org for support or any other issues.
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--
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-- Revision list
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--
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-- version 1.0 initial opencores release
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--
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library ieee;
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  use ieee.std_logic_1164.all;
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package pkg_prims is
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  component MUX8
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    generic (
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      WIDTH         : in  natural;
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      OP_REG        : in  boolean
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      );
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    port (
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      DIN7          : in  std_logic_vector(WIDTH-1 downto 0);
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      DIN6          : in  std_logic_vector(WIDTH-1 downto 0);
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      DIN5          : in  std_logic_vector(WIDTH-1 downto 0);
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      DIN4          : in  std_logic_vector(WIDTH-1 downto 0);
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      DIN3          : in  std_logic_vector(WIDTH-1 downto 0);
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      DIN2          : in  std_logic_vector(WIDTH-1 downto 0);
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      DIN1          : in  std_logic_vector(WIDTH-1 downto 0);
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      DIN0          : in  std_logic_vector(WIDTH-1 downto 0);
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      SEL           : in  std_logic_vector(2 downto 0);
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      ENA           : in  std_logic;
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      CLK           : in  std_logic;
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      DOUT          : out std_logic_vector(WIDTH-1 downto 0)
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      );
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  end component;
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  component MUX4
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    generic (
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      WIDTH         : in  natural;
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      SLICE         : in  natural;
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      OP_REG        : in  boolean
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      );
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    port (
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      DIN3          : in  std_logic_vector(WIDTH-1 downto 0);
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      DIN2          : in  std_logic_vector(WIDTH-1 downto 0);
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      DIN1          : in  std_logic_vector(WIDTH-1 downto 0);
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      DIN0          : in  std_logic_vector(WIDTH-1 downto 0);
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      SEL           : in  std_logic_vector(1 downto 0);
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      ENA           : in  std_logic;
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      CLK           : in  std_logic;
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      DOUT          : out std_logic_vector(WIDTH-1 downto 0)
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      );
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  end component;
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  component MUX2
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    generic (
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      WIDTH         : in  natural;
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      SLICE         : in  natural;
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      OP_REG        : in  boolean
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      );
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    port (
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      DIN1          : in  std_logic_vector(WIDTH-1 downto 0);
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      DIN0          : in  std_logic_vector(WIDTH-1 downto 0);
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      SEL           : in  std_logic;
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      ENA           : in  std_logic;
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      CLK           : in  std_logic;
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      DOUT          : out std_logic_vector(WIDTH-1 downto 0)
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      );
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  end component;
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  component MUX2_ADD_REG
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    generic (
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      WIDTH         : in  natural
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      );
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    port (
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      ADD_VAL       : in  std_logic_vector(WIDTH-1 downto 0);
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      LOAD_VAL      : in  std_logic_vector(WIDTH-1 downto 0);
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      ADD           : in  std_logic;
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      PRESET        : in  std_logic; -- async
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      ENA           : in  std_logic;
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      CLK           : in  std_logic;
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      DOUT          : out std_logic_vector(WIDTH-1 downto 0);
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      REG_DOUT      : out std_logic_vector(WIDTH-1 downto 0)
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      );
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  end component;
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  component ADD_SUB
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    generic (
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      WIDTH         : in  natural
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      );
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    port (
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      A             : in  std_logic_vector(WIDTH-1 downto 0);
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      B             : in  std_logic_vector(WIDTH-1 downto 0);
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      ADD_OR_SUB    : in  std_logic; -- high for DOUT <= A +/- B, low for DOUT <= A
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      DO_SUB        : in  std_logic; -- high for DOUT <= A   - B, low for DOUT <= A + B
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      CARRY_OUT     : out std_logic_vector(WIDTH-1 downto 0);
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      DOUT          : out std_logic_vector(WIDTH-1 downto 0)
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      );
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  end component;
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  component ALUBIT
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    generic (
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      WIDTH         : in  natural
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      );
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    port (
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      A             : in  std_logic_vector(WIDTH-1 downto 0);
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      B             : in  std_logic_vector(WIDTH-1 downto 0);
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      OP            : in  std_logic_vector(1 downto 0);
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      DOUT          : out std_logic_vector(WIDTH-1 downto 0)
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      );
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  end component;
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end;

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