Subversion Repositories risc5x

#--

#-- Risc5x

#-- www.OpenCores.Org - November 2001

#--

#--

#-- This library is free software; you can distribute it and/or modify it

#-- under the terms of the GNU Lesser General Public License as published

#-- by the Free Software Foundation; either version 2.1 of the License, or

#-- (at your option) any later version.

#--

#-- This library is distributed in the hope that it will be useful, but

#-- WITHOUT ANY WARRANTY; without even the implied warranty of

#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

#-- See the GNU Lesser General Public License for more details.

#--

#-- A RISC CPU core.

#--

#-- (c) Mike Johnson 2001. All Rights Reserved.

#-- mikej@opencores.org for support or any other issues.

#--

#-- Revision list

#--

#-- version 1.0 initial opencores release

#--

CONFIG PART = XCV300E-FG456-8 ;

NET CLK          TNM_NET = clk_cpu;

TIMESPEC TS1 =PERIOD:clk_cpu : 25 ns;

TIMESPEC TS11=FROM:PADS:TO:FFS : 8ns;

TIMESPEC TS12=FROM:FFS:TO:PADS : 8ns;

AREA_GROUP RISC_GRP RANGE = CLB_R20C1:CLB_R32C10 ;

INST U0 AREA_GROUP = RISC_GRP ;

INST U0/PC_MUX2_ADD_REG RLOC_ORIGIN=R27C1;

INST U0/PC_LOAD_MUX     RLOC_ORIGIN=R22C1;

INST U0/FILEADDR_MUX    RLOC_ORIGIN=R26C2;

INST U0/U_REGS          RLOC_ORIGIN=R25C2;

INST U0/SBUS_MUXA       RLOC_ORIGIN=R25C6;

INST U0/SBUS_MUXB       RLOC_ORIGIN=R25C7;

INST U0/ALUA_MUX        RLOC_ORIGIN=R25C8;

INST U0/ALUB_MUX        RLOC_ORIGIN=R25C8;

INST U0/U_ALU/U_ADD_SUB RLOC_ORIGIN=R25C9;

INST U0/U_ALU/U_ALUBIT  RLOC_ORIGIN=R29C9;

INST U0/U_ALU/U_MUX4    RLOC_ORIGIN=R24C9;