OpenCores
URL https://opencores.org/ocsvn/riscompatible/riscompatible/trunk

Subversion Repositories riscompatible

[/] [riscompatible/] [trunk/] [bench/] [riscompatible_tb.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 borin
-------------------------------------------------------------------------------------------------------------------
2
library ieee;
3
use ieee.std_logic_1164.all;
4
use ieee.std_logic_signed.all;
5
use ieee.std_logic_arith.all;
6
use work.riscompatible_package.all;
7
-------------------------------------------------------------------------------------------------------------------
8
entity riscompatible_tb is
9
end riscompatible_tb;
10
-------------------------------------------------------------------------------------------------------------------
11
architecture behavioral of riscompatible_tb is
12
    constant C_NumBitsProgramMemory  : Natural:=14;
13
    constant C_NumBitsDataMemory     : Natural:=7;
14
    constant C_NumBitsRegBank        : natural:=5;
15
    constant C_NumBitsInputPorts     : natural:=2;
16
    constant C_NumBitsOutputPorts    : natural:=2;
17
    component riscompatible is
18
        generic
19
        (
20
            NumBitsProgramMemory : Natural:=5;
21
            NumBitsDataMemory    : Natural:=5;
22
            NumBitsRegBank       : natural:=5;
23
            NumBitsInputPorts    : natural:=2;
24
            NumBitsOutputPorts   : natural:=2
25
        );
26
        port
27
        (
28
            Clk_I         : in  std_logic;
29
            Reset_I       : in  std_logic;
30
            Int_I         : in  std_logic;
31
            IntAck_O      : out std_logic;
32
            InputPorts_I  : in  std_logic_vector(NumBitsInputPorts-1 downto 0);
33
            OutputPorts_O : out std_logic_vector(NumBitsOutputPorts-1 downto 0)
34
        );
35
    end component;
36
    signal Clk_W         : std_logic;
37
    signal Reset_W       : std_logic;
38
    signal Int_W         : std_logic;
39
    signal IntAck_W      : std_logic;
40
    signal InputPorts_W  : std_logic_vector(C_NumBitsInputPorts-1 downto 0):="10";
41
    signal OutputPorts_W : std_logic_vector(C_NumBitsOutputPorts-1 downto 0);
42
begin
43
---------------------------------------------
44
-- Clock Generation
45
---------------------------------------------
46
process
47
begin
48
    Clk_W <= '1';
49
    wait for 10 ns;
50
    Clk_W <= '0';
51
    wait for 10 ns;
52
end process;
53
 
54
---------------------------------------------
55
-- Reset Generation
56
---------------------------------------------
57
process
58
begin
59
    Reset_W <= '1';
60
    wait for 20 ns;
61
    Reset_W <= '0';
62
    wait;
63
end process;
64
 
65
---------------------------------------------
66
-- Interruption Generation
67
---------------------------------------------
68
process
69
begin
70
    Int_W <= '0';
71
    wait for 1 us;
72
    Int_W <= '1';
73
    wait for 500 ns;
74
    Int_W <= '0';
75
    wait;
76
end process;
77
 
78
---------------------------------------------
79
-- Risco Instance
80
---------------------------------------------
81
Riscompatible1: riscompatible
82
    generic map
83
    (
84
        NumBitsProgramMemory  => C_NumBitsProgramMemory,
85
        NumBitsDataMemory     => C_NumBitsDataMemory,
86
        NumBitsRegBank        => C_NumBitsRegBank,
87
        NumBitsInputPorts     => C_NumBitsInputPorts,
88
        NumBitsOutputPorts    => C_NumBitsOutputPorts
89
    )
90
    port map
91
    (
92
        Clk_I         => Clk_W,
93
        Reset_I       => Reset_W,
94
        Int_I         => Int_W,
95
        IntAck_O      => IntAck_W,
96
        InputPorts_I  => InputPorts_W,
97
        OutputPorts_O => OutputPorts_W
98
    );
99
end behavioral;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.