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borin |
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.riscompatible_package.all;
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use work.ud_package.all;
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entity UD is
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port
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(
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InputData_I : in TRiscoWord;
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ShiftAmount_I : in std_logic_vector(4 downto 0);
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OutputData_o : out TRiscoWord;
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Function_I : in std_logic_vector(4 downto 0);
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Cy_I : in std_logic;
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Cy_O : out std_logic
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);
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end UD;
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architecture behavioral of UD is
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signal OutputData_w : TRiscoWordPlusCarry;
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begin
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with Function_I select
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OutputData_w <=
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Cy_I & SRL_F(InputData_I,ShiftAmount_I) when C_SRL,
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Cy_I & SLL_F(InputData_I,ShiftAmount_I) when C_SLL,
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Cy_I & SRA_F(InputData_I,ShiftAmount_I) when C_SRA,
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Cy_I & SLA_F(InputData_I,ShiftAmount_I) when C_SLA,
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Cy_I & RRL_F(InputData_I,ShiftAmount_I) when C_RRL,
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Cy_I & RLL_F(InputData_I,ShiftAmount_I) when C_RLL,
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Cy_I & RRA_F(InputData_I,ShiftAmount_I) when C_RRA,
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Cy_I & RLA_F(InputData_I,ShiftAmount_I) when C_RLA,
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SRLC_F(InputData_I,ShiftAmount_I,Cy_I) when C_SRLC,
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SLLC_F(InputData_I,ShiftAmount_I,Cy_I) when C_SLLC,
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SRAC_F(InputData_I,ShiftAmount_I,Cy_I) when C_SRAC,
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SLAC_F(InputData_I,ShiftAmount_I,Cy_I) when C_SLAC,
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RRLC_F(InputData_I,ShiftAmount_I,Cy_I) when C_RRLC,
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RLLC_F(InputData_I,ShiftAmount_I,Cy_I) when C_RLLC,
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RRAC_F(InputData_I,ShiftAmount_I,Cy_I) when C_RRAC,
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RLAC_F(InputData_I,ShiftAmount_I,Cy_I) when C_RLAC,
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(others => '0') when others;
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OutputData_O <= OutputData_w(OutputData_O'high downto 0);
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Cy_O <= OutputData_w(OutputData_w'high);
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end behavioral;
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