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borin |
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.riscompatible_package.all;
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-------------------------------------------------------------------------------------------------------------------
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package ud_package is
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---------------------------------------------
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function SRLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function SRL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function SLLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function SLL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function SRAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function SRA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function SLAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function SLA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function RRLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function RRL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function RLLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function RLL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function RRAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function RRA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function RLAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function RLA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord;
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function SRLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function SRLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function SLLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function SLLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function SRACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function SRAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function SLACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function SLAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function RRLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function RRLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function RLLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function RLLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function RRACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function RRAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function RLACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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function RLAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry;
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---------------------------------------------
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end package;
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package body ud_package is
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--
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-- Estas funcoes necessitam uma validacao.
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-- Alguns casos nao estao completamente claros no texto original.
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--
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-- C - Carry
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-- S - Signal (bit 31)
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-- bn - bit n
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-- |bm -> bn| - bit m to bit n shift to right
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-- |bm <- bn| - bit m to bit n shift to left
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---------------------------------------------
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-- Shift Right Logical
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-- 0-> |b31 -> b0|
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--
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-- Generic
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function SRLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
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variable VSource1 : TRiscoWord;
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begin
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VSource1((TRiscoWord'high-to_integer(unsigned(FT2))) downto 0):=Source1(TRiscoWord'high downto to_integer(unsigned(FT2)));
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VSource1(TRiscoWord'high downto (TRiscoWord'high-to_integer(unsigned(FT2))+1)):=(others =>'0');
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return VSource1;
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end function SRLg_F;
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--
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-- Original (only 1,2,4,8,16)
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function SRL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
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variable VSource1 : TRiscoWord;
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begin
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case to_integer(unsigned(FT2)) is
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when 1 =>
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VSource1(TRiscoWord'high-1 downto 0):=Source1(TRiscoWord'high downto 1);
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VSource1(TRiscoWord'high):='0';
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when 2 =>
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VSource1(TRiscoWord'high-2 downto 0):=Source1(TRiscoWord'high downto 2);
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VSource1(TRiscoWord'high downto TRiscoWord'high-1):=(others =>'0');
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when 4 =>
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VSource1(TRiscoWord'high-4 downto 0):=Source1(TRiscoWord'high downto 4);
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VSource1(TRiscoWord'high downto TRiscoWord'high-3):=(others =>'0');
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when 8 =>
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VSource1(TRiscoWord'high-8 downto 0):=Source1(TRiscoWord'high downto 8);
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VSource1(TRiscoWord'high downto TRiscoWord'high-7):=(others =>'0');
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when others => --16
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VSource1(TRiscoWord'high-16 downto 0):=Source1(TRiscoWord'high downto 16);
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VSource1(TRiscoWord'high downto TRiscoWord'high-15):=(others =>'0');
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end case;
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return VSource1;
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end function SRL_F;
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---------------------------------------------
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-- Shift Left Logical
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-- |b31 <- b0| <-0
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--
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-- Generic
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function SLLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
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variable VSource1 : TRiscoWord;
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begin
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VSource1(TRiscoWord'high downto to_integer(unsigned(FT2))):=Source1(TRiscoWord'high-to_integer(unsigned(FT2)) downto 0);
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VSource1(to_integer(unsigned(FT2))-1 downto 0):=(others =>'0');
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return VSource1;
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end function SLLg_F;
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--
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-- Original (only 1,2,4,8,6)
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function SLL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
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variable VSource1 : TRiscoWord;
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begin
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case to_integer(unsigned(FT2)) is
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when 1 =>
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VSource1(TRiscoWord'high downto 1):=Source1(TRiscoWord'high-1 downto 0);
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VSource1(0):='0';
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when 2 =>
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VSource1(TRiscoWord'high downto 2):=Source1(TRiscoWord'high-2 downto 0);
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VSource1(1 downto 0):=(others =>'0');
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when 4 =>
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VSource1(TRiscoWord'high downto 4):=Source1(TRiscoWord'high-4 downto 0);
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VSource1(3 downto 0):=(others =>'0');
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when 8=>
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VSource1(TRiscoWord'high downto 8):=Source1(TRiscoWord'high-8 downto 0);
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VSource1(7 downto 0):=(others =>'0');
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when others => -- 16
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VSource1(TRiscoWord'high downto 16):=Source1(TRiscoWord'high-16 downto 0);
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VSource1(15 downto 0):=(others =>'0');
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end case;
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return VSource1;
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end function SLL_F;
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---------------------------------------------
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-- Shift Right Arithmetic
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-- S-> |b30 -> b0|
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--
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-- Generic
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function SRAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
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variable VSource1 : TRiscoWord;
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begin
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VSource1(TRiscoWord'high-to_integer(unsigned(FT2)) downto 0):=Source1(TRiscoWord'high downto to_integer(unsigned(FT2)));
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VSource1(TRiscoWord'high downto TRiscoWord'high-to_integer(unsigned(FT2))+1):=(others => Source1(Source1'high));
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return VSource1;
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end function SRAg_F;
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--
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-- Original (only 1,2,4,8,16)
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function SRA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
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variable VSource1 : TRiscoWord;
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begin
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case to_integer(unsigned(FT2)) is
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when 1 =>
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VSource1(TRiscoWord'high-1 downto 0):=Source1(TRiscoWord'high downto 1);
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VSource1(TRiscoWord'high):=Source1(Source1'high);
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when 2 =>
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VSource1(TRiscoWord'high-2 downto 0):=Source1(TRiscoWord'high downto 2);
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VSource1(TRiscoWord'high downto TRiscoWord'high-1):=(others =>Source1(Source1'high));
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when 4 =>
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VSource1(TRiscoWord'high-4 downto 0):=Source1(TRiscoWord'high downto 4);
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VSource1(TRiscoWord'high downto TRiscoWord'high-3):=(others =>Source1(Source1'high));
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when 8=>
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VSource1(TRiscoWord'high-8 downto 0):=Source1(TRiscoWord'high downto 8);
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VSource1(TRiscoWord'high downto TRiscoWord'high-7):=(others =>Source1(Source1'high));
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when others => -- 16
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VSource1(TRiscoWord'high-16 downto 0):=Source1(TRiscoWord'high downto 16);
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VSource1(TRiscoWord'high downto TRiscoWord'high-15):=(others =>Source1(Source1'high));
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end case;
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return VSource1;
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end function SRA_F;
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---------------------------------------------
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-- Shift Left Arithmetic
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-- S |b30 <- b0|
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--
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-- Generic
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function SLAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
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variable VSource1 : TRiscoWord;
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begin
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VSource1(TRiscoWord'high):=Source1(TRiscoWord'high);
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VSource1(TRiscoWord'high-1 downto to_integer(unsigned(FT2))):=Source1(TRiscoWord'high-to_integer(unsigned(FT2))-1 downto 0);
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VSource1(to_integer(unsigned(FT2))-1 downto 0):=(others =>'0');
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return VSource1;
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end function SLAg_F;
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--
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-- Original (only 1,2,4,8,6)
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function SLA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
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variable VSource1 : TRiscoWord;
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begin
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VSource1(TRiscoWord'high):=Source1(TRiscoWord'high);
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case to_integer(unsigned(FT2)) is
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when 1 =>
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VSource1(TRiscoWord'high-1 downto 1):=Source1(TRiscoWord'high-2 downto 0);
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VSource1(0):='0';
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when 2 =>
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VSource1(TRiscoWord'high-1 downto 2):=Source1(TRiscoWord'high-3 downto 0);
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VSource1(1 downto 0):=(others =>'0');
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when 4 =>
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VSource1(TRiscoWord'high-1 downto 4):=Source1(TRiscoWord'high-5 downto 0);
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VSource1(3 downto 0):=(others =>'0');
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when 8=>
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VSource1(TRiscoWord'high-1 downto 8):=Source1(TRiscoWord'high-9 downto 0);
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VSource1(7 downto 0):=(others =>'0');
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when others => -- 16
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VSource1(TRiscoWord'high-1 downto 16):=Source1(TRiscoWord'high-17 downto 0);
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VSource1(15 downto 0):=(others =>'0');
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end case;
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return VSource1;
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end function SLA_F;
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---------------------------------------------
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-- Rotate Right Logical
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-- b0-> |b31 -> b0|
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--
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-- Generic
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function RRLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
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variable VSource1 : TRiscoWord;
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begin
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VSource1(TRiscoWord'high-to_integer(unsigned(FT2)) downto 0):=Source1(TRiscoWord'high downto to_integer(unsigned(FT2)));
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VSource1(TRiscoWord'high downto TRiscoWord'high-to_integer(unsigned(FT2))+1):=Source1(to_integer(unsigned(FT2))-1 downto 0);
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return VSource1;
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end function RRLg_F;
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--
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-- Original (only 1,2,4,8,6)
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function RRL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
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variable VSource1 : TRiscoWord;
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begin
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case to_integer(unsigned(FT2)) is
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when 1 =>
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VSource1(TRiscoWord'high-1 downto 0):=Source1(TRiscoWord'high downto 1);
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VSource1(TRiscoWord'high):=Source1(0);
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when 2 =>
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VSource1(TRiscoWord'high-2 downto 0):=Source1(TRiscoWord'high downto 2);
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VSource1(TRiscoWord'high downto TRiscoWord'high-1):=Source1(1 downto 0);
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when 4 =>
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VSource1(TRiscoWord'high-4 downto 0):=Source1(TRiscoWord'high downto 4);
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VSource1(TRiscoWord'high downto TRiscoWord'high-3):=Source1(3 downto 0);
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when 8=>
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VSource1(TRiscoWord'high-8 downto 0):=Source1(TRiscoWord'high downto 8);
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VSource1(TRiscoWord'high downto TRiscoWord'high-7):=Source1(7 downto 0);
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when others => -- 16
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VSource1(TRiscoWord'high-16 downto 0):=Source1(TRiscoWord'high downto 16);
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VSource1(TRiscoWord'high downto TRiscoWord'high-15):=Source1(15 downto 0);
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end case;
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return VSource1;
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end function RRL_F;
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---------------------------------------------
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-- Rotate Left Logical
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-- |b31 <- b0| <-b31
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--
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-- Generic
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function RLLg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
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variable VSource1 : TRiscoWord;
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begin
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VSource1(TRiscoWord'high downto to_integer(unsigned(FT2))):=Source1(TRiscoWord'high-to_integer(unsigned(FT2)) downto 0);
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VSource1(to_integer(unsigned(FT2))-1 downto 0):=Source1(TRiscoWord'high downto TRiscoWord'high-to_integer(unsigned(FT2))+1);
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return VSource1;
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end function RLLg_F;
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--
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-- Original (only 1,2,4,8,6)
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252 |
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function RLL_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
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253 |
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variable VSource1 : TRiscoWord;
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254 |
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begin
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255 |
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case to_integer(unsigned(FT2)) is
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256 |
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when 1 =>
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VSource1(TRiscoWord'high downto 1):=Source1(TRiscoWord'high-1 downto 0);
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VSource1(0):=Source1(TRiscoWord'high);
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when 2 =>
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VSource1(TRiscoWord'high downto 2):=Source1(TRiscoWord'high-2 downto 0);
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VSource1(1 downto 0):=Source1(TRiscoWord'high downto TRiscoWord'high-1);
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when 4 =>
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VSource1(TRiscoWord'high downto 4):=Source1(TRiscoWord'high-4 downto 0);
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264 |
|
|
VSource1(3 downto 0):=Source1(TRiscoWord'high downto TRiscoWord'high-3);
|
265 |
|
|
when 8 =>
|
266 |
|
|
VSource1(TRiscoWord'high downto 8):=Source1(TRiscoWord'high-8 downto 0);
|
267 |
|
|
VSource1(7 downto 0):=Source1(TRiscoWord'high downto TRiscoWord'high-7);
|
268 |
|
|
when others => -- 16
|
269 |
|
|
VSource1(TRiscoWord'high downto 16):=Source1(TRiscoWord'high-16 downto 0);
|
270 |
|
|
VSource1(15 downto 0):=Source1(TRiscoWord'high downto TRiscoWord'high-15);
|
271 |
|
|
end case;
|
272 |
|
|
return VSource1;
|
273 |
|
|
end function RLL_F;
|
274 |
|
|
---------------------------------------------
|
275 |
|
|
-- Rotate Right Arithmetical
|
276 |
|
|
-- b0-> |b30 -> b0|
|
277 |
|
|
--
|
278 |
|
|
-- Generic
|
279 |
|
|
function RRAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
|
280 |
|
|
variable VSource1 : TRiscoWord;
|
281 |
|
|
begin
|
282 |
|
|
VSource1(TRiscoWord'high-to_integer(unsigned(FT2))-1 downto 0):=Source1(TRiscoWord'high-1 downto to_integer(unsigned(FT2)));
|
283 |
|
|
VSource1(TRiscoWord'high-1 downto TRiscoWord'high-to_integer(unsigned(FT2))):=Source1(to_integer(unsigned(FT2))-1 downto 0);
|
284 |
|
|
VSource1(TRiscoWord'high):=Source1(TRiscoWord'high);
|
285 |
|
|
return VSource1;
|
286 |
|
|
end function RRAg_F;
|
287 |
|
|
--
|
288 |
|
|
-- Original (only 1,2,4,8,6)
|
289 |
|
|
function RRA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
|
290 |
|
|
variable VSource1 : TRiscoWord;
|
291 |
|
|
begin
|
292 |
|
|
VSource1(TRiscoWord'high):=Source1(TRiscoWord'high);
|
293 |
|
|
case to_integer(unsigned(FT2)) is
|
294 |
|
|
when 1 =>
|
295 |
|
|
VSource1(TRiscoWord'high-2 downto 0):=Source1(TRiscoWord'high-1 downto 1);
|
296 |
|
|
VSource1(TRiscoWord'high-1):=Source1(0);
|
297 |
|
|
when 2 =>
|
298 |
|
|
VSource1(TRiscoWord'high-3 downto 0):=Source1(TRiscoWord'high-1 downto 2);
|
299 |
|
|
VSource1(TRiscoWord'high-1 downto TRiscoWord'high-2):=Source1(1 downto 0);
|
300 |
|
|
when 4 =>
|
301 |
|
|
VSource1(TRiscoWord'high-5 downto 0):=Source1(TRiscoWord'high-1 downto 4);
|
302 |
|
|
VSource1(TRiscoWord'high-1 downto TRiscoWord'high-4):=Source1(3 downto 0);
|
303 |
|
|
when 8=>
|
304 |
|
|
VSource1(TRiscoWord'high-9 downto 0):=Source1(TRiscoWord'high-1 downto 8);
|
305 |
|
|
VSource1(TRiscoWord'high-1 downto TRiscoWord'high-8):=Source1(7 downto 0);
|
306 |
|
|
when others => -- 16
|
307 |
|
|
VSource1(TRiscoWord'high-17 downto 0):=Source1(TRiscoWord'high-1 downto 16);
|
308 |
|
|
VSource1(TRiscoWord'high-1 downto TRiscoWord'high-16):=Source1(15 downto 0);
|
309 |
|
|
end case;
|
310 |
|
|
return VSource1;
|
311 |
|
|
end function RRA_F;
|
312 |
|
|
---------------------------------------------
|
313 |
|
|
-- Rotate Left Arithmetical
|
314 |
|
|
-- |b31 <- b0| <-b31
|
315 |
|
|
--
|
316 |
|
|
-- Generic
|
317 |
|
|
function RLAg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
|
318 |
|
|
variable VSource1 : TRiscoWord;
|
319 |
|
|
begin
|
320 |
|
|
VSource1(TRiscoWord'high-1 downto to_integer(unsigned(FT2))):=Source1(TRiscoWord'high-to_integer(unsigned(FT2))-1 downto 0);
|
321 |
|
|
VSource1(to_integer(unsigned(FT2))-1 downto 0):=Source1(TRiscoWord'high-1 downto TRiscoWord'high-to_integer(unsigned(FT2)));
|
322 |
|
|
VSource1(TRiscoWord'high):=Source1(TRiscoWord'high);
|
323 |
|
|
return VSource1;
|
324 |
|
|
end function RLAg_F;
|
325 |
|
|
--
|
326 |
|
|
-- Original (only 1,2,4,8,6)
|
327 |
|
|
function RLA_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0)) return TRiscoWord is
|
328 |
|
|
variable VSource1 : TRiscoWord;
|
329 |
|
|
begin
|
330 |
|
|
VSource1(TRiscoWord'high):=Source1(TRiscoWord'high);
|
331 |
|
|
case to_integer(unsigned(FT2)) is
|
332 |
|
|
when 1 =>
|
333 |
|
|
VSource1(TRiscoWord'high-1 downto 1):=Source1(TRiscoWord'high-2 downto 0);
|
334 |
|
|
VSource1(0):=Source1(TRiscoWord'high-1);
|
335 |
|
|
when 2 =>
|
336 |
|
|
VSource1(TRiscoWord'high-1 downto 2):=Source1(TRiscoWord'high-3 downto 0);
|
337 |
|
|
VSource1(1 downto 0):=Source1(TRiscoWord'high-1 downto TRiscoWord'high-2);
|
338 |
|
|
when 4 =>
|
339 |
|
|
VSource1(TRiscoWord'high-1 downto 4):=Source1(TRiscoWord'high-5 downto 0);
|
340 |
|
|
VSource1(3 downto 0):=Source1(TRiscoWord'high-1 downto TRiscoWord'high-4);
|
341 |
|
|
when 8=>
|
342 |
|
|
VSource1(TRiscoWord'high-1 downto 8):=Source1(TRiscoWord'high-9 downto 0);
|
343 |
|
|
VSource1(7 downto 0):=Source1(TRiscoWord'high-1 downto TRiscoWord'high-8);
|
344 |
|
|
when others => -- 16
|
345 |
|
|
VSource1(TRiscoWord'high-1 downto 16):=Source1(TRiscoWord'high-17 downto 0);
|
346 |
|
|
VSource1(15 downto 0):=Source1(TRiscoWord'high-1 downto TRiscoWord'high-16);
|
347 |
|
|
end case;
|
348 |
|
|
return VSource1;
|
349 |
|
|
end function RLA_F;
|
350 |
|
|
|
351 |
|
|
---------------------------------------------
|
352 |
|
|
-- Shift Right Logical Carry
|
353 |
|
|
-- 0-> C-> |b31 -> b0|
|
354 |
|
|
-- Diss. Risco, 3.4.1 d) O carry comporta-se como bit 32
|
355 |
|
|
-- Generic
|
356 |
|
|
function SRLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
357 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
358 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
359 |
|
|
begin
|
360 |
|
|
VSource1(VSource1'high):=Cy;
|
361 |
|
|
VSource1(VSource1'high-1 downto 0):=Source1;
|
362 |
|
|
VSource2((VSource2'high-to_integer(unsigned(FT2))) downto 0):=VSource1(VSource1'high downto to_integer(unsigned(FT2)));
|
363 |
|
|
VSource2(VSource2'high downto (VSource2'high-to_integer(unsigned(FT2))+1)):=(others => '0');
|
364 |
|
|
return VSource2;
|
365 |
|
|
end function SRLCg_F;
|
366 |
|
|
--
|
367 |
|
|
-- Original (only 1,2,4,8,16)
|
368 |
|
|
function SRLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
369 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
370 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
371 |
|
|
begin
|
372 |
|
|
VSource1(VSource1'high):=Cy;
|
373 |
|
|
VSource1(VSource1'high-1 downto 0):=Source1;
|
374 |
|
|
case to_integer(unsigned(FT2)) is
|
375 |
|
|
when 1 =>
|
376 |
|
|
VSource2(VSource2'high-1 downto 0):=VSource1(VSource1'high downto 1);
|
377 |
|
|
VSource2(VSource2'high):='0';
|
378 |
|
|
when 2 =>
|
379 |
|
|
VSource2(VSource2'high-2 downto 0):=VSource1(VSource1'high downto 2);
|
380 |
|
|
VSource2(VSource2'high downto VSource2'high-1):=(others => '0');
|
381 |
|
|
when 4 =>
|
382 |
|
|
VSource2(VSource2'high-4 downto 0):=VSource1(VSource1'high downto 4);
|
383 |
|
|
VSource2(VSource2'high downto VSource2'high-3):=(others => '0');
|
384 |
|
|
when 8 =>
|
385 |
|
|
VSource2(VSource2'high-8 downto 0):=VSource1(VSource1'high downto 8);
|
386 |
|
|
VSource2(VSource2'high downto VSource2'high-7):=(others => '0');
|
387 |
|
|
when others => --16
|
388 |
|
|
VSource2(VSource2'high-16 downto 0):=VSource1(VSource1'high downto 16);
|
389 |
|
|
VSource2(VSource2'high downto VSource2'high-15):=(others => '0');
|
390 |
|
|
end case;
|
391 |
|
|
return VSource2;
|
392 |
|
|
end function SRLC_F;
|
393 |
|
|
---------------------------------------------
|
394 |
|
|
-- Shift Left Logical Carry
|
395 |
|
|
-- C <-|b31 <- b0| <-0
|
396 |
|
|
-- Diss. Risco, 3.4.1 d) O carry comporta-se como bit 32
|
397 |
|
|
-- Generic
|
398 |
|
|
function SLLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
399 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
400 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
401 |
|
|
begin
|
402 |
|
|
VSource1(VSource1'high):=Cy;
|
403 |
|
|
VSource1(VSource1'high-1 downto 0):=Source1;
|
404 |
|
|
VSource2((VSource2'high) downto to_integer(unsigned(FT2))):=VSource1(VSource1'high-to_integer(unsigned(FT2)) downto 0);
|
405 |
|
|
VSource2((to_integer(unsigned(FT2))-1) downto 0):=(others => '0');
|
406 |
|
|
return VSource2;
|
407 |
|
|
end function SLLCg_F;
|
408 |
|
|
--
|
409 |
|
|
-- Original (only 1,2,4,8,16)
|
410 |
|
|
function SLLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
411 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
412 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
413 |
|
|
begin
|
414 |
|
|
VSource1(VSource1'high):=Cy;
|
415 |
|
|
VSource1(VSource1'high-1 downto 0):=Source1;
|
416 |
|
|
case to_integer(unsigned(FT2)) is
|
417 |
|
|
when 1 =>
|
418 |
|
|
VSource2(VSource2'high downto 1):=VSource1(VSource1'high-1 downto 0);
|
419 |
|
|
VSource2(0):='0';
|
420 |
|
|
when 2 =>
|
421 |
|
|
VSource2(VSource2'high downto 2):=VSource1(VSource1'high-2 downto 0);
|
422 |
|
|
VSource2(1 downto 0):=(others => '0');
|
423 |
|
|
when 4 =>
|
424 |
|
|
VSource2(VSource2'high downto 4):=VSource1(VSource1'high-4 downto 0);
|
425 |
|
|
VSource2(3 downto 0):=(others => '0');
|
426 |
|
|
when 8 =>
|
427 |
|
|
VSource2(VSource2'high downto 8):=VSource1(VSource1'high-8 downto 0);
|
428 |
|
|
VSource2(7 downto 0):=(others => '0');
|
429 |
|
|
when others => --16
|
430 |
|
|
VSource2(VSource2'high downto 16):=VSource1(VSource1'high-16 downto 0);
|
431 |
|
|
VSource2(15 downto 0):=(others => '0');
|
432 |
|
|
end case;
|
433 |
|
|
return VSource2;
|
434 |
|
|
end function SLLC_F;
|
435 |
|
|
---------------------------------------------
|
436 |
|
|
-- Shift Right Arithmetical Carry
|
437 |
|
|
-- 0-> C-> |b31 -> b0|
|
438 |
|
|
-- Diss. Risco, 3.4.1 d) O carry comporta-se como bit 32
|
439 |
|
|
-- Generic
|
440 |
|
|
function SRACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
441 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
442 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
443 |
|
|
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
|
444 |
|
|
begin
|
445 |
|
|
VSource1(VSource1'high):=Source1(Source1'high);
|
446 |
|
|
VSource1(VSource1'high-1):=Cy;
|
447 |
|
|
VSource1(VSource1'high-2 downto 0):=Source1(Source1'high-1 downto 0);
|
448 |
|
|
|
449 |
|
|
VSource2(VSource2'high-to_integer(unsigned(FT2))-1 downto 0):=VSource1(VSource1'high-1 downto to_integer(unsigned(FT2)));
|
450 |
|
|
VSource2(VSource2'high-1 downto VSource2'high-to_integer(unsigned(FT2))):=(others => VSource1(VSource1'high));
|
451 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
452 |
|
|
|
453 |
|
|
VSourceR:=VSource2(VSource2'high-1)&VSource2(VSource2'high)&VSource2(VSource2'high-2 downto 0);
|
454 |
|
|
return VSourceR;
|
455 |
|
|
end function SRACg_F;
|
456 |
|
|
--
|
457 |
|
|
-- Original (only 1,2,4,8,16)
|
458 |
|
|
function SRAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
459 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
460 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
461 |
|
|
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
|
462 |
|
|
begin
|
463 |
|
|
VSource1(VSource1'high):=Source1(Source1'high);
|
464 |
|
|
VSource1(VSource1'high-1):=Cy;
|
465 |
|
|
VSource1(VSource1'high-2 downto 0):=Source1(Source1'high-1 downto 0);
|
466 |
|
|
case to_integer(unsigned(FT2)) is
|
467 |
|
|
when 1 =>
|
468 |
|
|
VSource2(VSource2'high-2 downto 0):=VSource1(VSource1'high-1 downto 1);
|
469 |
|
|
VSource2(VSource2'high-1):=VSource1(VSource1'high);
|
470 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
471 |
|
|
when 2 =>
|
472 |
|
|
VSource2(VSource2'high-3 downto 0):=VSource1(VSource1'high-1 downto 2);
|
473 |
|
|
VSource2(VSource2'high-1 downto VSource2'high-2):=(others => VSource1(VSource1'high));
|
474 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
475 |
|
|
when 4 =>
|
476 |
|
|
VSource2(VSource2'high-5 downto 0):=VSource1(VSource1'high-1 downto 4);
|
477 |
|
|
VSource2(VSource2'high-1 downto VSource2'high-4):=(others => VSource1(VSource1'high));
|
478 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
479 |
|
|
when 8 =>
|
480 |
|
|
VSource2(VSource2'high-9 downto 0):=VSource1(VSource1'high-1 downto 8);
|
481 |
|
|
VSource2(VSource2'high-1 downto VSource2'high-8):=(others => VSource1(VSource1'high));
|
482 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
483 |
|
|
when others => --16
|
484 |
|
|
VSource2(VSource2'high-17 downto 0):=VSource1(VSource1'high-1 downto 16);
|
485 |
|
|
VSource2(VSource2'high-1 downto VSource2'high-16):=(others => VSource1(VSource1'high));
|
486 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
487 |
|
|
end case;
|
488 |
|
|
VSourceR:=VSource2(VSource2'high-1)&VSource2(VSource2'high)&VSource2(VSource2'high-2 downto 0);
|
489 |
|
|
return VSourceR;
|
490 |
|
|
end function SRAC_F;
|
491 |
|
|
---------------------------------------------
|
492 |
|
|
-- Shift Left Arithmetical Carry
|
493 |
|
|
-- C <-|b31 <- b0| <-0
|
494 |
|
|
-- Diss. Risco, 3.4.1 d) O carry comporta-se como bit 32
|
495 |
|
|
-- Generic
|
496 |
|
|
function SLACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
497 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
498 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
499 |
|
|
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
|
500 |
|
|
begin
|
501 |
|
|
VSource1(VSource1'high):=Source1(Source1'high);
|
502 |
|
|
VSource1(VSource1'high-1):=Cy;
|
503 |
|
|
VSource1(VSource1'high-2 downto 0):=Source1(Source1'high-1 downto 0);
|
504 |
|
|
|
505 |
|
|
VSource2(VSource2'high-1 downto to_integer(unsigned(FT2))):=VSource1(VSource1'high-1-to_integer(unsigned(FT2)) downto 0);
|
506 |
|
|
VSource2(to_integer(unsigned(FT2))-1 downto 0):=(others => '0');
|
507 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
508 |
|
|
|
509 |
|
|
VSourceR:=VSource2(VSource2'high-1)&VSource2(VSource2'high)&VSource2(VSource2'high-2 downto 0);
|
510 |
|
|
return VSourceR;
|
511 |
|
|
end function SLACg_F;
|
512 |
|
|
--
|
513 |
|
|
-- Original (only 1,2,4,8,16)
|
514 |
|
|
function SLAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
515 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
516 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
517 |
|
|
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
|
518 |
|
|
begin
|
519 |
|
|
VSource1(VSource1'high):=Source1(Source1'high);
|
520 |
|
|
VSource1(VSource1'high-1):=Cy;
|
521 |
|
|
VSource1(VSource1'high-2 downto 0):=Source1(Source1'high-1 downto 0);
|
522 |
|
|
case to_integer(unsigned(FT2)) is
|
523 |
|
|
when 1 =>
|
524 |
|
|
VSource2(VSource2'high-1 downto 1):=VSource1(VSource1'high-2 downto 0);
|
525 |
|
|
VSource2(0):='0';
|
526 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
527 |
|
|
when 2 =>
|
528 |
|
|
VSource2(VSource2'high-1 downto 2):=VSource1(VSource1'high-3 downto 0);
|
529 |
|
|
VSource2(1 downto 0):=(others => '0');
|
530 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
531 |
|
|
when 4 =>
|
532 |
|
|
VSource2(VSource2'high-1 downto 4):=VSource1(VSource1'high-5 downto 0);
|
533 |
|
|
VSource2(3 downto 0):=(others => '0');
|
534 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
535 |
|
|
when 8 =>
|
536 |
|
|
VSource2(VSource2'high-1 downto 8):=VSource1(VSource1'high-9 downto 0);
|
537 |
|
|
VSource2(7 downto 0):=(others => '0');
|
538 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
539 |
|
|
when others => --16
|
540 |
|
|
VSource2(VSource2'high-1 downto 16):=VSource1(VSource1'high-17 downto 0);
|
541 |
|
|
VSource2(15 downto 0):=(others => '0');
|
542 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
543 |
|
|
end case;
|
544 |
|
|
VSourceR:=VSource2(VSource2'high-1)&VSource2(VSource2'high)&VSource2(VSource2'high-2 downto 0);
|
545 |
|
|
return VSourceR;
|
546 |
|
|
end function SLAC_F;
|
547 |
|
|
---------------------------------------------
|
548 |
|
|
-- Rotate Right Logical through carry
|
549 |
|
|
-- C-> |b31 -> b0| -> C
|
550 |
|
|
--
|
551 |
|
|
-- Generic
|
552 |
|
|
function RRLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
553 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
554 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
555 |
|
|
begin
|
556 |
|
|
VSource1(VSource1'high):=Cy;
|
557 |
|
|
VSource1(VSource1'high-1 downto 0):=Source1;
|
558 |
|
|
VSource2(VSource2'high-to_integer(unsigned(FT2)) downto 0):=VSource1(VSource1'high downto to_integer(unsigned(FT2)));
|
559 |
|
|
VSource2(VSource2'high downto VSource2'high-to_integer(unsigned(FT2))+1):=VSource1(to_integer(unsigned(FT2))-1 downto 0);
|
560 |
|
|
return VSource2;
|
561 |
|
|
end function RRLCg_F;
|
562 |
|
|
--
|
563 |
|
|
-- Original (only 1,2,4,8,6)
|
564 |
|
|
function RRLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
565 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
566 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
567 |
|
|
begin
|
568 |
|
|
VSource1(VSource1'high):=Cy;
|
569 |
|
|
VSource1(VSource1'high-1 downto 0):=Source1;
|
570 |
|
|
case to_integer(unsigned(FT2)) is
|
571 |
|
|
when 1 =>
|
572 |
|
|
VSource2(VSource2'high-1 downto 0):=VSource1(VSource1'high downto 1);
|
573 |
|
|
VSource2(VSource2'high):=VSource1(0);
|
574 |
|
|
when 2 =>
|
575 |
|
|
VSource2(VSource2'high-2 downto 0):=VSource1(VSource1'high downto 2);
|
576 |
|
|
VSource2(VSource2'high downto VSource2'high-1):=VSource1(1 downto 0);
|
577 |
|
|
when 4 =>
|
578 |
|
|
VSource2(VSource2'high-4 downto 0):=VSource1(VSource1'high downto 4);
|
579 |
|
|
VSource2(VSource2'high downto VSource2'high-3):=VSource1(3 downto 0);
|
580 |
|
|
when 8=>
|
581 |
|
|
VSource2(VSource2'high-8 downto 0):=VSource1(VSource1'high downto 8);
|
582 |
|
|
VSource2(VSource2'high downto VSource2'high-7):=VSource1(7 downto 0);
|
583 |
|
|
when others => -- 16
|
584 |
|
|
VSource2(VSource2'high-16 downto 0):=VSource1(VSource1'high downto 16);
|
585 |
|
|
VSource2(VSource2'high downto VSource2'high-15):=VSource1(15 downto 0);
|
586 |
|
|
end case;
|
587 |
|
|
return VSource2;
|
588 |
|
|
end function RRLC_F;
|
589 |
|
|
---------------------------------------------
|
590 |
|
|
-- Rotate Left Logical through carry
|
591 |
|
|
-- C <-|b31 <- b0| <-C
|
592 |
|
|
--
|
593 |
|
|
-- Generic
|
594 |
|
|
function RLLCg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
595 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
596 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
597 |
|
|
begin
|
598 |
|
|
VSource1(VSource1'high):=Cy;
|
599 |
|
|
VSource1(VSource1'high-1 downto 0):=Source1;
|
600 |
|
|
VSource2(VSource2'high downto to_integer(unsigned(FT2))):=Source1(VSource1'high-to_integer(unsigned(FT2)) downto 0);
|
601 |
|
|
VSource2(to_integer(unsigned(FT2))-1 downto 0):=VSource1(VSource1'high downto VSource1'high-to_integer(unsigned(FT2))+1);
|
602 |
|
|
return VSource2;
|
603 |
|
|
end function RLLCg_F;
|
604 |
|
|
--
|
605 |
|
|
-- Original (only 1,2,4,8,6)
|
606 |
|
|
function RLLC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
607 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
608 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
609 |
|
|
begin
|
610 |
|
|
VSource1(VSource1'high):=Cy;
|
611 |
|
|
VSource1(VSource1'high-1 downto 0):=Source1;
|
612 |
|
|
case to_integer(unsigned(FT2)) is
|
613 |
|
|
when 1 =>
|
614 |
|
|
VSource2(VSource2'high downto 1):=Source1(VSource1'high-1 downto 0);
|
615 |
|
|
VSource2(0):=VSource1(VSource1'high);
|
616 |
|
|
when 2 =>
|
617 |
|
|
VSource2(VSource2'high downto 2):=Source1(VSource1'high-2 downto 0);
|
618 |
|
|
VSource2(1 downto 0):=VSource1(VSource2'high downto VSource1'high-1);
|
619 |
|
|
when 4 =>
|
620 |
|
|
VSource2(VSource2'high downto 4):=Source1(VSource1'high-4 downto 0);
|
621 |
|
|
VSource2(3 downto 0):=VSource1(VSource2'high downto VSource1'high-3);
|
622 |
|
|
when 8=>
|
623 |
|
|
VSource2(VSource2'high downto 8):=Source1(VSource1'high-8 downto 0);
|
624 |
|
|
VSource2(7 downto 0):=VSource1(VSource2'high downto VSource1'high-7);
|
625 |
|
|
when others => -- 16
|
626 |
|
|
VSource2(VSource2'high downto 16):=Source1(VSource1'high-16 downto 0);
|
627 |
|
|
VSource2(15 downto 0):=VSource1(VSource2'high downto VSource1'high-15);
|
628 |
|
|
end case;
|
629 |
|
|
return VSource2;
|
630 |
|
|
end function RLLC_F;
|
631 |
|
|
---------------------------------------------
|
632 |
|
|
-- Rotate Right Arithmetical through carry
|
633 |
|
|
-- C-> |b30 -> b0| -> C
|
634 |
|
|
--
|
635 |
|
|
-- Generic
|
636 |
|
|
function RRACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
637 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
638 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
639 |
|
|
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
|
640 |
|
|
begin
|
641 |
|
|
VSource1(0):=Cy;
|
642 |
|
|
VSource1(VSource1'high downto 1):=Source1;
|
643 |
|
|
|
644 |
|
|
VSource2(VSource2'high-to_integer(unsigned(FT2))-1 downto 0):=VSource1(VSource1'high-1 downto to_integer(unsigned(FT2)));
|
645 |
|
|
VSource2(VSource2'high-1 downto VSource2'high-to_integer(unsigned(FT2))):=VSource1(to_integer(unsigned(FT2))-1 downto 0);
|
646 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
647 |
|
|
VSourceR:=VSource2(0) & VSource2(VSource2'high downto 1);
|
648 |
|
|
return VSourceR;
|
649 |
|
|
end function RRACg_F;
|
650 |
|
|
--
|
651 |
|
|
-- Original (only 1,2,4,8,6)
|
652 |
|
|
function RRAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
653 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
654 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
655 |
|
|
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
|
656 |
|
|
begin
|
657 |
|
|
VSource1(0):=Cy;
|
658 |
|
|
VSource1(VSource1'high downto 1):=Source1;
|
659 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
660 |
|
|
case to_integer(unsigned(FT2)) is
|
661 |
|
|
when 1 =>
|
662 |
|
|
VSource2(VSource2'high-2 downto 0):=VSource1(VSource1'high-1 downto 1);
|
663 |
|
|
VSource2(VSource2'high-1):=VSource1(0);
|
664 |
|
|
when 2 =>
|
665 |
|
|
VSource2(VSource2'high-3 downto 0):=VSource1(VSource1'high-1 downto 2);
|
666 |
|
|
VSource2(VSource2'high-1 downto VSource2'high-2):=VSource1(1 downto 0);
|
667 |
|
|
when 4 =>
|
668 |
|
|
VSource2(VSource2'high-5 downto 0):=VSource1(VSource1'high-1 downto 4);
|
669 |
|
|
VSource2(VSource2'high-1 downto VSource2'high-4):=VSource1(3 downto 0);
|
670 |
|
|
when 8=>
|
671 |
|
|
VSource2(VSource2'high-9 downto 0):=VSource1(VSource1'high-1 downto 8);
|
672 |
|
|
VSource2(VSource2'high-1 downto VSource2'high-8):=VSource1(7 downto 0);
|
673 |
|
|
when others => -- 16
|
674 |
|
|
VSource2(VSource2'high-17 downto 0):=VSource1(VSource1'high-1 downto 16);
|
675 |
|
|
VSource2(VSource2'high-1 downto VSource2'high-16):=VSource1(15 downto 0);
|
676 |
|
|
end case;
|
677 |
|
|
VSourceR:=VSource2(0) & VSource2(VSource2'high downto 1);
|
678 |
|
|
return VSourceR;
|
679 |
|
|
end function RRAC_F;
|
680 |
|
|
---------------------------------------------
|
681 |
|
|
-- Rotate Left Arithmetical through carry
|
682 |
|
|
-- C <-|b30 <- b0| <-C
|
683 |
|
|
--
|
684 |
|
|
-- Generic
|
685 |
|
|
function RLACg_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
686 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
687 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
688 |
|
|
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
|
689 |
|
|
begin
|
690 |
|
|
VSource1(0):=Cy;
|
691 |
|
|
VSource1(VSource1'high downto 1):=Source1;
|
692 |
|
|
|
693 |
|
|
VSource2(VSource2'high-1 downto to_integer(unsigned(FT2))):=VSource1(VSource1'high-1-to_integer(unsigned(FT2)) downto 0);
|
694 |
|
|
VSource2(to_integer(unsigned(FT2))-1 downto 0):=VSource1(VSource2'high-1 downto VSource1'high-to_integer(unsigned(FT2)));
|
695 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
696 |
|
|
VSourceR:=VSource2(0) & VSource2(VSource2'high downto 1);
|
697 |
|
|
return VSourceR;
|
698 |
|
|
end function RLACg_F;
|
699 |
|
|
--
|
700 |
|
|
-- Original (only 1,2,4,8,6)
|
701 |
|
|
function RLAC_F(Source1 : TRiscoWord ; FT2 : std_logic_vector(4 downto 0) ; Cy : std_logic) return TRiscoWordPlusCarry is
|
702 |
|
|
variable VSource1 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
703 |
|
|
variable VSource2 : std_logic_vector(TRiscoWord'high+1 downto 0);
|
704 |
|
|
variable VSourceR : std_logic_vector(TRiscoWord'high+1 downto 0);
|
705 |
|
|
begin
|
706 |
|
|
VSource1(0):=Cy;
|
707 |
|
|
VSource1(VSource1'high downto 1):=Source1;
|
708 |
|
|
VSource2(VSource2'high):=VSource1(VSource1'high);
|
709 |
|
|
case to_integer(unsigned(FT2)) is
|
710 |
|
|
when 1 =>
|
711 |
|
|
VSource2(VSource2'high-1 downto 1):=VSource1(VSource1'high-2 downto 0);
|
712 |
|
|
VSource2(0):=VSource1(VSource2'high-1);
|
713 |
|
|
when 2 =>
|
714 |
|
|
VSource2(VSource2'high-1 downto 2):=VSource1(VSource1'high-3 downto 0);
|
715 |
|
|
VSource2(1 downto 0):=VSource1(VSource2'high-1 downto VSource2'high-2);
|
716 |
|
|
when 4 =>
|
717 |
|
|
VSource2(VSource2'high-1 downto 4):=VSource1(VSource1'high-5 downto 0);
|
718 |
|
|
VSource2(3 downto 0):=VSource1(VSource2'high-1 downto VSource2'high-4);
|
719 |
|
|
when 8=>
|
720 |
|
|
VSource2(VSource2'high-1 downto 8):=VSource1(VSource1'high-9 downto 0);
|
721 |
|
|
VSource2(7 downto 0):=VSource1(VSource2'high-1 downto VSource2'high-8);
|
722 |
|
|
when others => -- 16
|
723 |
|
|
VSource2(VSource2'high-1 downto 16):=VSource1(VSource1'high-17 downto 0);
|
724 |
|
|
VSource2(15 downto 0):=VSource1(VSource2'high-1 downto VSource2'high-16);
|
725 |
|
|
end case;
|
726 |
|
|
VSourceR:=VSource2(0) & VSource2(VSource2'high downto 1);
|
727 |
|
|
return VSourceR;
|
728 |
|
|
end function RLAC_F;
|
729 |
|
|
end ud_package;
|