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[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [common/] [coreservices/] [icpu_hc08.h] - Blame information for rev 5

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/**
 * @file
 * @copyright  Copyright 2017 GNSS Sensor Ltd. All right reserved.
 * @author     Sergey Khabarov - sergeykhbr@gmail.com
 * @brief      CPU HC08 specific interface.
 */
 
#ifndef __DEBUGGER_COMMON_CORESERVICES_ICPU_HC08_H__
#define __DEBUGGER_COMMON_CORESERVICES_ICPU_HC08_H__
 
#include <inttypes.h>
#include <iface.h>
 
namespace debugger {
 
static const char *const IFACE_CPU_HC08 = "ICpuHC08";
 
enum ERegNames {
    Reg_A,          // 0
    Reg_HX,         // 1
    Reg_SP,         // 2
    Reg_CCR,        // 3
    Reg_PPAGE,      // 4
    Reg_ClkHz,      // 5
    Reg_rsrv6,      // 6
    Reg_rsrv7,
    Reg_rsrv8,
    Reg_rsrv9,
    Reg_rsrv10,
    Reg_rsrv11,
    Reg_rsrv12,
    Reg_rsrv13,
    Reg_rsrv14,
    Reg_rsrv15,
    Reg_rsrv16,
    Reg_rsrv17,
    Reg_rsrv18,
    Reg_rsrv19,
    Reg_rsrv20,
    Reg_rsrv21,
    Reg_rsrv22,
    Reg_rsrv23,
    Reg_rsrv24,
    Reg_rsrv25,
    Reg_rsrv26,
    Reg_rsrv27,
    Reg_rsrv28,
    Reg_rsrv29,
    Reg_rsrv30,
    Reg_rsrv31,
    Reg_Total
};
 
/** Signal types */
enum EResetType {
    RESET_Unused0,
    RESET_LVI,      // Low-voltage inhibit Reset Bit
    RESET_Unused2,
    RESET_ILAD,     // Illegal Address Reset Bit
    RESET_ILOP,     // Illegal Opcode Reset Bit
    RESET_COP,      // Compute Operating Properly Reset Bit
    RESET_PIN,      // External Reset Bit (nRST)
    RESET_PON,      // POWER-on Reset Bit
};
 
class ICpuHC08 : public IFace {
 public:
    ICpuHC08() : IFace(IFACE_CPU_HC08) {}
 
    /** Fast access to memory mapped registers */
    virtual Reg64Type *getpRegs() = 0;
 
    /** External IRQ line status (need for BIH, BIL instructions) */
    virtual bool getIRQ() = 0;
 
    /** Update COP watchdog settings */
    virtual void updateCOP() = 0;
 
    /** Reset sequence has ben writen */
    virtual void resetCOP() = 0;
    virtual void vectorUpdated() = 0;
};
 
}  // namespace debugger
 
#endif  // __DEBUGGER_COMMON_CORESERVICES_ICPU_HC08_H__

Line No.	Rev	Author	Line
1	5	sergeykhbr	`/**`
2			`* @file`
3			`* @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.`
4			`* @author Sergey Khabarov - sergeykhbr@gmail.com`
5			`* @brief CPU HC08 specific interface.`
6			`*/`
7
8			`#ifndef __DEBUGGER_COMMON_CORESERVICES_ICPU_HC08_H__`
9			`#define __DEBUGGER_COMMON_CORESERVICES_ICPU_HC08_H__`
10
11			`#include <inttypes.h>`
12			`#include <iface.h>`
13
14			`namespace debugger {`
15
16			`static const char *const IFACE_CPU_HC08 = "ICpuHC08";`
17
18			`enum ERegNames {`
19			`Reg_A, // 0`
20			`Reg_HX, // 1`
21			`Reg_SP, // 2`
22			`Reg_CCR, // 3`
23			`Reg_PPAGE, // 4`
24			`Reg_ClkHz, // 5`
25			`Reg_rsrv6, // 6`
26			`Reg_rsrv7,`
27			`Reg_rsrv8,`
28			`Reg_rsrv9,`
29			`Reg_rsrv10,`
30			`Reg_rsrv11,`
31			`Reg_rsrv12,`
32			`Reg_rsrv13,`
33			`Reg_rsrv14,`
34			`Reg_rsrv15,`
35			`Reg_rsrv16,`
36			`Reg_rsrv17,`
37			`Reg_rsrv18,`
38			`Reg_rsrv19,`
39			`Reg_rsrv20,`
40			`Reg_rsrv21,`
41			`Reg_rsrv22,`
42			`Reg_rsrv23,`
43			`Reg_rsrv24,`
44			`Reg_rsrv25,`
45			`Reg_rsrv26,`
46			`Reg_rsrv27,`
47			`Reg_rsrv28,`
48			`Reg_rsrv29,`
49			`Reg_rsrv30,`
50			`Reg_rsrv31,`
51			`Reg_Total`
52			`};`
53
54			`/** Signal types */`
55			`enum EResetType {`
56			`RESET_Unused0,`
57			`RESET_LVI, // Low-voltage inhibit Reset Bit`
58			`RESET_Unused2,`
59			`RESET_ILAD, // Illegal Address Reset Bit`
60			`RESET_ILOP, // Illegal Opcode Reset Bit`
61			`RESET_COP, // Compute Operating Properly Reset Bit`
62			`RESET_PIN, // External Reset Bit (nRST)`
63			`RESET_PON, // POWER-on Reset Bit`
64			`};`
65
66			`class ICpuHC08 : public IFace {`
67			`public:`
68			`ICpuHC08() : IFace(IFACE_CPU_HC08) {}`
69
70			`/** Fast access to memory mapped registers */`
71			`virtual Reg64Type *getpRegs() = 0;`
72
73			`/** External IRQ line status (need for BIH, BIL instructions) */`
74			`virtual bool getIRQ() = 0;`
75
76			`/** Update COP watchdog settings */`
77			`virtual void updateCOP() = 0;`
78
79			`/** Reset sequence has ben writen */`
80			`virtual void resetCOP() = 0;`
81			`virtual void vectorUpdated() = 0;`
82			`};`
83
84			`} // namespace debugger`
85
86			`#endif // __DEBUGGER_COMMON_CORESERVICES_ICPU_HC08_H__`

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[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [common/] [coreservices/] [icpu_hc08.h] - Blame information for rev 5