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Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [common/] [coreservices/] [imemop.h] - Blame information for rev 2

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/**
 * @file
 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
 * @author     Sergey Khabarov - sergeykhbr@gmail.com
 * @brief      Memory Operation interface implemented by slave devices on bus.
 */
 
#ifndef __DEBUGGER_IMEMOP_PLUGIN_H__
#define __DEBUGGER_IMEMOP_PLUGIN_H__
 
#include "iface.h"
#include <inttypes.h>
#include "isocinfo.h"
 
namespace debugger {
 
static const char *const IFACE_MEMORY_OPERATION = "IMemoryOperation";
static const char *const IFACE_AXI4_NB_RESPONSE = "IAxi4NbResponse";
 
static const int PAYLOAD_MAX_BYTES = 8;
 
enum EAxi4Action {
    MemAction_Read,
    MemAction_Write,
    MemAction_Total
};
 
enum EAxi4Response {
    MemResp_Valid,
    MemResp_Accepted,
    MemResp_Error
};
 
typedef struct Axi4TransactionType {
    EAxi4Action action;
    EAxi4Response response;
    uint32_t xsize;             // [Bytes] Isn't used XSize AXI format!!!.
    uint32_t wstrb;             // 1 bit per byte
    uint64_t addr;
    union {
        uint8_t b8[PAYLOAD_MAX_BYTES];
        uint16_t b16[PAYLOAD_MAX_BYTES/sizeof(uint16_t)];
        uint32_t b32[PAYLOAD_MAX_BYTES/sizeof(uint32_t)];
        uint64_t b64[PAYLOAD_MAX_BYTES/sizeof(uint64_t)];
    } rpayload, wpayload;
    int source_idx;             // Need for bus utilization statistic
} Axi4TransactionType;
 
/**
 * Non-blocking memory access response interface (Initiator/Master)
 */
class IAxi4NbResponse : public IFace {
public:
    IAxi4NbResponse() : IFace(IFACE_AXI4_NB_RESPONSE) {}
 
    virtual void nb_response(Axi4TransactionType *trans) =0;
};
 
/**
 * Slave/Targer interface
 */
class IMemoryOperation : public IFace {
public:
    IMemoryOperation() : IFace(IFACE_MEMORY_OPERATION) {}
 
    /**
     * Blocking transaction
     *
     * Must be implemented by any functional/systemc device mapped into memory
     */
    virtual void b_transport(Axi4TransactionType *trans) =0;
 
    /**
     * Non-blocking transaction
     *
     * Can be implemented for interaction with the SystemC model for an example.
     * Default implementation re-direct to blocking transport
     */
    virtual void nb_transport(Axi4TransactionType *trans,
                              IAxi4NbResponse *cb) {
        b_transport(trans);
        cb->nb_response(trans);
    }
 
    virtual uint64_t getBaseAddress() =0;
 
    virtual uint64_t getLength() =0;
};
 
}  // namespace debugger
 
#endif  // __DEBUGGER_IMEMOP_PLUGIN_H__

Line No.	Rev	Author	Line
1	2	sergeykhbr	`/**`
2			`* @file`
3			`* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.`
4			`* @author Sergey Khabarov - sergeykhbr@gmail.com`
5			`* @brief Memory Operation interface implemented by slave devices on bus.`
6			`*/`
7
8			`#ifndef __DEBUGGER_IMEMOP_PLUGIN_H__`
9			`#define __DEBUGGER_IMEMOP_PLUGIN_H__`
10
11			`#include "iface.h"`
12			`#include <inttypes.h>`
13			`#include "isocinfo.h"`
14
15			`namespace debugger {`
16
17			`static const char *const IFACE_MEMORY_OPERATION = "IMemoryOperation";`
18			`static const char *const IFACE_AXI4_NB_RESPONSE = "IAxi4NbResponse";`
19
20			`static const int PAYLOAD_MAX_BYTES = 8;`
21
22			`enum EAxi4Action {`
23			`MemAction_Read,`
24			`MemAction_Write,`
25			`MemAction_Total`
26			`};`
27
28			`enum EAxi4Response {`
29			`MemResp_Valid,`
30			`MemResp_Accepted,`
31			`MemResp_Error`
32			`};`
33
34			`typedef struct Axi4TransactionType {`
35			`EAxi4Action action;`
36			`EAxi4Response response;`
37			`uint32_t xsize; // [Bytes] Isn't used XSize AXI format!!!.`
38			`uint32_t wstrb; // 1 bit per byte`
39			`uint64_t addr;`
40			`union {`
41			`uint8_t b8[PAYLOAD_MAX_BYTES];`
42			`uint16_t b16[PAYLOAD_MAX_BYTES/sizeof(uint16_t)];`
43			`uint32_t b32[PAYLOAD_MAX_BYTES/sizeof(uint32_t)];`
44			`uint64_t b64[PAYLOAD_MAX_BYTES/sizeof(uint64_t)];`
45			`} rpayload, wpayload;`
46			`int source_idx; // Need for bus utilization statistic`
47			`} Axi4TransactionType;`
48
49			`/**`
50			`* Non-blocking memory access response interface (Initiator/Master)`
51			`*/`
52			`class IAxi4NbResponse : public IFace {`
53			`public:`
54			`IAxi4NbResponse() : IFace(IFACE_AXI4_NB_RESPONSE) {}`
55
56			`virtual void nb_response(Axi4TransactionType *trans) =0;`
57			`};`
58
59			`/**`
60			`* Slave/Targer interface`
61			`*/`
62			`class IMemoryOperation : public IFace {`
63			`public:`
64			`IMemoryOperation() : IFace(IFACE_MEMORY_OPERATION) {}`
65
66			`/**`
67			`* Blocking transaction`
68			`*`
69			`* Must be implemented by any functional/systemc device mapped into memory`
70			`*/`
71			`virtual void b_transport(Axi4TransactionType *trans) =0;`
72
73			`/**`
74			`* Non-blocking transaction`
75			`*`
76			`* Can be implemented for interaction with the SystemC model for an example.`
77			`* Default implementation re-direct to blocking transport`
78			`*/`
79			`virtual void nb_transport(Axi4TransactionType *trans,`
80			`IAxi4NbResponse *cb) {`
81			`b_transport(trans);`
82			`cb->nb_response(trans);`
83			`}`
84
85			`virtual uint64_t getBaseAddress() =0;`
86
87			`virtual uint64_t getLength() =0;`
88			`};`
89
90			`} // namespace debugger`
91
92			`#endif // __DEBUGGER_IMEMOP_PLUGIN_H__`

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[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [common/] [coreservices/] [imemop.h] - Blame information for rev 2