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/*
 *  Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
 *
 *  Licensed under the Apache License, Version 2.0 (the "License");
 *  you may not use this file except in compliance with the License.
 *  You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 *  Unless required by applicable law or agreed to in writing, software
 *  distributed under the License is distributed on an "AS IS" BASIS,
 *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *  See the License for the specific language governing permissions and
 *  limitations under the License.
 */
 
#ifndef __DEBUGGER_RISCV_ISA_H__
#define __DEBUGGER_RISCV_ISA_H__
 
#include <inttypes.h>
 
namespace debugger {
 
union ISA_R_type {
    struct bits_type {
        uint32_t opcode : 7;  // [6:0]
        uint32_t rd     : 5;  // [11:7]
        uint32_t funct3 : 3;  // [14:12]
        uint32_t rs1    : 5;  // [19:15]
        uint32_t rs2    : 5;  // [24:20]
        uint32_t funct7 : 7;  // [31:25]
    } bits;
    uint32_t value;
};
 
union ISA_I_type {
    struct bits_type {
        uint32_t opcode : 7;  // [6:0]
        uint32_t rd     : 5;  // [11:7]
        uint32_t funct3 : 3;  // [14:12]
        uint32_t rs1    : 5;  // [19:15]
        uint32_t imm    : 12;  // [31:20]
    } bits;
    uint32_t value;
};
 
union ISA_S_type {
    struct bits_type {
        uint32_t opcode : 7;  // [6:0]
        uint32_t imm4_0 : 5;  // [11:7]
        uint32_t funct3 : 3;  // [14:12]
        uint32_t rs1    : 5;  // [19:15]
        uint32_t rs2    : 5;  // [24:20]
        uint32_t imm11_5 : 7;  // [31:25]
    } bits;
    uint32_t value;
};
 
union ISA_SB_type {
    struct bits_type {
        uint32_t opcode : 7;  // [6:0]
        uint32_t imm11  : 1;  // [7]
        uint32_t imm4_1 : 4;  // [11:8]
        uint32_t funct3 : 3;  // [14:12]
        uint32_t rs1    : 5;  // [19:15]
        uint32_t rs2    : 5;  // [24:20]
        uint32_t imm10_5 : 6;  // [30:25]
        uint32_t imm12   : 1;  // [31]
    } bits;
    uint32_t value;
};
 
union ISA_U_type {
    struct bits_type {
        uint32_t opcode : 7;  // [6:0]
        uint32_t rd     : 5;  // [11:7]
        uint32_t imm31_12 : 20;  // [31:12]
    } bits;
    uint32_t value;
};
 
union ISA_UJ_type {
    struct bits_type {
        uint32_t opcode   : 7;   // [6:0]
        uint32_t rd       : 5;   // [11:7]
        uint32_t imm19_12 : 8;   // [19:12]
        uint32_t imm11    : 1;   // [20]
        uint32_t imm10_1  : 10;  // [30:21]
        uint32_t imm20    : 1;   // [31]
    } bits;
    uint32_t value;
};
 
/**
 * Compressed extension types:
 */
 
// Regsiter
union ISA_CR_type {
    struct bits_type {
        uint16_t opcode : 2;  // [1:0]
        uint16_t rs2    : 5;  // [6:2]
        uint16_t rdrs1  : 5;  // [11:7]
        uint16_t funct4 : 4;  // [15:12]
    } bits;
    uint16_t value;
};
 
// Immediate
union ISA_CI_type {
    struct bits_type {
        uint16_t opcode : 2;  // [1:0]
        uint16_t imm    : 5;  // [6:2]
        uint16_t rdrs   : 5;  // [11:7]
        uint16_t imm6   : 1;  // [12]
        uint16_t funct3 : 3;  // [15:13]
    } bits;
    struct sp_bits_type {
        uint16_t opcode : 2;  // [1:0]
        uint16_t imm5    : 1; // [2]
        uint16_t imm8_7  : 2; // [4:3]
        uint16_t imm6  : 1;   // [5]
        uint16_t imm4  : 1;   // [6]
        uint16_t sp    : 5;   // [11:7]
        uint16_t imm9   : 1;  // [12]
        uint16_t funct3 : 3;  // [15:13]
    } spbits;
    struct ldsp_bits_type {
        uint16_t opcode : 2;  // [1:0]
        uint16_t off8_6 : 3;  // [4:2]
        uint16_t off4_3 : 2;  // [6:5]
        uint16_t rd     : 5;  // [11:7]
        uint16_t off5   : 1;  // [12]
        uint16_t funct3 : 3;  // [15:13]
    } ldspbits;
    struct lwsp_bits_type {
        uint16_t opcode : 2;  // [1:0]
        uint16_t off7_6 : 2;  // [3:2]
        uint16_t off4_2 : 3;  // [6:4]
        uint16_t rd     : 5;  // [11:7]
        uint16_t off5   : 1;  // [12]
        uint16_t funct3 : 3;  // [15:13]
    } lwspbits;
    uint16_t value;
};
 
// Stack relative Store
union ISA_CSS_type {
    struct w_bits_type {
        uint16_t opcode : 2;  // [1:0]
        uint16_t rs2    : 5;  // [6:2]
        uint16_t imm7_6 : 2;  // [8:7]
        uint16_t imm5_2 : 4;  // [12:9]
        uint16_t funct3 : 3;  // [15:13]
    } wbits;
    struct d_bits_type {
        uint16_t opcode : 2;  // [1:0]
        uint16_t rs2    : 5;  // [6:2]
        uint16_t imm8_6 : 3;  // [9:7]
        uint16_t imm5_3 : 3;  // [12:10]
        uint16_t funct3 : 3;  // [15:13]
    } dbits;
    uint16_t value;
};
 
// Wide immediate
union ISA_CIW_type {
    struct bits_type {
        uint16_t opcode : 2;  // [1:0]
        uint16_t rd     : 3;  // [4:2]
        uint16_t imm3   : 1;  // [5]
        uint16_t imm2   : 1;  // [6]
        uint16_t imm9_6 : 4;  // [10:7]
        uint16_t imm5_4 : 2;  // [12:11]
        uint16_t funct3 : 3;  // [15:13]
    } bits;
    uint16_t value;
};
 
// Load
union ISA_CL_type {
    struct bits_type {
        uint16_t opcode : 2;  // [1:0]
        uint16_t rd     : 3;  // [4:2]
        uint16_t imm6   : 1;  // [5]
        uint16_t imm27  : 1;  // [6]
        uint16_t rs1    : 3;  // [9:7]
        uint16_t imm5_3 : 3;  // [12:10]
        uint16_t funct3 : 3;  // [15:13]
    } bits;
    uint16_t value;
};
 
// Store
union ISA_CS_type {
    struct bits_type {
        uint16_t opcode : 2;  // [1:0]
        uint16_t rs2    : 3;  // [4:2]
        uint16_t imm6   : 1;  // [5]
        uint16_t imm27  : 1;  // [6]
        uint16_t rs1    : 3;  // [9:7]
        uint16_t imm5_3 : 3;  // [12:10]
        uint16_t funct3 : 3;  // [15:13]
    } bits;
    uint16_t value;
};
 
// Branch
union ISA_CB_type {
    struct bits_type {
        uint16_t opcode : 2;  // [1:0]
        uint16_t off5   : 1;  // [2]
        uint16_t off2_1 : 2;  // [4:3]
        uint16_t off7_6 : 2;  // [6:5]
        uint16_t rs1    : 3;  // [9:7]
        uint16_t off4_3 : 2;  // [11:10]
        uint16_t off8   : 1;  // [12]
        uint16_t funct3 : 3;  // [15:13]
    } bits;
    struct sh_bits_type {
        uint16_t opcode : 2;  // [1:0]
        uint16_t shamt  : 5;  // [6:2]
        uint16_t rd     : 3;  // [9:7]
        uint16_t funct2 : 2;  // [11:10]
        uint16_t shamt5 : 1;  // [12]
        uint16_t funct3 : 3;  // [15:13]
    } shbits;
    uint16_t value;
};
 
// Jump
union ISA_CJ_type {
    struct bits_type {
        uint16_t opcode : 2;  // [1:0]
        uint16_t off5   : 1;  // [2]
        uint16_t off3_1 : 3;  // [5:3]
        uint16_t off7   : 1;  // [6]
        uint16_t off6   : 1;  // [7]
        uint16_t off10  : 1;  // [8]
        uint16_t off9_8 : 2;  // [10:9]
        uint16_t off4   : 1;  // [11]
        uint16_t off11  : 1;  // [12]
        uint16_t funct3 : 3;  // [15:13]
    } bits;
    uint16_t value;
};
 
 
static const uint64_t EXT_SIGN_5  = 0xFFFFFFFFFFFFFFF0LL;
static const uint64_t EXT_SIGN_6  = 0xFFFFFFFFFFFFFFE0LL;
static const uint64_t EXT_SIGN_8  = 0xFFFFFFFFFFFFFF80LL;
static const uint64_t EXT_SIGN_9  = 0xFFFFFFFFFFFFFF00LL;
static const uint64_t EXT_SIGN_11 = 0xFFFFFFFFFFFFF800LL;
static const uint64_t EXT_SIGN_12 = 0xFFFFFFFFFFFFF000LL;
static const uint64_t EXT_SIGN_16 = 0xFFFFFFFFFFFF0000LL;
static const uint64_t EXT_SIGN_32 = 0xFFFFFFFF00000000LL;
 
static const char *const IREGS_NAMES[] = {
    "zero",     // [0] zero
    "ra",       // [1] Return address
    "sp",       // [2] Stack pointer
    "gp",       // [3] Global pointer
    "tp",       // [4] Thread pointer
    "t0",       // [5] Temporaries 0 s3
    "t1",       // [6] Temporaries 1 s4
    "t2",       // [7] Temporaries 2 s5
    "s0",       // [8] s0/fp Saved register/frame pointer
    "s1",       // [9] Saved register 1
    "a0",       // [10] Function argumentes 0
    "a1",       // [11] Function argumentes 1
    "a2",       // [12] Function argumentes 2
    "a3",       // [13] Function argumentes 3
    "a4",       // [14] Function argumentes 4
    "a5",       // [15] Function argumentes 5
    "a6",       // [16] Function argumentes 6
    "a7",       // [17] Function argumentes 7
    "s2",       // [18] Saved register 2
    "s3",       // [19] Saved register 3
    "s4",       // [20] Saved register 4
    "s5",       // [21] Saved register 5
    "s6",       // [22] Saved register 6
    "s7",       // [23] Saved register 7
    "s8",       // [24] Saved register 8
    "s9",       // [25] Saved register 9
    "s10",      // [26] Saved register 10
    "s11",      // [27] Saved register 11
    "t3",       // [28]
    "t4",       // [29]
    "t5",       // [30]
    "t6"        // [31]
};
 
const char *const FREGS_NAME[] = {
  "ft0", "ft1", "ft2",  "ft3",  "ft4", "ft5", "ft6",  "ft7",
  "fs0", "fs1", "fa0",  "fa1",  "fa2", "fa3", "fa4",  "fa5",
  "fa6", "fa7", "fs2",  "fs3",  "fs4", "fs5", "fs6",  "fs7",
  "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
};
 
enum ERegNames {
    Reg_Zero,
    Reg_ra,       // [1] Return address
    Reg_sp,       // [2] Stack pointer
    Reg_gp,       // [3] Global pointer
    Reg_tp,       // [4] Thread pointer
    Reg_t0,       // [5] Temporaries 0 s3
    Reg_t1,       // [6] Temporaries 1 s4
    Reg_t2,       // [7] Temporaries 2 s5
    Reg_s0,       // [8] s0/fp Saved register/frame pointer
    Reg_s1,       // [9] Saved register 1
    Reg_a0,       // [10] Function argumentes 0
    Reg_a1,       // [11] Function argumentes 1
    Reg_a2,       // [12] Function argumentes 2
    Reg_a3,       // [13] Function argumentes 3
    Reg_a4,       // [14] Function argumentes 4
    Reg_a5,       // [15] Function argumentes 5
    Reg_a6,       // [16] Function argumentes 6
    Reg_a7,       // [17] Function argumentes 7
    Reg_s2,       // [18] Saved register 2
    Reg_s3,       // [19] Saved register 3
    Reg_s4,       // [20] Saved register 4
    Reg_s5,       // [21] Saved register 5
    Reg_s6,       // [22] Saved register 6
    Reg_s7,       // [23] Saved register 7
    Reg_s8,       // [24] Saved register 8
    Reg_s9,       // [25] Saved register 9
    Reg_s10,      // [26] Saved register 10
    Reg_s11,      // [27] Saved register 11
    Reg_t3,       // [28]
    Reg_t4,       // [29]
    Reg_t5,       // [30]
    Reg_t6,       // [31]
    Reg_Total
};
 
 
union csr_mstatus_type {
    struct bits_type {
        uint64_t UIE    : 1;    // [0]: User level interrupts ena for current
                                //      priv. mode
        uint64_t SIE    : 1;    // [1]: Super-User level interrupts ena for
                                //      current priv. mode
        uint64_t HIE    : 1;    // [2]: Hypervisor level interrupts ena for
                                //      current priv. mode
        uint64_t MIE    : 1;    // [3]: Machine level interrupts ena for
                                //      current priv. mode
        uint64_t UPIE   : 1;    // [4]: User level interrupts ena previous
                                //      value (before interrupt)
        uint64_t SPIE   : 1;    // [5]: Super-User level interrupts ena
                                //      previous value (before interrupt)
        uint64_t HPIE   : 1;    // [6]: Hypervisor level interrupts ena
                                //      previous value (before interrupt)
        uint64_t MPIE   : 1;    // [7]: Machine level interrupts ena previous
                                //      value (before interrupt)
        uint64_t SPP    : 1;    // [8]: One bit wide. Supper-user previously
                                //      priviledged level
        uint64_t HPP    : 2;    // [10:9]: the Hypervisor previous priv mode
        uint64_t MPP    : 2;    // [12:11]: the Machine previous priv mode
        uint64_t FS     : 2;    // [14:13]: RW: FPU context status
        uint64_t XS     : 2;    // [16:15]: RW: extension context status
        uint64_t MPRV   : 1;    // [17] Memory privilege bit
        uint64_t PUM    : 1;    // [18]
        uint64_t MXR    : 1;    // [19]
        uint64_t rsrv1  : 4;    // [23:20]
        uint64_t VM     : 5;    // [28:24] Virtualization management field
        uint64_t rsv2 : 64-30;  // [62:29]
        uint64_t SD     : 1;    // RO: [63] Bit summarizes FS/XS bits
    } bits;
    uint64_t value;
};
 
union csr_mcause_type {
    struct bits_type {
        uint64_t code   : 63;   // 11 - Machine external interrupt
        uint64_t irq    : 1;
    } bits;
    uint64_t value;
};
 
union csr_mie_type {
    struct bits_type {
        uint64_t zero1  : 1;
        uint64_t SSIE   : 1;    // super-visor software interrupt enable
        uint64_t HSIE   : 1;    // hyper-visor software interrupt enable
        uint64_t MSIE   : 1;    // machine mode software interrupt enable
        uint64_t zero2  : 1;
        uint64_t STIE   : 1;    // super-visor time interrupt enable
        uint64_t HTIE   : 1;    // hyper-visor time interrupt enable
        uint64_t MTIE   : 1;    // machine mode time interrupt enable
    } bits;
    uint64_t value;
};
 
union csr_mip_type {
    struct bits_type {
        uint64_t zero1  : 1;
        uint64_t SSIP   : 1;    // super-visor software interrupt pending
        uint64_t HSIP   : 1;    // hyper-visor software interrupt pending
        uint64_t MSIP   : 1;    // machine mode software interrupt pending
        uint64_t zero2  : 1;
        uint64_t STIP   : 1;    // super-visor time interrupt pending
        uint64_t HTIP   : 1;    // hyper-visor time interrupt pending
        uint64_t MTIP   : 1;    // machine mode time interrupt pending
    } bits;
    uint64_t value;
};
 
 
/**
 * @name PRV bits possible values:
 */
/// @{
/// User-mode
static const uint64_t PRV_U       = 0;
/// super-visor mode
static const uint64_t PRV_S       = 1;
/// hyper-visor mode
static const uint64_t PRV_H       = 2;
//// machine mode
static const uint64_t PRV_M       = 3;
/// @}
 
/**
 * @name CSR registers.
 */
/// @{
/** ISA and extensions supported. */
static const uint16_t CSR_misa              = 0xf10;
/** Vendor ID. */
static const uint16_t CSR_mvendorid         = 0xf11;
/** Architecture ID. */
static const uint16_t CSR_marchid           = 0xf12;
/** Vendor ID. */
static const uint16_t CSR_mimplementationid = 0xf13;
/** Thread id (the same as core). */
static const uint16_t CSR_mhartid           = 0xf14;
/** Machine wall-clock time */
static const uint16_t CSR_mtime         = 0x701;
 
/** machine mode status read/write register. */
static const uint16_t CSR_mstatus       = 0x300;
/** Machine exception delegation  */
static const uint16_t CSR_medeleg       = 0x302;
/** Machine interrupt delegation  */
static const uint16_t CSR_mideleg       = 0x303;
/** Machine interrupt enable */
static const uint16_t CSR_mie           = 0x304;
/** The base address of the M-mode trap vector. */
static const uint16_t CSR_mtvec         = 0x305;
/** Machine wall-clock timer compare value. */
static const uint16_t CSR_mtimecmp      = 0x321;
/** Scratch register for machine trap handlers. */
static const uint16_t CSR_mscratch      = 0x340;
/** Exception program counters. */
static const uint16_t CSR_uepc          = 0x041;
static const uint16_t CSR_sepc          = 0x141;
static const uint16_t CSR_hepc          = 0x241;
static const uint16_t CSR_mepc          = 0x341;
/** Machine trap cause */
static const uint16_t CSR_mcause        = 0x342;
/** Machine bad address. */
static const uint16_t CSR_mbadaddr      = 0x343;
/** Machine interrupt pending */
static const uint16_t CSR_mip           = 0x344;
/// @}
 
/** Exceptions */
enum ESignals {
    // Instruction address misaligned
    EXCEPTION_InstrMisalign,
    // Instruction access fault
    EXCEPTION_InstrFault,
    // Illegal instruction
    EXCEPTION_InstrIllegal,
    // Breakpoint
    EXCEPTION_Breakpoint,
    // Load address misaligned
    EXCEPTION_LoadMisalign,
    // Load access fault
    EXCEPTION_LoadFault,
    // Store/AMO address misaligned
    EXCEPTION_StoreMisalign,
    // Store/AMO access fault
    EXCEPTION_StoreFault,
    // Environment call from U-mode
    EXCEPTION_CallFromUmode,
    // Environment call from S-mode
    EXCEPTION_CallFromSmode,
    // Environment call from H-mode
    EXCEPTION_CallFromHmode,
    // Environment call from M-mode
    EXCEPTION_CallFromMmode,
 
    // User software interrupt
    INTERRUPT_USoftware,
    // Superuser software interrupt
    INTERRUPT_SSoftware,
    // Hypervisor software itnerrupt
    INTERRUPT_HSoftware,
    // Machine software interrupt
    INTERRUPT_MSoftware,
    // User timer interrupt
    INTERRUPT_UTimer,
    // Superuser timer interrupt
    INTERRUPT_STimer,
    // Hypervisor timer interrupt
    INTERRUPT_HTimer,
    // Machine timer interrupt
    INTERRUPT_MTimer,
    // User external interrupt
    INTERRUPT_UExternal,
    // Superuser external interrupt
    INTERRUPT_SExternal,
    // Hypervisor external interrupt
    INTERRUPT_HExternal,
    // Machine external interrupt (from PLIC)
    INTERRUPT_MExternal,
 
    SIGNAL_HardReset,
    SIGNAL_Total
};
 
}  // namespace debugger
 
#endif  // __DEBUGGER_RISCV_ISA_H__

Line No.	Rev	Author	Line
1	4	sergeykhbr	`/*`
2			`* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com`
3			`*`
4			`* Licensed under the Apache License, Version 2.0 (the "License");`
5			`* you may not use this file except in compliance with the License.`
6			`* You may obtain a copy of the License at`
7			`*`
8			`* http://www.apache.org/licenses/LICENSE-2.0`
9			`*`
10			`* Unless required by applicable law or agreed to in writing, software`
11			`* distributed under the License is distributed on an "AS IS" BASIS,`
12			`* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.`
13			`* See the License for the specific language governing permissions and`
14			`* limitations under the License.`
15	2	sergeykhbr	`*/`
16	4	sergeykhbr
17	2	sergeykhbr	`#ifndef __DEBUGGER_RISCV_ISA_H__`
18			`#define __DEBUGGER_RISCV_ISA_H__`
19
20			`#include <inttypes.h>`
21
22			`namespace debugger {`
23
24			`union ISA_R_type {`
25			`struct bits_type {`
26	4	sergeykhbr	`uint32_t opcode : 7; // [6:0]`
27			`uint32_t rd : 5; // [11:7]`
28			`uint32_t funct3 : 3; // [14:12]`
29			`uint32_t rs1 : 5; // [19:15]`
30			`uint32_t rs2 : 5; // [24:20]`
31			`uint32_t funct7 : 7; // [31:25]`
32	2	sergeykhbr	`} bits;`
33			`uint32_t value;`
34			`};`
35
36			`union ISA_I_type {`
37			`struct bits_type {`
38	4	sergeykhbr	`uint32_t opcode : 7; // [6:0]`
39			`uint32_t rd : 5; // [11:7]`
40			`uint32_t funct3 : 3; // [14:12]`
41			`uint32_t rs1 : 5; // [19:15]`
42			`uint32_t imm : 12; // [31:20]`
43	2	sergeykhbr	`} bits;`
44			`uint32_t value;`
45			`};`
46
47			`union ISA_S_type {`
48			`struct bits_type {`
49	4	sergeykhbr	`uint32_t opcode : 7; // [6:0]`
50			`uint32_t imm4_0 : 5; // [11:7]`
51			`uint32_t funct3 : 3; // [14:12]`
52			`uint32_t rs1 : 5; // [19:15]`
53			`uint32_t rs2 : 5; // [24:20]`
54			`uint32_t imm11_5 : 7; // [31:25]`
55	2	sergeykhbr	`} bits;`
56			`uint32_t value;`
57			`};`
58
59			`union ISA_SB_type {`
60			`struct bits_type {`
61	4	sergeykhbr	`uint32_t opcode : 7; // [6:0]`
62			`uint32_t imm11 : 1; // [7]`
63			`uint32_t imm4_1 : 4; // [11:8]`
64			`uint32_t funct3 : 3; // [14:12]`
65			`uint32_t rs1 : 5; // [19:15]`
66			`uint32_t rs2 : 5; // [24:20]`
67			`uint32_t imm10_5 : 6; // [30:25]`
68			`uint32_t imm12 : 1; // [31]`
69	2	sergeykhbr	`} bits;`
70			`uint32_t value;`
71			`};`
72
73			`union ISA_U_type {`
74			`struct bits_type {`
75	4	sergeykhbr	`uint32_t opcode : 7; // [6:0]`
76			`uint32_t rd : 5; // [11:7]`
77			`uint32_t imm31_12 : 20; // [31:12]`
78	2	sergeykhbr	`} bits;`
79			`uint32_t value;`
80			`};`
81
82			`union ISA_UJ_type {`
83			`struct bits_type {`
84	4	sergeykhbr	`uint32_t opcode : 7; // [6:0]`
85			`uint32_t rd : 5; // [11:7]`
86			`uint32_t imm19_12 : 8; // [19:12]`
87			`uint32_t imm11 : 1; // [20]`
88			`uint32_t imm10_1 : 10; // [30:21]`
89			`uint32_t imm20 : 1; // [31]`
90	2	sergeykhbr	`} bits;`
91			`uint32_t value;`
92			`};`
93
94	4	sergeykhbr	`/**`
95			`* Compressed extension types:`
96			`*/`
97
98			`// Regsiter`
99			`union ISA_CR_type {`
100			`struct bits_type {`
101			`uint16_t opcode : 2; // [1:0]`
102			`uint16_t rs2 : 5; // [6:2]`
103			`uint16_t rdrs1 : 5; // [11:7]`
104			`uint16_t funct4 : 4; // [15:12]`
105			`} bits;`
106			`uint16_t value;`
107			`};`
108
109			`// Immediate`
110			`union ISA_CI_type {`
111			`struct bits_type {`
112			`uint16_t opcode : 2; // [1:0]`
113			`uint16_t imm : 5; // [6:2]`
114			`uint16_t rdrs : 5; // [11:7]`
115			`uint16_t imm6 : 1; // [12]`
116			`uint16_t funct3 : 3; // [15:13]`
117			`} bits;`
118			`struct sp_bits_type {`
119			`uint16_t opcode : 2; // [1:0]`
120			`uint16_t imm5 : 1; // [2]`
121			`uint16_t imm8_7 : 2; // [4:3]`
122			`uint16_t imm6 : 1; // [5]`
123			`uint16_t imm4 : 1; // [6]`
124			`uint16_t sp : 5; // [11:7]`
125			`uint16_t imm9 : 1; // [12]`
126			`uint16_t funct3 : 3; // [15:13]`
127			`} spbits;`
128			`struct ldsp_bits_type {`
129			`uint16_t opcode : 2; // [1:0]`
130			`uint16_t off8_6 : 3; // [4:2]`
131			`uint16_t off4_3 : 2; // [6:5]`
132			`uint16_t rd : 5; // [11:7]`
133			`uint16_t off5 : 1; // [12]`
134			`uint16_t funct3 : 3; // [15:13]`
135			`} ldspbits;`
136			`struct lwsp_bits_type {`
137			`uint16_t opcode : 2; // [1:0]`
138			`uint16_t off7_6 : 2; // [3:2]`
139			`uint16_t off4_2 : 3; // [6:4]`
140			`uint16_t rd : 5; // [11:7]`
141			`uint16_t off5 : 1; // [12]`
142			`uint16_t funct3 : 3; // [15:13]`
143			`} lwspbits;`
144			`uint16_t value;`
145			`};`
146
147			`// Stack relative Store`
148			`union ISA_CSS_type {`
149			`struct w_bits_type {`
150			`uint16_t opcode : 2; // [1:0]`
151			`uint16_t rs2 : 5; // [6:2]`
152			`uint16_t imm7_6 : 2; // [8:7]`
153			`uint16_t imm5_2 : 4; // [12:9]`
154			`uint16_t funct3 : 3; // [15:13]`
155			`} wbits;`
156			`struct d_bits_type {`
157			`uint16_t opcode : 2; // [1:0]`
158			`uint16_t rs2 : 5; // [6:2]`
159			`uint16_t imm8_6 : 3; // [9:7]`
160			`uint16_t imm5_3 : 3; // [12:10]`
161			`uint16_t funct3 : 3; // [15:13]`
162			`} dbits;`
163			`uint16_t value;`
164			`};`
165
166			`// Wide immediate`
167			`union ISA_CIW_type {`
168			`struct bits_type {`
169			`uint16_t opcode : 2; // [1:0]`
170			`uint16_t rd : 3; // [4:2]`
171			`uint16_t imm3 : 1; // [5]`
172			`uint16_t imm2 : 1; // [6]`
173			`uint16_t imm9_6 : 4; // [10:7]`
174			`uint16_t imm5_4 : 2; // [12:11]`
175			`uint16_t funct3 : 3; // [15:13]`
176			`} bits;`
177			`uint16_t value;`
178			`};`
179
180			`// Load`
181			`union ISA_CL_type {`
182			`struct bits_type {`
183			`uint16_t opcode : 2; // [1:0]`
184			`uint16_t rd : 3; // [4:2]`
185			`uint16_t imm6 : 1; // [5]`
186			`uint16_t imm27 : 1; // [6]`
187			`uint16_t rs1 : 3; // [9:7]`
188			`uint16_t imm5_3 : 3; // [12:10]`
189			`uint16_t funct3 : 3; // [15:13]`
190			`} bits;`
191			`uint16_t value;`
192			`};`
193
194			`// Store`
195			`union ISA_CS_type {`
196			`struct bits_type {`
197			`uint16_t opcode : 2; // [1:0]`
198			`uint16_t rs2 : 3; // [4:2]`
199			`uint16_t imm6 : 1; // [5]`
200			`uint16_t imm27 : 1; // [6]`
201			`uint16_t rs1 : 3; // [9:7]`
202			`uint16_t imm5_3 : 3; // [12:10]`
203			`uint16_t funct3 : 3; // [15:13]`
204			`} bits;`
205			`uint16_t value;`
206			`};`
207
208			`// Branch`
209			`union ISA_CB_type {`
210			`struct bits_type {`
211			`uint16_t opcode : 2; // [1:0]`
212			`uint16_t off5 : 1; // [2]`
213			`uint16_t off2_1 : 2; // [4:3]`
214			`uint16_t off7_6 : 2; // [6:5]`
215			`uint16_t rs1 : 3; // [9:7]`
216			`uint16_t off4_3 : 2; // [11:10]`
217			`uint16_t off8 : 1; // [12]`
218			`uint16_t funct3 : 3; // [15:13]`
219			`} bits;`
220			`struct sh_bits_type {`
221			`uint16_t opcode : 2; // [1:0]`
222			`uint16_t shamt : 5; // [6:2]`
223			`uint16_t rd : 3; // [9:7]`
224			`uint16_t funct2 : 2; // [11:10]`
225			`uint16_t shamt5 : 1; // [12]`
226			`uint16_t funct3 : 3; // [15:13]`
227			`} shbits;`
228			`uint16_t value;`
229			`};`
230
231			`// Jump`
232			`union ISA_CJ_type {`
233			`struct bits_type {`
234			`uint16_t opcode : 2; // [1:0]`
235			`uint16_t off5 : 1; // [2]`
236			`uint16_t off3_1 : 3; // [5:3]`
237			`uint16_t off7 : 1; // [6]`
238			`uint16_t off6 : 1; // [7]`
239			`uint16_t off10 : 1; // [8]`
240			`uint16_t off9_8 : 2; // [10:9]`
241			`uint16_t off4 : 1; // [11]`
242			`uint16_t off11 : 1; // [12]`
243			`uint16_t funct3 : 3; // [15:13]`
244			`} bits;`
245			`uint16_t value;`
246			`};`
247
248
249			`static const uint64_t EXT_SIGN_5 = 0xFFFFFFFFFFFFFFF0LL;`
250			`static const uint64_t EXT_SIGN_6 = 0xFFFFFFFFFFFFFFE0LL;`
251			`static const uint64_t EXT_SIGN_8 = 0xFFFFFFFFFFFFFF80LL;`
252			`static const uint64_t EXT_SIGN_9 = 0xFFFFFFFFFFFFFF00LL;`
253			`static const uint64_t EXT_SIGN_11 = 0xFFFFFFFFFFFFF800LL;`
254	2	sergeykhbr	`static const uint64_t EXT_SIGN_12 = 0xFFFFFFFFFFFFF000LL;`
255			`static const uint64_t EXT_SIGN_16 = 0xFFFFFFFFFFFF0000LL;`
256			`static const uint64_t EXT_SIGN_32 = 0xFFFFFFFF00000000LL;`
257
258			`static const char *const IREGS_NAMES[] = {`
259			`"zero", // [0] zero`
260			`"ra", // [1] Return address`
261			`"sp", // [2] Stack pointer`
262			`"gp", // [3] Global pointer`
263			`"tp", // [4] Thread pointer`
264			`"t0", // [5] Temporaries 0 s3`
265			`"t1", // [6] Temporaries 1 s4`
266			`"t2", // [7] Temporaries 2 s5`
267			`"s0", // [8] s0/fp Saved register/frame pointer`
268			`"s1", // [9] Saved register 1`
269			`"a0", // [10] Function argumentes 0`
270			`"a1", // [11] Function argumentes 1`
271			`"a2", // [12] Function argumentes 2`
272			`"a3", // [13] Function argumentes 3`
273			`"a4", // [14] Function argumentes 4`
274			`"a5", // [15] Function argumentes 5`
275			`"a6", // [16] Function argumentes 6`
276			`"a7", // [17] Function argumentes 7`
277			`"s2", // [18] Saved register 2`
278			`"s3", // [19] Saved register 3`
279			`"s4", // [20] Saved register 4`
280			`"s5", // [21] Saved register 5`
281			`"s6", // [22] Saved register 6`
282			`"s7", // [23] Saved register 7`
283			`"s8", // [24] Saved register 8`
284			`"s9", // [25] Saved register 9`
285			`"s10", // [26] Saved register 10`
286			`"s11", // [27] Saved register 11`
287	4	sergeykhbr	`"t3", // [28]`
288			`"t4", // [29]`
289			`"t5", // [30]`
290			`"t6" // [31]`
291	2	sergeykhbr	`};`
292
293			`const char *const FREGS_NAME[] = {`
294			`"ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",`
295			`"fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",`
296			`"fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",`
297			`"fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"`
298			`};`
299
300	4	sergeykhbr	`enum ERegNames {`
301			`Reg_Zero,`
302			`Reg_ra, // [1] Return address`
303			`Reg_sp, // [2] Stack pointer`
304			`Reg_gp, // [3] Global pointer`
305			`Reg_tp, // [4] Thread pointer`
306			`Reg_t0, // [5] Temporaries 0 s3`
307			`Reg_t1, // [6] Temporaries 1 s4`
308			`Reg_t2, // [7] Temporaries 2 s5`
309			`Reg_s0, // [8] s0/fp Saved register/frame pointer`
310			`Reg_s1, // [9] Saved register 1`
311			`Reg_a0, // [10] Function argumentes 0`
312			`Reg_a1, // [11] Function argumentes 1`
313			`Reg_a2, // [12] Function argumentes 2`
314			`Reg_a3, // [13] Function argumentes 3`
315			`Reg_a4, // [14] Function argumentes 4`
316			`Reg_a5, // [15] Function argumentes 5`
317			`Reg_a6, // [16] Function argumentes 6`
318			`Reg_a7, // [17] Function argumentes 7`
319			`Reg_s2, // [18] Saved register 2`
320			`Reg_s3, // [19] Saved register 3`
321			`Reg_s4, // [20] Saved register 4`
322			`Reg_s5, // [21] Saved register 5`
323			`Reg_s6, // [22] Saved register 6`
324			`Reg_s7, // [23] Saved register 7`
325			`Reg_s8, // [24] Saved register 8`
326			`Reg_s9, // [25] Saved register 9`
327			`Reg_s10, // [26] Saved register 10`
328			`Reg_s11, // [27] Saved register 11`
329			`Reg_t3, // [28]`
330			`Reg_t4, // [29]`
331			`Reg_t5, // [30]`
332			`Reg_t6, // [31]`
333			`Reg_Total`
334			`};`
335	2	sergeykhbr
336
337			`union csr_mstatus_type {`
338			`struct bits_type {`
339	4	sergeykhbr	`uint64_t UIE : 1; // [0]: User level interrupts ena for current`
340			`// priv. mode`
341			`uint64_t SIE : 1; // [1]: Super-User level interrupts ena for`
342			`// current priv. mode`
343			`uint64_t HIE : 1; // [2]: Hypervisor level interrupts ena for`
344			`// current priv. mode`
345			`uint64_t MIE : 1; // [3]: Machine level interrupts ena for`
346			`// current priv. mode`
347			`uint64_t UPIE : 1; // [4]: User level interrupts ena previous`
348			`// value (before interrupt)`
349			`uint64_t SPIE : 1; // [5]: Super-User level interrupts ena`
350			`// previous value (before interrupt)`
351			`uint64_t HPIE : 1; // [6]: Hypervisor level interrupts ena`
352			`// previous value (before interrupt)`
353			`uint64_t MPIE : 1; // [7]: Machine level interrupts ena previous`
354			`// value (before interrupt)`
355			`uint64_t SPP : 1; // [8]: One bit wide. Supper-user previously`
356			`// priviledged level`
357			`uint64_t HPP : 2; // [10:9]: the Hypervisor previous priv mode`
358			`uint64_t MPP : 2; // [12:11]: the Machine previous priv mode`
359	2	sergeykhbr	`uint64_t FS : 2; // [14:13]: RW: FPU context status`
360			`uint64_t XS : 2; // [16:15]: RW: extension context status`
361			`uint64_t MPRV : 1; // [17] Memory privilege bit`
362			`uint64_t PUM : 1; // [18]`
363			`uint64_t MXR : 1; // [19]`
364			`uint64_t rsrv1 : 4; // [23:20]`
365	4	sergeykhbr	`uint64_t VM : 5; // [28:24] Virtualization management field`
366			`uint64_t rsv2 : 64-30; // [62:29]`
367	2	sergeykhbr	`uint64_t SD : 1; // RO: [63] Bit summarizes FS/XS bits`
368			`} bits;`
369			`uint64_t value;`
370			`};`
371
372			`union csr_mcause_type {`
373			`struct bits_type {`
374			`uint64_t code : 63; // 11 - Machine external interrupt`
375			`uint64_t irq : 1;`
376			`} bits;`
377			`uint64_t value;`
378			`};`
379
380			`union csr_mie_type {`
381			`struct bits_type {`
382			`uint64_t zero1 : 1;`
383			`uint64_t SSIE : 1; // super-visor software interrupt enable`
384			`uint64_t HSIE : 1; // hyper-visor software interrupt enable`
385			`uint64_t MSIE : 1; // machine mode software interrupt enable`
386			`uint64_t zero2 : 1;`
387			`uint64_t STIE : 1; // super-visor time interrupt enable`
388			`uint64_t HTIE : 1; // hyper-visor time interrupt enable`
389			`uint64_t MTIE : 1; // machine mode time interrupt enable`
390			`} bits;`
391			`uint64_t value;`
392			`};`
393
394			`union csr_mip_type {`
395			`struct bits_type {`
396			`uint64_t zero1 : 1;`
397			`uint64_t SSIP : 1; // super-visor software interrupt pending`
398			`uint64_t HSIP : 1; // hyper-visor software interrupt pending`
399			`uint64_t MSIP : 1; // machine mode software interrupt pending`
400			`uint64_t zero2 : 1;`
401			`uint64_t STIP : 1; // super-visor time interrupt pending`
402			`uint64_t HTIP : 1; // hyper-visor time interrupt pending`
403			`uint64_t MTIP : 1; // machine mode time interrupt pending`
404			`} bits;`
405			`uint64_t value;`
406			`};`
407
408
409			`/**`
410			`* @name PRV bits possible values:`
411			`*/`
412			`/// @{`
413			`/// User-mode`
414	4	sergeykhbr	`static const uint64_t PRV_U = 0;`
415			`/// super-visor mode`
416			`static const uint64_t PRV_S = 1;`
417			`/// hyper-visor mode`
418			`static const uint64_t PRV_H = 2;`
419			`//// machine mode`
420			`static const uint64_t PRV_M = 3;`
421	2	sergeykhbr	`/// @}`
422
423			`/**`
424			`* @name CSR registers.`
425			`*/`
426			`/// @{`
427			`/** ISA and extensions supported. */`
428			`static const uint16_t CSR_misa = 0xf10;`
429			`/** Vendor ID. */`
430			`static const uint16_t CSR_mvendorid = 0xf11;`
431			`/** Architecture ID. */`
432			`static const uint16_t CSR_marchid = 0xf12;`
433			`/** Vendor ID. */`
434			`static const uint16_t CSR_mimplementationid = 0xf13;`
435			`/** Thread id (the same as core). */`
436			`static const uint16_t CSR_mhartid = 0xf14;`
437			`/** Machine wall-clock time */`
438			`static const uint16_t CSR_mtime = 0x701;`
439
440			`/** machine mode status read/write register. */`
441			`static const uint16_t CSR_mstatus = 0x300;`
442			`/** Machine exception delegation */`
443			`static const uint16_t CSR_medeleg = 0x302;`
444			`/** Machine interrupt delegation */`
445			`static const uint16_t CSR_mideleg = 0x303;`
446			`/** Machine interrupt enable */`
447			`static const uint16_t CSR_mie = 0x304;`
448			`/** The base address of the M-mode trap vector. */`
449			`static const uint16_t CSR_mtvec = 0x305;`
450			`/** Machine wall-clock timer compare value. */`
451			`static const uint16_t CSR_mtimecmp = 0x321;`
452			`/** Scratch register for machine trap handlers. */`
453			`static const uint16_t CSR_mscratch = 0x340;`
454			`/** Exception program counters. */`
455			`static const uint16_t CSR_uepc = 0x041;`
456			`static const uint16_t CSR_sepc = 0x141;`
457			`static const uint16_t CSR_hepc = 0x241;`
458			`static const uint16_t CSR_mepc = 0x341;`
459			`/** Machine trap cause */`
460			`static const uint16_t CSR_mcause = 0x342;`
461	4	sergeykhbr	`/** Machine bad address. */`
462	2	sergeykhbr	`static const uint16_t CSR_mbadaddr = 0x343;`
463			`/** Machine interrupt pending */`
464			`static const uint16_t CSR_mip = 0x344;`
465			`/// @}`
466
467			`/** Exceptions */`
468	4	sergeykhbr	`enum ESignals {`
469	2	sergeykhbr	`// Instruction address misaligned`
470	4	sergeykhbr	`EXCEPTION_InstrMisalign,`
471	2	sergeykhbr	`// Instruction access fault`
472	4	sergeykhbr	`EXCEPTION_InstrFault,`
473	2	sergeykhbr	`// Illegal instruction`
474	4	sergeykhbr	`EXCEPTION_InstrIllegal,`
475	2	sergeykhbr	`// Breakpoint`
476	4	sergeykhbr	`EXCEPTION_Breakpoint,`
477	2	sergeykhbr	`// Load address misaligned`
478	4	sergeykhbr	`EXCEPTION_LoadMisalign,`
479	2	sergeykhbr	`// Load access fault`
480	4	sergeykhbr	`EXCEPTION_LoadFault,`
481			`// Store/AMO address misaligned`
482			`EXCEPTION_StoreMisalign,`
483	2	sergeykhbr	`// Store/AMO access fault`
484	4	sergeykhbr	`EXCEPTION_StoreFault,`
485	2	sergeykhbr	`// Environment call from U-mode`
486	4	sergeykhbr	`EXCEPTION_CallFromUmode,`
487	2	sergeykhbr	`// Environment call from S-mode`
488	4	sergeykhbr	`EXCEPTION_CallFromSmode,`
489	2	sergeykhbr	`// Environment call from H-mode`
490	4	sergeykhbr	`EXCEPTION_CallFromHmode,`
491	2	sergeykhbr	`// Environment call from M-mode`
492	4	sergeykhbr	`EXCEPTION_CallFromMmode,`
493	2	sergeykhbr
494			`// User software interrupt`
495	4	sergeykhbr	`INTERRUPT_USoftware,`
496	2	sergeykhbr	`// Superuser software interrupt`
497	4	sergeykhbr	`INTERRUPT_SSoftware,`
498	2	sergeykhbr	`// Hypervisor software itnerrupt`
499	4	sergeykhbr	`INTERRUPT_HSoftware,`
500	2	sergeykhbr	`// Machine software interrupt`

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