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sergeykhbr |
/*
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* Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __DEBUGGER_SRC_CPU_ARM_PLUGIN_INSTRUCTIONS_H__
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#define __DEBUGGER_SRC_CPU_ARM_PLUGIN_INSTRUCTIONS_H__
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#include <inttypes.h>
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#include "generic/cpu_generic.h"
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namespace debugger {
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class CpuCortex_Functional;
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class ArmInstruction : public GenericInstruction {
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public:
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ArmInstruction(CpuCortex_Functional *icpu, const char *name,
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const char *bits);
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// IInstruction interface:
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virtual const char *name() { return name_.to_string(); }
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virtual int exec(Reg64Type *payload);
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/** conditions return true */
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virtual int exec_checked(Reg64Type *payload) = 0;
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virtual bool parse(uint32_t *payload) {
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return ((payload[0] & mask_) == opcode_);
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}
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virtual uint32_t hash() {
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return (opcode_ >> 24) & 0xF;
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}
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virtual bool check_cond(uint32_t cond);
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virtual uint32_t shift12(DataProcessingType::reg_bits_type instr,
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uint32_t reg, uint64_t Rs);
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virtual uint32_t imm12(DataProcessingType::imm_bits_type instr);
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protected:
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virtual IFace *getInterface(const char *name);
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protected:
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AttributeType name_;
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CpuCortex_Functional *icpu_;
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Axi4TransactionType trans_;
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uint32_t mask_;
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uint32_t opcode_;
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uint64_t *R;
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};
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/** opcodes:
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0000 = AND - Rd:= Op1 AND Op2
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0001 = EOR - Rd:= Op1 EOR Op2
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0010 = SUB - Rd:= Op1 - Op2
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0011 = RSB - Rd:= Op2 - Op1
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0100 = ADD - Rd:= Op1 + Op2
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0101 = ADC - Rd:= Op1 + Op2 + C
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0110 = SBC - Rd:= Op1 - Op2 + C
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0111 = RSC - Rd:= Op2 - Op1 + C
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1000 = TST - set condition codes on Op1 AND Op2
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1001 = TEQ - set condition codes on Op1 EOR Op2
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1010 = CMP - set condition codes on Op1 - Op2
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1011 = CMN - set condition codes on Op1 + Op2
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1100 = ORR - Rd:= Op1 OR Op2
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1101 = MOV - Rd:= Op2
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1110 = BIC - Rd:= Op1 AND NOT Op2
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1111 = MVN - Rd:= NOT Op2
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*/
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class ArmDataProcessingInstruction : public ArmInstruction {
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public:
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ArmDataProcessingInstruction(CpuCortex_Functional *icpu, const char *name,
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const char *bits) : ArmInstruction(icpu, name, bits) {}
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virtual int exec_checked(Reg64Type *payload);
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protected:
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enum EOperationResult {
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OP_Drop,
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OP_Write
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};
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/** Return true if need to write result into Rd register */
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virtual EOperationResult do_operation(uint32_t A, uint32_t M,
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uint32_t *pRes) = 0;
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virtual bool is_flags_changed(DataProcessingType u);
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virtual void set_flags(uint32_t A, uint32_t M, uint32_t Res);
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};
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} // namespace debugger
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#endif // __DEBUGGER_SRC_CPU_ARM_PLUGIN_INSTRUCTIONS_H__
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