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[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_fnc_plugin/] [cpu_riscv_func.cpp] - Blame information for rev 5

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1 4 sergeykhbr 
/**
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 * @file
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 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
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 * @author     Sergey Khabarov - sergeykhbr@gmail.com
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 * @brief      CPU functional simulator class definition.
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 */
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#include <api_core.h>
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#include "cpu_riscv_func.h"
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namespace debugger {
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CpuRiver_Functional::CpuRiver_Functional(const char *name) :
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    CpuGeneric(name),
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    portRegs_(this, "regs", DSUREG(ureg.v.iregs), Reg_Total),
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    portSavedRegs_(this, "savedregs", 0, Reg_Total),  // not mapped !!!
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    portCSR_(this, "csr", DSUREG(csr), 1<<12) {
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    registerInterface(static_cast<ICpuRiscV *>(this));
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    registerAttribute("ListExtISA", &listExtISA_);
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    registerAttribute("VendorID", &vendorID_);
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    registerAttribute("VectorTable", &vectorTable_);
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}
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CpuRiver_Functional::~CpuRiver_Functional() {
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}
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void CpuRiver_Functional::postinitService() {
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    // Supported instruction sets:
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    for (int i = 0; i < INSTR_HASH_TABLE_SIZE; i++) {
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        listInstr_[i].make_list(0);
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    }
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    addIsaUserRV64I();
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    addIsaPrivilegedRV64I();
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    for (unsigned i = 0; i < listExtISA_.size(); i++) {
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        if (listExtISA_[i].to_string()[0] == 'A') {
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            addIsaExtensionA();
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        } else if (listExtISA_[i].to_string()[0] == 'C') {
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            addIsaExtensionC();
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        } else if (listExtISA_[i].to_string()[0] == 'F') {
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            addIsaExtensionF();
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        } else if (listExtISA_[i].to_string()[0] == 'M') {
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            addIsaExtensionM();
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        }
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    }
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    // Power-on
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    reset(false);
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    CpuGeneric::postinitService();
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}
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unsigned CpuRiver_Functional::addSupportedInstruction(
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                                    RiscvInstruction *instr) {
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    AttributeType tmp(instr);
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    listInstr_[instr->hash()].add_to_list(&tmp);
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    return 0;
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}
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void CpuRiver_Functional::handleTrap() {
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    csr_mstatus_type mstatus;
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    csr_mcause_type mcause;
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    if (interrupt_pending_ == 0) {
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        return;
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    }
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    mstatus.value = portCSR_.read(CSR_mstatus).val;
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    mcause.value =  portCSR_.read(CSR_mcause).val;
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    uint64_t exception_mask = (1ull << INTERRUPT_USoftware) - 1;
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    if ((interrupt_pending_ & exception_mask) == 0 &&
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        mstatus.bits.MIE == 0 && cur_prv_level == PRV_M) {
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        return;
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    }
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    if (mcause.value == EXCEPTION_Breakpoint) {
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        DsuMapType::udbg_type::debug_region_type::breakpoint_control_reg t1;
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        t1.val = br_control_.getValue().val;
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        if (t1.bits.trap_on_break == 0) {
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            sw_breakpoint_ = true;
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            interrupt_pending_ &= ~(1ull << EXCEPTION_Breakpoint);
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            npc_.setValue(pc_.getValue());
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            halt("EBREAK Breakpoint");
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            return;
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        }
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    }
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    // All traps handle via machine mode while CSR mdelegate
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    // doesn't setup other.
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    // @todo delegating
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    mstatus.bits.MPP = cur_prv_level;
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    mstatus.bits.MPIE = (mstatus.value >> cur_prv_level) & 0x1;
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    mstatus.bits.MIE = 0;
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    cur_prv_level = PRV_M;
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    portCSR_.write(CSR_mstatus, mstatus.value);
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    int xepc = static_cast<int>((cur_prv_level << 8) + 0x41);
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    if (interrupt_pending_ & exception_mask) {
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        // Exception
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        portCSR_.write(xepc, pc_.getValue().val);
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    } else {
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        // Software interrupt handled after instruction was executed
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        portCSR_.write(xepc,  npc_.getValue().val);
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    }
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    npc_.setValue(portCSR_.read(CSR_mtvec));
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    interrupt_pending_ = 0;
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}
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void CpuRiver_Functional::reset(bool active) {
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    CpuGeneric::reset(active);
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    portRegs_.reset();
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    portCSR_.reset();
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    portCSR_.write(CSR_mvendorid, vendorID_.to_uint64());
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    portCSR_.write(CSR_mtvec, vectorTable_.to_uint64());
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    cur_prv_level = PRV_M;           // Current privilege level
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}
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GenericInstruction *CpuRiver_Functional::decodeInstruction(Reg64Type *cache) {
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    RiscvInstruction *instr = NULL;
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    int hash_idx = hash32(cacheline_[0].buf32[0]);
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    for (unsigned i = 0; i < listInstr_[hash_idx].size(); i++) {
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        instr = static_cast<RiscvInstruction *>(
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                        listInstr_[hash_idx][i].to_iface());
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        if (instr->parse(cacheline_[0].buf32)) {
123 
            break;
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        }
125 
        instr = NULL;
126 
    }
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    // Check compressed instructions:
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    if (instr == NULL) {
129 
        hash_idx = hash16(cacheline_[0].buf16[0]);
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        for (unsigned i = 0; i < listInstr_[hash_idx].size(); i++) {
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            instr = static_cast<RiscvInstruction *>(
132 
                            listInstr_[hash_idx][i].to_iface());
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            if (instr->parse(cacheline_[0].buf32)) {
134 
                break;
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            }
136 
            instr = NULL;
137 
        }
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    }
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    return instr;
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}
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142 
void CpuRiver_Functional::generateIllegalOpcode() {
143 
    raiseSignal(EXCEPTION_InstrIllegal);
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    RISCV_error("Illegal instruction at 0x%08" RV_PRI64 "x", getPC());
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}
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147 
void CpuRiver_Functional::trackContextStart() {
148 
    if (reg_trace_file == 0) {
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        return;
150 
    }
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    /** Save previous reg values to find modification after exec() */
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    uint64_t *dst = portSavedRegs_.getpR64();
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    uint64_t *src = portRegs_.getpR64();
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    memcpy(dst, src, Reg_Total*sizeof(uint64_t));
155 
}
156 
 
157 
void CpuRiver_Functional::trackContextEnd() {
158 
    if (reg_trace_file == 0) {
159 
        return;
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    }
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    int sz;
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    char tstr[1024];
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    sz = RISCV_sprintf(tstr, sizeof(tstr),"%8I64d [%08x]: ",
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        step_cnt_, pc_.getValue().buf32[0]);
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166 
    bool reg_changed = false;
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    uint64_t *prev = portSavedRegs_.getpR64();
168 
    uint64_t *cur = portRegs_.getpR64();
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    for (int i = 0; i < Reg_Total; i++) {
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        if (prev[i] != cur[i]) {
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            reg_changed = true;
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            sz += RISCV_sprintf(&tstr[sz], sizeof(tstr) - sz,
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                    "%3s <= %016I64x",
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                    IREGS_NAMES[i], cur[i]);//, instr_->name());
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        }
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    }
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    if (instr_ && !reg_changed) {
178 
        sz += RISCV_sprintf(&tstr[sz], sizeof(tstr) - sz, "-", NULL);
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    }
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    (*reg_trace_file) << tstr << "\n";
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    reg_trace_file->flush();
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}
183 
 
184 
void CpuRiver_Functional::raiseSignal(int idx) {
185 
    if (idx < INTERRUPT_USoftware) {
186 
        // Exception:
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        csr_mcause_type cause;
188 
        cause.value     = 0;
189 
        cause.bits.irq  = 0;
190 
        cause.bits.code = idx;
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        portCSR_.write(CSR_mcause, cause.value);
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        interrupt_pending_ |= 1LL << idx;
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    } else if (idx < SIGNAL_HardReset) {
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        csr_mcause_type cause;
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        cause.value     = 0;
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        cause.bits.irq  = 1;
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        cause.bits.code = idx - INTERRUPT_USoftware;
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        portCSR_.write(CSR_mcause, cause.value);
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        interrupt_pending_ |= 1LL << idx;
200 
    } else if (idx == SIGNAL_HardReset) {
201 
    } else {
202 
        RISCV_error("Raise unsupported signal %d", idx);
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    }
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}
205 
 
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void CpuRiver_Functional::lowerSignal(int idx) {
207 
    if (idx == SIGNAL_HardReset) {
208 
    } else if (idx < SIGNAL_HardReset) {
209 
        interrupt_pending_ &= ~(1 << idx);
210 
    } else {
211 
        RISCV_error("Lower unsupported signal %d", idx);
212 
    }
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}
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uint64_t CpuRiver_Functional::readCSR(int idx) {
216 
    if (idx == CSR_mtime) {
217 
        return step_cnt_;
218 
    }
219 
    return portCSR_.read(idx).val;
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}
221 
 
222 
void CpuRiver_Functional::writeCSR(int idx, uint64_t val) {
223 
    switch (idx) {
224 
    // Read-Only registers
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    case CSR_misa:
226 
    case CSR_mvendorid:
227 
    case CSR_marchid:
228 
    case CSR_mimplementationid:
229 
    case CSR_mhartid:
230 
        break;
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    case CSR_mtime:
232 
        break;
233 
    default:
234 
        portCSR_.write(idx, val);
235 
    }
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}
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}  // namespace debugger
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