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Subversion Repositories riscv_vhdl

[/] [riscv_vhdl/] [trunk/] [debugger/] [src/] [cpu_sysc_plugin/] [riverlib/] [cache/] [dcache.cpp] - Blame information for rev 4

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Line No. Rev Author Line
1 3 sergeykhbr 
/**
2 
 * @file
3 
 * @copyright  Copyright 2016 GNSS Sensor Ltd. All right reserved.
4 
 * @author     Sergey Khabarov - sergeykhbr@gmail.com
5 
 * @brief      Data Cache.
6 
 */
7 
 
8 
#include "dcache.h"
9 
 
10 
namespace debugger {
11 
 
12 
DCache::DCache(sc_module_name name_) : sc_module(name_) {
13 
    SC_METHOD(comb);
14 
    sensitive << i_nrst;
15 
    sensitive << i_req_data_valid;
16 
    sensitive << i_req_data_write;
17 
    sensitive << i_req_data_sz;
18 
    sensitive << i_req_data_addr;
19 
    sensitive << i_req_data_data;
20 
    sensitive << i_resp_mem_data_valid;
21 
    sensitive << i_resp_mem_data;
22 
    sensitive << i_req_mem_ready;
23 
    sensitive << i_resp_data_ready;
24 
    sensitive << r.dline_data;
25 
    sensitive << r.dline_addr_req;
26 
    sensitive << r.dline_size_req;
27 
    sensitive << r.state;
28 
 
29 
    SC_METHOD(registers);
30 
    sensitive << i_clk.pos();
31 
};
32 
 
33 
void DCache::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
34 
    if (o_vcd) {
35 
        sc_trace(o_vcd, i_req_data_valid, "/top/cache0/d0/i_req_data_valid");
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        sc_trace(o_vcd, i_req_data_write, "/top/cache0/d0/i_req_data_write");
37 
        sc_trace(o_vcd, i_req_data_sz, "/top/cache0/d0/i_req_data_sz");
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        sc_trace(o_vcd, i_req_data_addr, "/top/cache0/d0/i_req_data_addr");
39 
        sc_trace(o_vcd, i_req_data_data, "/top/cache0/d0/i_req_data_data");
40 
        sc_trace(o_vcd, o_req_mem_addr, "/top/cache0/d0/o_req_mem_addr");
41 
        sc_trace(o_vcd, o_req_mem_strob, "/top/cache0/d0/o_req_mem_strob");
42 
        sc_trace(o_vcd, o_req_mem_data, "/top/cache0/d0/o_req_mem_data");
43 
        sc_trace(o_vcd, o_resp_data_valid, "/top/cache0/d0/o_resp_data_valid");
44 
        sc_trace(o_vcd, o_resp_data_addr, "/top/cache0/d0/o_resp_data_addr");
45 
        sc_trace(o_vcd, o_resp_data_data, "/top/cache0/d0/o_resp_data_data");
46 
        sc_trace(o_vcd, r.dline_data, "/top/cache0/d0/r_dline_data");
47 
        sc_trace(o_vcd, r.dline_addr_req, "/top/cache0/d0/r_dline_addr_req");
48 
        sc_trace(o_vcd, r.dline_size_req, "/top/cache0/d0/r_dline_size_req");
49 
        sc_trace(o_vcd, r.state, "/top/cache0/d0/r_state");
50 4 sergeykhbr 
        sc_trace(o_vcd, w_wait_response, "/top/cache0/d0/w_wait_response");    }
51 3 sergeykhbr 
}
52 
 
53 
void DCache::comb() {
54 
    bool w_o_req_data_ready;
55 
    bool w_o_req_mem_valid;
56 
    sc_uint<BUS_ADDR_WIDTH> wb_o_req_mem_addr;
57 
    sc_uint<BUS_DATA_BYTES> wb_o_req_strob;
58 
    sc_uint<BUS_DATA_WIDTH> wb_o_req_wdata;
59 
    bool w_req_fire;
60 
    bool w_o_resp_valid;
61 
    sc_uint<BUS_ADDR_WIDTH> wb_o_resp_addr;
62 
    sc_uint<BUS_DATA_WIDTH> wb_resp_data_mux;
63 
    sc_uint<BUS_DATA_WIDTH> wb_o_resp_data;
64 
    sc_uint<BUS_DATA_WIDTH> wb_rtmp;
65 
 
66 
    v = r;
67 
 
68 
    wb_o_req_strob = 0;
69 
    wb_o_req_wdata = 0;
70 
    wb_o_resp_data = 0;
71 
    wb_rtmp = 0;
72 
 
73 4 sergeykhbr 
    w_wait_response = 0;
74 
    if (r.state.read() == State_WaitResp && i_resp_mem_data_valid.read() == 0) {
75 
        w_wait_response = 1;
76 
    }
77 
 
78 3 sergeykhbr 
    switch (i_req_data_sz.read()) {
79 
    case 0:
80 
        wb_o_req_wdata = (i_req_data_data.read()(7, 0),
81 
            i_req_data_data.read()(7, 0), i_req_data_data.read()(7, 0),
82 
            i_req_data_data.read()(7, 0), i_req_data_data.read()(7, 0),
83 
            i_req_data_data.read()(7, 0), i_req_data_data.read()(7, 0),
84 
            i_req_data_data.read()(7, 0));
85 
        if (i_req_data_addr.read()(2, 0) == 0x0) {
86 
            wb_o_req_strob = 0x01;
87 
        } else if (i_req_data_addr.read()(2, 0) == 0x1) {
88 
            wb_o_req_strob = 0x02;
89 
        } else if (i_req_data_addr.read()(2, 0) == 0x2) {
90 
            wb_o_req_strob = 0x04;
91 
        } else if (i_req_data_addr.read()(2, 0) == 0x3) {
92 
            wb_o_req_strob = 0x08;
93 
        } else if (i_req_data_addr.read()(2, 0) == 0x4) {
94 
            wb_o_req_strob = 0x10;
95 
        } else if (i_req_data_addr.read()(2, 0) == 0x5) {
96 
            wb_o_req_strob = 0x20;
97 
        } else if (i_req_data_addr.read()(2, 0) == 0x6) {
98 
            wb_o_req_strob = 0x40;
99 
        } else if (i_req_data_addr.read()(2, 0) == 0x7) {
100 
            wb_o_req_strob = 0x80;
101 
        }
102 
        break;
103 
    case 1:
104 
        wb_o_req_wdata = (i_req_data_data.read()(15, 0),
105 
            i_req_data_data.read()(15, 0), i_req_data_data.read()(15, 0),
106 
            i_req_data_data.read()(15, 0));
107 
        if (i_req_data_addr.read()(2, 1) == 0) {
108 
            wb_o_req_strob = 0x03;
109 
        } else if (i_req_data_addr.read()(2, 1) == 1) {
110 
            wb_o_req_strob = 0x0C;
111 
        } else if (i_req_data_addr.read()(2, 1) == 2) {
112 
            wb_o_req_strob = 0x30;
113 
        } else {
114 
            wb_o_req_strob = 0xC0;
115 
        }
116 
        break;
117 
    case 2:
118 
        wb_o_req_wdata = (i_req_data_data.read()(31, 0),
119 
                    i_req_data_data.read()(31, 0));
120 
        if (i_req_data_addr.read()[2]) {
121 
            wb_o_req_strob = 0xF0;
122 
        } else {
123 
            wb_o_req_strob = 0x0F;
124 
        }
125 
        break;
126 
    case 3:
127 
        wb_o_req_wdata = i_req_data_data;
128 
        wb_o_req_strob = 0xFF;
129 
        break;
130 
    default:;
131 
    }
132 
 
133 4 sergeykhbr 
    w_o_req_mem_valid = i_req_data_valid.read() && !w_wait_response;
134 3 sergeykhbr 
    wb_o_req_mem_addr = i_req_data_addr.read()(BUS_ADDR_WIDTH-1, 3) << 3;
135 
    w_o_req_data_ready = i_req_mem_ready.read();
136 4 sergeykhbr 
    w_req_fire = w_o_req_mem_valid && w_o_req_data_ready;
137 3 sergeykhbr 
    switch (r.state.read()) {
138 
    case State_Idle:
139 
        if (i_req_data_valid.read()) {
140 
            if (i_req_mem_ready.read()) {
141 
                v.state = State_WaitResp;
142 
            } else {
143 
                v.state = State_WaitGrant;
144 
            }
145 
        }
146 
        break;
147 
    case State_WaitGrant:
148 
        if (i_req_mem_ready.read()) {
149 
            v.state = State_WaitResp;
150 
        }
151 
        break;
152 
    case State_WaitResp:
153 
        if (i_resp_mem_data_valid.read()) {
154 
            if (!i_resp_data_ready.read()) {
155 
                v.state = State_WaitAccept;
156 
            } else if (!i_req_data_valid.read()) {
157 
                v.state = State_Idle;
158 
            } else {
159 
                // New request
160 
                if (i_req_mem_ready.read()) {
161 
                    v.state = State_WaitResp;
162 
                } else {
163 
                    v.state = State_WaitGrant;
164 
                }
165 
            }
166 
        }
167 
        break;
168 
    case State_WaitAccept:
169 
        if (i_resp_data_ready.read()) {
170 
            if (!i_req_data_valid.read()) {
171 
                v.state = State_Idle;
172 
            } else {
173 
                if (i_req_mem_ready.read()) {
174 
                    v.state = State_WaitResp;
175 
                } else {
176 
                    v.state = State_WaitGrant;
177 
                }
178 
            }
179 
        }
180 
        break;
181 
    default:;
182 
    }
183 
 
184 
    if (w_req_fire) {
185 
        v.dline_addr_req = i_req_data_addr;
186 
        v.dline_size_req = i_req_data_sz;
187 
    }
188 
    if (i_resp_mem_data_valid.read()) {
189 
        v.dline_data =  i_resp_mem_data;
190 
    }
191 
 
192 
    wb_o_resp_addr = r.dline_addr_req;
193 
    if (r.state.read() == State_WaitAccept) {
194 
        w_o_resp_valid = 1;
195 
        wb_resp_data_mux = r.dline_data;
196 
    } else {
197 
        w_o_resp_valid = i_resp_mem_data_valid;
198 
        wb_resp_data_mux = i_resp_mem_data;
199 
    }
200 
 
201 
    switch (r.dline_addr_req.read()(2, 0)) {
202 
    case 1:
203 
        wb_rtmp = wb_resp_data_mux(63, 8);
204 
        break;
205 
    case 2:
206 
        wb_rtmp = wb_resp_data_mux(63, 16);
207 
        break;
208 
    case 3:
209 
        wb_rtmp = wb_resp_data_mux(63, 24);
210 
        break;
211 
    case 4:
212 
        wb_rtmp = wb_resp_data_mux(63, 32);
213 
        break;
214 
    case 5:
215 
        wb_rtmp = wb_resp_data_mux(63, 40);
216 
        break;
217 
    case 6:
218 
        wb_rtmp = wb_resp_data_mux(63, 48);
219 
        break;
220 
    case 7:
221 
        wb_rtmp = wb_resp_data_mux(63, 56);
222 
        break;
223 
    default:
224 
        wb_rtmp = wb_resp_data_mux;
225 
    }
226 
 
227 
    switch (r.dline_size_req.read()) {
228 
    case 0:
229 
        wb_o_resp_data = wb_rtmp(7, 0);
230 
        break;
231 
    case 1:
232 
        wb_o_resp_data = wb_rtmp(15, 0);
233 
        break;
234 
    case 2:
235 
        wb_o_resp_data = wb_rtmp(31, 0);
236 
        break;
237 
    default:
238 
        wb_o_resp_data = wb_rtmp;
239 
    }
240 
 
241 
    if (!i_nrst.read()) {
242 
        v.dline_addr_req = 0;
243 
        v.dline_size_req = 0;
244 
        v.dline_data = 0;
245 
        v.state = State_Idle;
246 
    }
247 
 
248 
    o_req_data_ready = w_o_req_data_ready;
249 
 
250 
    o_req_mem_valid = w_o_req_mem_valid;
251 
    o_req_mem_addr = wb_o_req_mem_addr;
252 
    o_req_mem_write = i_req_data_write;
253 
    o_req_mem_strob = wb_o_req_strob;
254 
    o_req_mem_data = wb_o_req_wdata;
255 
 
256 
    o_resp_data_valid = w_o_resp_valid;
257 
    o_resp_data_data = wb_o_resp_data;
258 
    o_resp_data_addr = wb_o_resp_addr;
259 
    o_dstate = r.state;
260 
}
261 
 
262 
void DCache::registers() {
263 
    r = v;
264 
}
265 
 
266 
}  // namespace debugger
267 
 

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