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sergeykhbr |
/**
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* @file
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* @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* @brief Instruction Cache.
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*/
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#include "icache.h"
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namespace debugger {
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ICache::ICache(sc_module_name name_) : sc_module(name_) {
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SC_METHOD(comb);
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sensitive << i_nrst;
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sensitive << i_req_ctrl_valid;
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sensitive << i_req_ctrl_addr;
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sensitive << i_resp_mem_data_valid;
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sensitive << i_resp_mem_data;
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sensitive << i_resp_ctrl_ready;
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sensitive << i_req_mem_ready;
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sensitive << r.iline_addr;
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sensitive << r.iline_data;
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sensitive << r.iline_addr_hit;
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sensitive << r.iline_data_hit;
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sensitive << r.iline_addr_req;
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sensitive << r.hit_line;
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sensitive << r.state;
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SC_METHOD(registers);
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sensitive << i_clk.pos();
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};
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void ICache::generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd) {
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if (o_vcd) {
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sc_trace(o_vcd, i_nrst, "/top/cache0/i0/i_nrst");
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sc_trace(o_vcd, i_req_ctrl_valid, "/top/cache0/i0/i_req_ctrl_valid");
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sc_trace(o_vcd, i_req_ctrl_addr, "/top/cache0/i0/i_req_ctrl_addr");
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sc_trace(o_vcd, o_req_ctrl_ready, "/top/cache0/i0/o_req_ctrl_ready");
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sc_trace(o_vcd, o_req_mem_valid, "/top/cache0/i0/o_req_mem_valid");
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sc_trace(o_vcd, o_req_mem_addr, "/top/cache0/i0/o_req_mem_addr");
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sc_trace(o_vcd, i_req_mem_ready, "/top/cache0/i0/i_req_mem_ready");
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sc_trace(o_vcd, i_resp_mem_data_valid, "/top/cache0/i0/i_resp_mem_data_valid");
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sc_trace(o_vcd, i_resp_mem_data, "/top/cache0/i0/i_resp_mem_data");
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sc_trace(o_vcd, o_resp_ctrl_valid, "/top/cache0/i0/o_resp_ctrl_valid");
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sc_trace(o_vcd, i_resp_ctrl_ready, "/top/cache0/i0/i_resp_ctrl_ready");
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sc_trace(o_vcd, o_resp_ctrl_addr, "/top/cache0/i0/o_resp_ctrl_addr");
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sc_trace(o_vcd, o_resp_ctrl_data, "/top/cache0/i0/o_resp_ctrl_data");
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sc_trace(o_vcd, r.iline_addr, "/top/cache0/i0/r_iline_addr");
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sc_trace(o_vcd, r.iline_data, "/top/cache0/i0/r_iline_data");
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sc_trace(o_vcd, r.iline_addr_hit, "/top/cache0/i0/r_iline_addr_hit");
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sc_trace(o_vcd, r.iline_data_hit, "/top/cache0/i0/r_iline_data_hit");
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sc_trace(o_vcd, r.iline_addr_req, "/top/cache0/i0/r_iline_addr_req");
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sc_trace(o_vcd, r.hit_line, "/top/cache0/i0/r_hit_line");
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sc_trace(o_vcd, r.state, "/top/cache0/i0/r_state");
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sc_trace(o_vcd, w_hit, "/top/cache0/i0/w_hit");
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sc_trace(o_vcd, w_hit_line, "/top/cache0/i0/w_hit_line");
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sc_trace(o_vcd, w_hit_req, "/top/cache0/i0/w_hit_req");
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//sc_trace(o_vcd, wb_req_line, "/top/cache0/i0/wb_req_line");
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//sc_trace(o_vcd, wb_cached_addr, "/top/cache0/i0/wb_cached_addr");
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//sc_trace(o_vcd, wb_cached_data, "/top/cache0/i0/wb_cached_data");
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}
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}
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void ICache::comb() {
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// Instruction cache:
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bool w_o_req_ctrl_ready;
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bool w_o_req_mem_valid;
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sc_uint<BUS_ADDR_WIDTH> wb_o_req_mem_addr;
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bool w_req_fire;
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bool w_o_resp_valid;
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sc_uint<BUS_ADDR_WIDTH> wb_o_resp_addr;
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sc_uint<32> wb_o_resp_data;
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sc_uint<BUS_ADDR_WIDTH - 3> wb_req_line;
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v = r;
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w_hit_req = 0;
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w_hit_line = 0;
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w_hit = 0;
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wb_req_line = i_req_ctrl_addr.read()(BUS_ADDR_WIDTH-1, 3);
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if (i_resp_mem_data_valid.read()
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&& (wb_req_line == r.iline_addr_req.read()(BUS_ADDR_WIDTH-1, 3))) {
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w_hit_req = 1;
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}
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if (wb_req_line == r.iline_addr.read()) {
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w_hit_line = 1;
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}
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w_hit = w_hit_req || w_hit_line;
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w_o_req_mem_valid = !w_hit & i_req_ctrl_valid.read();
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wb_o_req_mem_addr = i_req_ctrl_addr.read()(BUS_ADDR_WIDTH-1, 3) << 3;
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w_o_req_ctrl_ready = w_hit | i_req_mem_ready.read();
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w_req_fire = i_req_ctrl_valid.read() && w_o_req_ctrl_ready;
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switch (r.state.read()) {
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case State_Idle:
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if (i_req_ctrl_valid.read()) {
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if (w_hit_line) {
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v.state = State_WaitAccept;
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} else if (i_req_mem_ready.read()) {
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v.state = State_WaitResp;
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} else {
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v.state = State_WaitGrant;
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}
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}
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break;
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case State_WaitGrant:
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if (i_req_mem_ready.read()) {
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v.state = State_WaitResp;
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} else if (w_hit) {
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/** Fetcher can change request address while request wasn't
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* accepteed. */
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v.state = State_WaitAccept;
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}
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break;
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case State_WaitResp:
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if (i_resp_mem_data_valid.read()) {
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if (!i_resp_ctrl_ready.read()) {
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v.state = State_WaitAccept;
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} else if (!i_req_ctrl_valid.read()) {
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v.state = State_Idle;
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} else {
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// New request
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if (w_hit) {
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v.state = State_WaitAccept;
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} else if (i_req_mem_ready.read()) {
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v.state = State_WaitResp;
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} else {
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v.state = State_WaitGrant;
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}
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}
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}
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break;
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case State_WaitAccept:
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if (i_resp_ctrl_ready.read()) {
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if (!i_req_ctrl_valid.read()) {
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v.state = State_Idle;
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} else {
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if (w_hit) {
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v.state = State_WaitAccept;
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} else if (i_req_mem_ready.read()) {
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v.state = State_WaitResp;
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} else {
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v.state = State_WaitGrant;
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}
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}
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}
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break;
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default:;
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}
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if (w_req_fire) {
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v.iline_addr_req = i_req_ctrl_addr;
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v.hit_line = 0;
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if (w_hit_line) {
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v.hit_line = 1;
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v.iline_addr_hit = i_req_ctrl_addr;
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if (i_req_ctrl_addr.read()[2] == 0) {
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v.iline_data_hit = r.iline_data.read()(31, 0);
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} else {
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v.iline_data_hit = r.iline_data.read()(63, 32);
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}
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}
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}
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if (i_resp_mem_data_valid.read()) {
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v.iline_addr = r.iline_addr_req.read()(BUS_ADDR_WIDTH-1, 3);
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v.iline_data = i_resp_mem_data;
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}
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wb_o_resp_addr = r.iline_addr_req;
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if (r.state.read() == State_WaitAccept) {
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w_o_resp_valid = 1;
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if (r.hit_line) {
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wb_o_resp_addr = r.iline_addr_hit;
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wb_o_resp_data = r.iline_data_hit;
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} else {
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if (r.iline_addr_req.read()[2] == 0) {
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wb_o_resp_data = r.iline_data.read()(31, 0);
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} else {
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wb_o_resp_data = r.iline_data.read()(63, 32);
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}
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}
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} else {
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w_o_resp_valid = i_resp_mem_data_valid;
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if (r.iline_addr_req.read()[2] == 0) {
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wb_o_resp_data = i_resp_mem_data.read()(31, 0);
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} else {
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wb_o_resp_data = i_resp_mem_data.read()(63, 32);
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}
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}
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if (!i_nrst.read()) {
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v.iline_addr_req = 0;
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v.iline_addr = ~0;
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v.iline_data = 0;
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v.iline_addr_hit = ~0;
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v.iline_data_hit = 0;
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v.hit_line = 0;
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v.state = State_Idle;
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}
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o_req_ctrl_ready = w_o_req_ctrl_ready;
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o_req_mem_valid = w_o_req_mem_valid;
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o_req_mem_addr = wb_o_req_mem_addr;
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o_req_mem_write = false;
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o_req_mem_strob = 0;
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o_req_mem_data = 0;
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o_resp_ctrl_valid = w_o_resp_valid;
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o_resp_ctrl_data = wb_o_resp_data;
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o_resp_ctrl_addr = wb_o_resp_addr;
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o_istate = r.state;
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}
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void ICache::registers() {
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r = v;
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}
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#ifdef DBG_ICACHE_TB
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void ICache_tb::comb0() {
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v = r;
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v.clk_cnt = r.clk_cnt.read() + 1;
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if (r.clk_cnt.read() < 10) {
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w_nrst = 0;
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v.mem_state = 0;
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v.mem_cnt = 0;
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v.fetch_state = 0;
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v.fetch_cnt = 0;
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return;
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}
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w_nrst = 1;
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w_req_ctrl_valid = 0;
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wb_req_ctrl_addr = 0;
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w_resp_ctrl_ready = 0;
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struct FetchDelayType {
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uint32_t raddr;
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int req_wait;
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int accept_wait;
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};
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static const FetchDelayType RADDR[4] = {{0x100008f4, 0, 0}, {0x100007b0, 0, 0}, {0x100008f0, 2, 0}, {0x100007b4, 0, 0}};
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struct MemDelayType {
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unsigned rdy_wait;
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unsigned valid_wait;
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};
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//static const MemDelayType MEM_DELAY[4] = {{2,3}, {2,3}, {0,0}, {0,0}};
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static const MemDelayType MEM_DELAY[4] = {{0,0}, {0,0}, {5,0}, {5,0}};
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// fetch model:
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w_resp_ctrl_ready = 0;
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if (r.clk_cnt.read() >= 15) {
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switch (r.fetch_state.read()) {
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case 0:
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if (r.fetch_cnt.read() < 4) {
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if (RADDR[r.fetch_cnt.read()].req_wait == 0) {
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w_req_ctrl_valid = 1;
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wb_req_ctrl_addr = RADDR[r.fetch_cnt.read()].raddr;
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if (w_req_ctrl_ready) {
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v.fetch_state = 3;
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v.fetch_cnt = r.fetch_cnt.read() + 1;
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v.fetch_wait_cnt = RADDR[r.fetch_cnt.read()].accept_wait;
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} else {
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v.fetch_state = 2;
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}
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} else {
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| 270 |
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if (RADDR[r.fetch_cnt.read()].req_wait == 1) {
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v.fetch_state = 2;
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} else {
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v.fetch_state = 1;
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}
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| 275 |
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v.fetch_wait_cnt = RADDR[r.fetch_cnt.read()].req_wait;
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}
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| 277 |
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}
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| 278 |
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break;
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| 279 |
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case 1:
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| 280 |
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// wait to request:
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| 281 |
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v.fetch_wait_cnt = r.fetch_wait_cnt.read() - 1;
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| 282 |
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if (r.fetch_wait_cnt.read() == 1) {
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v.fetch_state = 2;
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}
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| 285 |
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break;
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| 286 |
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case 2:// wait ready signal
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w_req_ctrl_valid = 1;
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wb_req_ctrl_addr = RADDR[r.fetch_cnt.read()].raddr;
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| 289 |
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if (w_req_ctrl_ready) {
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| 290 |
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v.fetch_state = 3;
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v.fetch_cnt = r.fetch_cnt.read() + 1;
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| 292 |
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v.fetch_wait_cnt = RADDR[r.fetch_cnt.read()].accept_wait;
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| 293 |
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}
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| 294 |
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break;
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| 295 |
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case 3: // wait valid signal:
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| 296 |
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if (w_resp_ctrl_valid) {
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| 297 |
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w_resp_ctrl_ready = 1;
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| 298 |
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if (r.fetch_wait_cnt.read()) {
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| 299 |
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v.fetch_wait_cnt = r.fetch_wait_cnt.read() - 1;
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| 300 |
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w_resp_ctrl_ready = 0;
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| 301 |
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} else if (r.fetch_cnt.read() < 4) {
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| 302 |
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if (RADDR[r.fetch_cnt.read()].req_wait == 0) {
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| 303 |
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w_req_ctrl_valid = 1;
|
| 304 |
|
|
wb_req_ctrl_addr = RADDR[r.fetch_cnt.read()].raddr;
|
| 305 |
|
|
if (w_req_ctrl_ready) {
|
| 306 |
|
|
v.fetch_state = 3;
|
| 307 |
|
|
v.fetch_cnt = r.fetch_cnt.read() + 1;
|
| 308 |
|
|
v.fetch_wait_cnt = RADDR[r.fetch_cnt.read()].accept_wait;
|
| 309 |
|
|
} else {
|
| 310 |
|
|
v.fetch_state = 2;
|
| 311 |
|
|
}
|
| 312 |
|
|
} else {
|
| 313 |
|
|
if (RADDR[r.fetch_cnt.read()].req_wait == 1) {
|
| 314 |
|
|
v.fetch_state = 2;
|
| 315 |
|
|
} else {
|
| 316 |
|
|
v.fetch_state = 1;
|
| 317 |
|
|
}
|
| 318 |
|
|
v.fetch_wait_cnt = RADDR[r.fetch_cnt.read()].req_wait;
|
| 319 |
|
|
}
|
| 320 |
|
|
} else {
|
| 321 |
|
|
v.fetch_state = 0;
|
| 322 |
|
|
}
|
| 323 |
|
|
}
|
| 324 |
|
|
break;
|
| 325 |
|
|
default:;
|
| 326 |
|
|
}
|
| 327 |
|
|
}
|
| 328 |
|
|
|
| 329 |
|
|
if (r.clk_cnt.read() == 21) {
|
| 330 |
|
|
wb_req_ctrl_addr = 0x100008f8;
|
| 331 |
|
|
} else if (r.clk_cnt.read() == 22) {
|
| 332 |
|
|
wb_req_ctrl_addr = 0x100007b4;
|
| 333 |
|
|
}
|
| 334 |
|
|
|
| 335 |
|
|
|
| 336 |
|
|
// Memory model:
|
| 337 |
|
|
w_req_mem_ready = 0;
|
| 338 |
|
|
w_resp_mem_data_valid = 0;
|
| 339 |
|
|
|
| 340 |
|
|
switch (r.mem_state.read()) {
|
| 341 |
|
|
case 0: // MemIdle
|
| 342 |
|
|
if (w_req_mem_valid && r.mem_cnt.read() < 4) {
|
| 343 |
|
|
if (MEM_DELAY[r.mem_cnt.read()].rdy_wait == 0) {
|
| 344 |
|
|
if (MEM_DELAY[r.mem_cnt.read()].valid_wait == 0) {
|
| 345 |
|
|
v.mem_state = 3;
|
| 346 |
|
|
v.mem_raddr = wb_req_mem_addr;
|
| 347 |
|
|
w_req_mem_ready = 1;
|
| 348 |
|
|
v.mem_cnt = r.mem_cnt.read() + 1;
|
| 349 |
|
|
} else {
|
| 350 |
|
|
v.mem_state = 2;
|
| 351 |
|
|
v.mem_wait_cnt = MEM_DELAY[r.mem_cnt.read()].valid_wait;
|
| 352 |
|
|
}
|
| 353 |
|
|
} else {
|
| 354 |
|
|
v.mem_state = 1;
|
| 355 |
|
|
v.mem_wait_cnt = MEM_DELAY[r.mem_cnt.read()].rdy_wait;
|
| 356 |
|
|
}
|
| 357 |
|
|
}
|
| 358 |
|
|
break;
|
| 359 |
|
|
case 1:
|
| 360 |
|
|
v.mem_wait_cnt = r.mem_wait_cnt.read() - 1;
|
| 361 |
|
|
if (r.mem_wait_cnt.read() == 1) {
|
| 362 |
|
|
if (w_req_mem_valid) {
|
| 363 |
|
|
v.mem_raddr = wb_req_mem_addr;
|
| 364 |
|
|
w_req_mem_ready = 1;
|
| 365 |
|
|
v.mem_cnt = r.mem_cnt.read() + 1;
|
| 366 |
|
|
if (MEM_DELAY[r.mem_cnt.read()].valid_wait == 0) {
|
| 367 |
|
|
v.mem_state = 3;
|
| 368 |
|
|
} else {
|
| 369 |
|
|
v.mem_state = 2;
|
| 370 |
|
|
v.mem_wait_cnt = MEM_DELAY[r.mem_cnt.read()].valid_wait;
|
| 371 |
|
|
}
|
| 372 |
|
|
} else {
|
| 373 |
|
|
v.mem_state = 0;
|
| 374 |
|
|
}
|
| 375 |
|
|
}
|
| 376 |
|
|
break;
|
| 377 |
|
|
case 2:
|
| 378 |
|
|
v.mem_wait_cnt = r.mem_wait_cnt.read() - 1;
|
| 379 |
|
|
if (r.mem_wait_cnt.read() == 1) {
|
| 380 |
|
|
v.mem_state = 3;
|
| 381 |
|
|
}
|
| 382 |
|
|
break;
|
| 383 |
|
|
case 3:
|
| 384 |
|
|
w_resp_mem_data_valid = 1;
|
| 385 |
|
|
if (r.mem_raddr.read() == 0x100008f0) {
|
| 386 |
|
|
wb_resp_mem_data = 0xffdff06fea9ff0efull;
|
| 387 |
|
|
} else if (r.mem_raddr.read() == 0x100007b0) {
|
| 388 |
|
|
wb_resp_mem_data = 0xfa0a0a1300004a17;
|
| 389 |
|
|
}
|
| 390 |
|
|
|
| 391 |
|
|
if (w_req_mem_valid && r.mem_cnt.read() < 4) {
|
| 392 |
|
|
if (MEM_DELAY[r.mem_cnt.read()].rdy_wait == 0) {
|
| 393 |
|
|
if (MEM_DELAY[r.mem_cnt.read()].valid_wait == 0) {
|
| 394 |
|
|
v.mem_state = 3;
|
| 395 |
|
|
v.mem_raddr = wb_req_mem_addr;
|
| 396 |
|
|
w_req_mem_ready = 1;
|
| 397 |
|
|
v.mem_cnt = r.mem_cnt.read() + 1;
|
| 398 |
|
|
} else {
|
| 399 |
|
|
v.mem_state = 2;
|
| 400 |
|
|
v.mem_wait_cnt = MEM_DELAY[r.mem_cnt.read()].valid_wait;
|
| 401 |
|
|
}
|
| 402 |
|
|
} else {
|
| 403 |
|
|
v.mem_state = 1;
|
| 404 |
|
|
v.mem_wait_cnt = MEM_DELAY[r.mem_cnt.read()].rdy_wait;
|
| 405 |
|
|
}
|
| 406 |
|
|
} else {
|
| 407 |
|
|
v.mem_state = 0;
|
| 408 |
|
|
}
|
| 409 |
|
|
break;
|
| 410 |
|
|
default:;
|
| 411 |
|
|
}
|
| 412 |
|
|
|
| 413 |
|
|
|
| 414 |
|
|
}
|
| 415 |
|
|
#endif
|
| 416 |
|
|
|
| 417 |
|
|
} // namespace debugger
|
| 418 |
|
|
|
