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sergeykhbr |
/**
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* @file
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* @brief Debug port.
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* @details Must be connected to DSU.
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*/
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#ifndef __DEBUGGER_RIVERLIB_DBG_PORT_H__
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#define __DEBUGGER_RIVERLIB_DBG_PORT_H__
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#include <systemc.h>
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#include "../river_cfg.h"
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#include "stacktrbuf.h"
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namespace debugger {
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SC_MODULE(DbgPort) {
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sc_in<bool> i_clk; // CPU clock
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sc_in<bool> i_nrst; // Reset. Active LOW.
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// "RIVER" Debug interface
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sc_in<bool> i_dport_valid; // Debug access from DSU is valid
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sc_in<bool> i_dport_write; // Write command flag
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sc_in<sc_uint<2>> i_dport_region; // Registers region ID: 0=CSR; 1=IREGS; 2=Control
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sc_in<sc_uint<12>> i_dport_addr; // Register idx
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sc_in<sc_uint<RISCV_ARCH>> i_dport_wdata; // Write value
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sc_out<bool> o_dport_ready; // Response is ready
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sc_out<sc_uint<RISCV_ARCH>> o_dport_rdata; // Response value
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// CPU debugging signals:
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sc_out<sc_uint<12>> o_core_addr; // Address of the sub-region register
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sc_out<sc_uint<RISCV_ARCH>> o_core_wdata; // Write data
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sc_out<bool> o_csr_ena; // Region 0: Access to CSR bank is enabled.
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sc_out<bool> o_csr_write; // Region 0: CSR write enable
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sc_in<sc_uint<RISCV_ARCH>> i_csr_rdata; // Region 0: CSR read value
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sc_out<bool> o_ireg_ena; // Region 1: Access to integer register bank is enabled
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sc_out<bool> o_ireg_write; // Region 1: Integer registers bank write pulse
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sc_out<bool> o_npc_write; // Region 1: npc write enable
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sc_in<sc_uint<RISCV_ARCH>> i_ireg_rdata; // Region 1: Integer register read value
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_pc; // Region 1: Instruction pointer
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_npc; // Region 1: Next Instruction pointer
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sc_in<bool> i_e_valid; // Stepping control signal
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sc_in<bool> i_e_call; // pseudo-instruction CALL
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sc_in<bool> i_e_ret; // pseudo-instruction RET
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sc_in<bool> i_m_valid; // To compute number of valid executed instruction
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sc_out<sc_uint<64>> o_clock_cnt; // Number of clocks excluding halt state
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sc_out<sc_uint<64>> o_executed_cnt; // Number of executed instructions
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sc_out<bool> o_halt; // Halt signal is equal to hold pipeline
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sc_in<bool> i_ebreak; // ebreak instruction decoded
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sc_out<bool> o_break_mode; // Behaviour on EBREAK instruction: 0 = halt; 1 = generate trap
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sc_out<bool> o_br_fetch_valid; // Fetch injection address/instr are valid
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_br_address_fetch; // Fetch injection address to skip ebreak instruciton only once
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sc_out<sc_uint<32>> o_br_instr_fetch; // Real instruction value that was replaced by ebreak
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// Cache debug signals:
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sc_in<sc_uint<2>> i_istate; // ICache transaction state
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sc_in<sc_uint<2>> i_dstate; // DCache transaction state
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sc_in<sc_uint<2>> i_cstate; // CacheTop state machine value
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sc_in<sc_biguint<DBG_FETCH_TRACE_SIZE*64>> i_instr_buf; // todo: remove it
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void comb();
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void registers();
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SC_HAS_PROCESS(DbgPort);
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DbgPort(sc_module_name name_);
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virtual ~DbgPort();
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void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
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private:
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struct RegistersType {
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sc_signal<bool> ready;
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sc_signal<bool> halt;
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sc_signal<bool> breakpoint;
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sc_signal<bool> stepping_mode;
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sc_signal<sc_uint<RISCV_ARCH>> stepping_mode_cnt;
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sc_signal<bool> trap_on_break;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> br_address_fetch;
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sc_signal<sc_uint<32>> br_instr_fetch;
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sc_signal<bool> br_fetch_valid;
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sc_signal<sc_uint<RISCV_ARCH>> rdata;
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sc_signal<sc_uint<RISCV_ARCH>> stepping_mode_steps; // Number of steps before halt in stepping mode
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sc_signal<sc_uint<64>> clock_cnt; // Timer in clocks.
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sc_signal<sc_uint<64>> executed_cnt; // Number of valid executed instructions
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sc_signal<sc_uint<5>> stack_trace_cnt; // Stack trace buffer counter (Log2[CFG_STACK_TRACE_BUF_SIZE])
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sc_signal<bool> rd_trbuf_ena;
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sc_signal<bool> rd_trbuf_addr0;
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} v, r;
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sc_signal<sc_uint<5>> wb_stack_raddr;
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sc_signal<sc_biguint<2*BUS_ADDR_WIDTH>> wb_stack_rdata;
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sc_signal<bool> w_stack_we;
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sc_signal<sc_uint<5>> wb_stack_waddr;
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sc_signal<sc_biguint<2*BUS_ADDR_WIDTH>> wb_stack_wdata;
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StackTraceBuffer *trbuf0;
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};
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} // namespace debugger
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#endif // __DEBUGGER_RIVERLIB_DBG_PORT_H__
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