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sergeykhbr |
/**
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* @file
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* @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* @brief CPU pipeline implementation.
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*/
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#ifndef __DEBUGGER_RIVERLIB_PROC_H__
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#define __DEBUGGER_RIVERLIB_PROC_H__
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#include <systemc.h>
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#include "../river_cfg.h"
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#include "fetch.h"
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#include "decoder.h"
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#include "execute.h"
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#include "memaccess.h"
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#include "execute.h"
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#include "regibank.h"
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#include "csr.h"
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#include "br_predic.h"
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#include "dbg_port.h"
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#include <fstream>
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namespace debugger {
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SC_MODULE(Processor) {
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sc_in<bool> i_clk; // CPU clock
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sc_in<bool> i_nrst; // Reset. Active LOW
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// Control path:
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sc_in<bool> i_req_ctrl_ready; // ICache is ready to accept request
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sc_out<bool> o_req_ctrl_valid; // Request to ICache is valid
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_req_ctrl_addr; // Requesting address to ICache
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sc_in<bool> i_resp_ctrl_valid; // ICache response is valid
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_resp_ctrl_addr; // Response address must be equal to the latest request address
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sc_in<sc_uint<32>> i_resp_ctrl_data; // Read value
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sc_out<bool> o_resp_ctrl_ready; // Core is ready to accept response from ICache
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// Data path:
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sc_in<bool> i_req_data_ready; // DCache is ready to accept request
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sc_out<bool> o_req_data_valid; // Request to DCache is valid
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sc_out<bool> o_req_data_write; // Read/Write transaction
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sc_out<sc_uint<2>> o_req_data_size; // Size [Bytes]: 0=1B; 1=2B; 2=4B; 3=8B
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sc_out<sc_uint<BUS_ADDR_WIDTH>> o_req_data_addr; // Requesting address to DCache
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sc_out<sc_uint<RISCV_ARCH>> o_req_data_data; // Writing value
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sc_in<bool> i_resp_data_valid; // DCache response is valid
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sc_in<sc_uint<BUS_ADDR_WIDTH>> i_resp_data_addr; // DCache response address must be equal to the latest request address
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sc_in<sc_uint<RISCV_ARCH>> i_resp_data_data; // Read value
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sc_out<bool> o_resp_data_ready; // Core is ready to accept response from DCache
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// External interrupt pin
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sc_in<bool> i_ext_irq; // PLIC interrupt accordingly with spec
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sc_out<sc_uint<64>> o_time; // Clock/Step counter depending attribute "GenerateRef"
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// Debug interface
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sc_in<bool> i_dport_valid; // Debug access from DSU is valid
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sc_in<bool> i_dport_write; // Write command flag
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sc_in<sc_uint<2>> i_dport_region; // Registers region ID: 0=CSR; 1=IREGS; 2=Control
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sc_in<sc_uint<12>> i_dport_addr; // Register idx
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sc_in<sc_uint<RISCV_ARCH>> i_dport_wdata; // Write value
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sc_out<bool> o_dport_ready; // Response is ready
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sc_out<sc_uint<RISCV_ARCH>> o_dport_rdata; // Response value
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// Cache debug signals:
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sc_in<sc_uint<2>> i_istate; // ICache transaction state
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sc_in<sc_uint<2>> i_dstate; // DCache transaction state
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sc_in<sc_uint<2>> i_cstate; // CacheTop state machine value
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void comb();
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void negedge_dbg_print();
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void generateRef(bool v);
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void generateVCD(sc_trace_file *i_vcd, sc_trace_file *o_vcd);
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SC_HAS_PROCESS(Processor);
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Processor(sc_module_name name_);
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virtual ~Processor();
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private:
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struct FetchType {
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sc_signal<bool> req_fire;
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sc_signal<bool> valid;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc;
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sc_signal<sc_uint<32>> instr;
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sc_signal<bool> imem_req_valid;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> imem_req_addr;
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sc_signal<bool> predict_miss;
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sc_signal<bool> pipeline_hold;
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sc_signal<sc_biguint<DBG_FETCH_TRACE_SIZE*64>> instr_buf;
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};
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struct InstructionDecodeType {
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc;
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sc_signal<sc_uint<32>> instr;
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sc_signal<bool> instr_valid;
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sc_signal<bool> memop_store;
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sc_signal<bool> memop_load;
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sc_signal<bool> memop_sign_ext;
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sc_signal<sc_uint<2>> memop_size;
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sc_signal<bool> rv32; // 32-bits instruction
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sc_signal<bool> unsigned_op; // Unsigned operands
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sc_signal<sc_bv<ISA_Total>> isa_type;
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sc_signal<sc_bv<Instr_Total>> instr_vec;
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sc_signal<bool> exception;
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};
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struct ExecuteType {
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sc_signal<bool> valid;
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sc_signal<sc_uint<32>> instr;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> npc;
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sc_signal<sc_uint<5>> radr1;
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sc_signal<sc_uint<5>> radr2;
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sc_signal<sc_uint<5>> res_addr;
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sc_signal<sc_uint<RISCV_ARCH>> res_data;
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sc_signal<bool> trap_ena; // Trap pulse
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sc_signal<sc_uint<5>> trap_code; // bit[4] : 1=interrupt; 0=exception; bits[3:0]=code
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> trap_pc; // trap on pc
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sc_signal<bool> xret;
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sc_signal<sc_uint<12>> csr_addr;
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sc_signal<bool> csr_wena;
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sc_signal<sc_uint<RISCV_ARCH>> csr_wdata;
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sc_signal<bool> memop_sign_ext;
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sc_signal<bool> memop_load;
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sc_signal<bool> memop_store;
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sc_signal<sc_uint<2>> memop_size;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> memop_addr;
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sc_signal<bool> pipeline_hold; // Hold pipeline from Execution stage
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sc_signal<bool> breakpoint;
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sc_signal<bool> call; // pseudo-instruction CALL
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sc_signal<bool> ret; // pseudo-instruction RET
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};
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struct MemoryType {
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sc_signal<bool> valid;
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sc_signal<sc_uint<32>> instr;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc;
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sc_signal<bool> pipeline_hold;
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};
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struct WriteBackType {
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> pc;
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sc_signal<bool> wena;
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sc_signal<sc_uint<5>> waddr;
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sc_signal<sc_uint<RISCV_ARCH>> wdata;
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};
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struct IntRegsType {
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sc_signal<sc_uint<RISCV_ARCH>> rdata1;
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sc_signal<sc_uint<RISCV_ARCH>> rdata2;
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sc_signal<sc_uint<RISCV_ARCH>> dport_rdata;
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sc_signal<sc_uint<RISCV_ARCH>> ra; // Return address
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} ireg;
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struct CsrType {
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sc_signal<sc_uint<RISCV_ARCH>> rdata;
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sc_signal<sc_uint<RISCV_ARCH>> dport_rdata;
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sc_signal<bool> ie; // Interrupt enable bit
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> mtvec;// Interrupt descriptor table
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sc_signal<sc_uint<2>> mode; // Current processor mode
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} csr;
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struct DebugType {
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sc_signal<sc_uint<12>> core_addr; // Address of the sub-region register
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sc_signal<sc_uint<RISCV_ARCH>> core_wdata; // Write data
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sc_signal<bool> csr_ena; // Region 0: Access to CSR bank is enabled.
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sc_signal<bool> csr_write; // Region 0: CSR write enable
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sc_signal<bool> ireg_ena; // Region 1: Access to integer register bank is enabled
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sc_signal<bool> ireg_write; // Region 1: Integer registers bank write pulse
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sc_signal<bool> npc_write; // Region 1: npc write enable
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sc_signal<bool> halt; // Halt signal is equal to hold pipeline
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sc_signal<sc_uint<64>> clock_cnt; // Number of clocks excluding halt state
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sc_signal<sc_uint<64>> executed_cnt; // Number of executed instruction
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sc_signal<bool> break_mode; // Behaviour on EBREAK instruction: 0 = halt; 1 = generate trap
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sc_signal<bool> br_fetch_valid; // Fetch injection address/instr are valid
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> br_address_fetch; // Fetch injection address to skip ebreak instruciton only once
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sc_signal<sc_uint<32>> br_instr_fetch; // Real instruction value that was replaced by ebreak
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} dbg;
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/** 5-stages CPU pipeline */
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struct PipelineType {
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FetchType f; // Fetch instruction stage
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InstructionDecodeType d; // Decode instruction stage
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ExecuteType e; // Execute instruction
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MemoryType m; // Memory load/store
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WriteBackType w; // Write back registers value
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} w;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> wb_npc_predict;
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sc_signal<sc_uint<5>> wb_ireg_dport_addr;
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sc_signal<sc_uint<BUS_ADDR_WIDTH>> wb_exec_dport_npc;
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sc_signal<bool> w_fetch_pipeline_hold;
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sc_signal<bool> w_any_pipeline_hold;
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sc_signal<bool> w_exec_pipeline_hold;
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InstrFetch *fetch0;
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InstrDecoder *dec0;
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InstrExecute *exec0;
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MemAccess *mem0;
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BranchPredictor *predic0;
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RegIntBank *iregs0;
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CsrRegs *csr0;
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DbgPort *dbg0;
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/** Used only for reference trace generation to compare with
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functional model */
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bool generate_ref_;
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char tstr[1024];
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ofstream *reg_dbg;
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ofstream *mem_dbg;
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bool mem_dbg_write_flag;
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uint64_t dbg_mem_value_mask;
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uint64_t dbg_mem_write_value;
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};
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} // namespace debugger
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#endif // __DEBUGGER_RIVERLIB_PROC_H__
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