URL
https://opencores.org/ocsvn/riscv_vhdl/riscv_vhdl/trunk
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
5 |
sergeykhbr |
/** @page gpio_page GPIO Controller
|
| 2 |
|
|
|
| 3 |
|
|
@section gpio_regs GPIO registers mapping
|
| 4 |
|
|
|
| 5 |
|
|
GPIO Controller acts like a slave AMBA AXI4 device that is directly mapped
|
| 6 |
|
|
into physical memory. Default address location for our implementation
|
| 7 |
|
|
is defined by 0x80000000. Memory size is 4 KB.
|
| 8 |
|
|
|
| 9 |
|
|
@par LED register (0x000).
|
| 10 |
|
|
|
| 11 |
|
|
|Bits|Type| Reset |Field Name| Bits | Description
|
| 12 |
|
|
|:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
| 13 |
|
|
| 24 | RW | 24h'0 | rsrv | 24 | Reserved
|
| 14 |
|
|
| 8 | RW | 8h'0 | led | 7:0 | LEDs. Written value directly assigned on SoC output pins and can be used as test signals.
|
| 15 |
|
|
|
| 16 |
|
|
@par DIP register (0x004).
|
| 17 |
|
|
|
| 18 |
|
|
|Bits|Type| Reset |Field Name| Bits | Description
|
| 19 |
|
|
|:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
| 20 |
|
|
| 28 | RO | 28h'0 | rsrv | 28 | Reserved
|
| 21 |
|
|
| 4 | RO | - | dip | 3:0 | DIPs. Input configuration pins value (Read-Only). Configuration pin meaning depends of the used FW.
|
| 22 |
|
|
|
| 23 |
|
|
@par Set of temporary registers (0x008).
|
| 24 |
|
|
|
| 25 |
|
|
|Offset |Bits|Type| Reset | Name | Definition
|
| 26 |
|
|
|:------|:--:|:--:|:-----:|:----:|---------------------------------------------|
|
| 27 |
|
|
|0x008 | 32 | RW | 32h'0 | reg32_2 | Temporary register 2. FW specific register used for debugging purposes.
|
| 28 |
|
|
|0x00C | 32 | RW | 32h'0 | reg32_3 | Temporary register 3.
|
| 29 |
|
|
|0x010 | 32 | RW | 32h'0 | reg32_4 | Temporary register 4.
|
| 30 |
|
|
|0x014 | 32 | RW | 32h'0 | reg32_5 | Temporary register 5.
|
| 31 |
|
|
|0x018 | 32 | RW | 32h'0 | reg32_6 | Temporary register 6.
|
| 32 |
|
|
|
| 33 |
|
|
*/
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.