1 |
5 |
sergeykhbr |
/** @page irqctrl_page Interrupt Controller
|
2 |
|
|
|
3 |
|
|
@section irqmp_overview IRQ assignments
|
4 |
|
|
|
5 |
|
|
IRQ pins configuration is the part of generic constants defined in file
|
6 |
|
|
ambalib/types_amba4.vhd. Number of interrupts and its indexes can
|
7 |
|
|
changed in future releases.
|
8 |
|
|
|
9 |
|
|
| Pin | Name | Description
|
10 |
|
|
|:----:|:----------|:------------------------------------------------------------|
|
11 |
|
|
| 0 | Unused | Zero Interrupt pin is unsued and connected to Ground.
|
12 |
|
|
| 1 | UART1 | Uart 1 IRQ. UART device used this line to signal CPU via Interrupt Controller that new data is available or device ready to accept new Rx data.
|
13 |
|
|
| 2 | ETHMAC | Ethernet IRQ.
|
14 |
|
|
| 3 | GPTIMERS | General Purpose Timers IRQ.
|
15 |
|
|
| 4 | MISS_ACCESS | Memory Miss Access IRQ. This interrupt is generated by AXI Controller in a case of access to unmapped memory region.
|
16 |
|
|
| 5 | GNSSENGINE | Gnss Engine IRQ. Device Specific 1 msec interrupt that schedules critical Navigation Task.
|
17 |
|
|
|
18 |
|
|
@section irqmp_regs IRQ Controller registers mapping
|
19 |
|
|
IRQ Controller acts like a slave AMBA AXI4 device that is directly mapped
|
20 |
|
|
into physical memory. Default address location for our implementation
|
21 |
|
|
is defined by 0x80002000. Memory size is 4 KB.
|
22 |
|
|
|
23 |
|
|
@par Interrupts Mask register (0x000).
|
24 |
|
|
|
25 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
26 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
27 |
|
|
| 32-N | RW | h'0 | reserved | 31:N | Reserved
|
28 |
|
|
| N | RW | all 1 | mask | N-1:0 | IRQ mask. 1 equals interrupt disabled; 0 is enabled.
|
29 |
|
|
|
30 |
|
|
@par Pending Interrupts register (0x004).
|
31 |
|
|
|
32 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
33 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
34 |
|
|
| 32-N | RO | h'0 | reserved | 31:N | Reserved
|
35 |
|
|
| N | RO | 0 | pending | N-1:0 | Pending Bits. 1 signals rised interrupt. This bit is cleared by writing 1 into the register 'Clear IRQ' or writing 1 into 'Lock Register'.
|
36 |
|
|
|
37 |
|
|
@par Clear Interrupt Mask register (0x008).
|
38 |
|
|
|
39 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
40 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
41 |
|
|
| 32-N | WO | h'0 | reserved | 31:N | Reserved
|
42 |
|
|
| N | WO | 0 | clear_bit| N-1:0 | Clear IRQ line. Clear Pending interrupt register bits that are marked with 1s.
|
43 |
|
|
|
44 |
|
|
@par Raise Interrupt Mask register (0x00C).
|
45 |
|
|
|
46 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
47 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
48 |
|
|
| 32-N | WO | h'0 | reserved | 31:N | Reserved
|
49 |
|
|
| N | WO | 0 | raise_irq| N-1:0 | Rise specified IRQ line manually. This register can be used for test and debugging either as for 'system calls'.
|
50 |
|
|
|
51 |
|
|
@par ISR table address (low word) (0x010).
|
52 |
|
|
|
53 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
54 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
55 |
|
|
| 32 | WR | 0 | isr_table| 31:0 | Interrupts table address LSB. This register stores address where located ISR table. This value must be intialized be Software.
|
56 |
|
|
|
57 |
|
|
@par ISR table address (high word) (0x014).
|
58 |
|
|
|
59 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
60 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
61 |
|
|
| 32 | WR | 0 | isr_table| 31:0 | Interrupts table address MSB. This register stores address where located ISR table. This value must be intialized be Software.
|
62 |
|
|
|
63 |
|
|
@par ISR cause code (low word) (0x018).
|
64 |
|
|
|
65 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
66 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
67 |
|
|
| 32 | WR | 0 | dbg_cause| 31:0 | Cause of te Interrupt LSB. This register stores the latest cause of the interrupt. This value is optional and updates by ROM ISR handler in current implementation.
|
68 |
|
|
|
69 |
|
|
@par ISR cause code (high word) (0x01C).
|
70 |
|
|
|
71 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
72 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
73 |
|
|
| 32 | WR | 0 | dbg_cause| 31:0 | Cause of the Interrupt MSB. This register stores the latest cause of the interrupt. This value is optional and updates by ROM ISR handler in current implementation.
|
74 |
|
|
|
75 |
|
|
@par Instruction Pointer before trap (low word) (0x020).
|
76 |
|
|
|
77 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
78 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
79 |
|
|
| 32 | WR | 0 | dbg_epc | 31:0 | npc[31:0] register value before trap . This register stores copy of xEPC value. This value is optional and updates by ROM ISR handler in current implementation.
|
80 |
|
|
|
81 |
|
|
@par Instruction Pointer before trap (high word) (0x024).
|
82 |
|
|
|
83 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
84 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
85 |
|
|
| 32 | WR | 0 | dbg_epc | 31:0 | npc[63:32] register value before trap. This register stores copy of xEPC value. This value is optional and updates by ROM ISR handler in current implementation.
|
86 |
|
|
|
87 |
|
|
@par Lock interrupt register (0x028).
|
88 |
|
|
|
89 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
90 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
91 |
|
|
| 31 | WR | 31h'0 | reserved | 31:1 | Reserved
|
92 |
|
|
| 1 | WR | 1b' | lock | 0 | Lock interrupts. Disabled all interrupts when this bit is 1. All new interrupt request marked as postponed and will be raised when 'lock' signal will be cleared.
|
93 |
|
|
|
94 |
|
|
@par Lock interrupt register (0x02C).
|
95 |
|
|
|
96 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
97 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
98 |
|
|
| 32 | WR | 0 | irq_idx | 31:0 | Interrupt Index. This register stores current interrupt index while in ISR handler. This value is optional and updates by ROM ISR handler in current implementation.
|
99 |
|
|
|
100 |
|
|
|
101 |
|
|
*/
|