1 |
5 |
sergeykhbr |
/** @page uart_page UART
|
2 |
|
|
|
3 |
|
|
@section uart_overview Overview
|
4 |
|
|
|
5 |
|
|
This UART implementation can be additionally configured using the following
|
6 |
|
|
generic parameters.
|
7 |
|
|
|
8 |
|
|
| Name | Default | Description
|
9 |
|
|
|:-----|:---------:|:------------
|
10 |
|
|
|irqx | 0 | Interrupt pin index This value is used only as argument in output Plug'n'Play configuration.
|
11 |
|
|
|fifosz| 16 | FIFO size. Size of the Tx and Rx FIFOs in bytes.
|
12 |
|
|
|
13 |
|
|
@section uart_regs UART registers mapping
|
14 |
|
|
UART acts like a slave AMBA AXI4 device that is directly mapped
|
15 |
|
|
into physical memory. Default address location for our implementation
|
16 |
|
|
is defined by 0x80001000. Memory size is 4 KB.
|
17 |
|
|
|
18 |
|
|
@par Control Status register (0x000).
|
19 |
|
|
|
20 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
21 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
22 |
|
|
| 16 | RW | 16h'0 | Reserved | 31:16 | Reserved.
|
23 |
|
|
| 1 | RW | 1b'0 | parity_bit | 15 | Enable parity checking. Serial port setting setup by SW.
|
24 |
|
|
| 1 | RW | 1b'0 | tx_irq_ena | 14 | Enable Tx Interrupt. Generate interrupt when number of symbol in output FIFO less than defined in Tx Threshold register.
|
25 |
|
|
| 1 | RW | 1b'0 | rx_irq_ena | 13 | Enable Rx Interrupt. Generate interrupt when number of available for reading symbol greater or equalt Rx Threshold register.
|
26 |
|
|
| 3 | RW | 3h'0 | Reserved | 12:10 | Reserved.
|
27 |
|
|
| 1 | RO | 1b'0 | err_stopbit | 9 | Stop Bit Error. This bit is set when the Stoping Bit has the wrnog value.
|
28 |
|
|
| 1 | RO | 1b'0 | err_parity | 8 | Parity Error. This bit is set when the Parity error occurs. Will be automatically cleared by next received symbol if the parity OK.
|
29 |
|
|
| 2 | RW | 2h'0 | Reserved | 7:6 | Reserved.
|
30 |
|
|
| 1 | RO | 1b'1 | rx_fifo_empty | 5 | Receive FIFO is Empty.
|
31 |
|
|
| 1 | RO | 1b'0 | rx_fifo_fifo | 4 | Receive FIFO is Full.
|
32 |
|
|
| 2 | RW | 2h'0 | Reserved | 3:2 | Reserved.
|
33 |
|
|
| 1 | RO | 1b'1 | tx_fifo_empty | 1 | Transmit FIFO is Empty.
|
34 |
|
|
| 1 | RO | 1'b0 | tx_fifo_full | 0 | Transmit FIFO is Full.
|
35 |
|
|
|
36 |
|
|
@par Scaler register (0x004).
|
37 |
|
|
|
38 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
39 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
40 |
|
|
| 32 | RW | 32h'0 | scaler | 31:16 | Scale threshold. This register value is used to transform System Bus clock into port baudrate.
|
41 |
|
|
|
42 |
|
|
@par Data register (0x010).
|
43 |
|
|
|
44 |
|
|
| Bits |Type| Reset |Field Name| Bits | Description
|
45 |
|
|
|:----:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
|
46 |
|
|
| 24 | RW | 28h'0 | Reserved | 31:8 | Reserved.
|
47 |
|
|
| 8 | RW | 8h'0 | data | 7:0 | Data. Access to Tx/Rx FIFO data. Writing into this register put data into Tx FIFO. Reading is accomplished from Rx FIFO.
|
48 |
|
|
|
49 |
|
|
|
50 |
|
|
*/
|