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/** @page pnp_page Plug'n'Play support module
 
 @section pnp_regs PNP registers mapping
 PNP module acts like a slave AMBA AXI4 device that is directly mapped
 into physical memory. Default address location for our implementation
 is defined as 0xFFFFF000. Memory size is 4 KB.
 
 @par HW ID register (0x000).
 
 |Bits|Type| Reset |Field Name| Bits  | Description
 |:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
 | 32 | RO | CFG_HW_ID  | hw_id  | 31:0   | HW ID. Read only SoC identificator. Now it contains manually specified date in hex-format. Can be changed via CFG_HW_ID configuration parameter.
 
 @par FW ID register (0x004).
 
 |Bits|Type| Reset |Field Name| Bits  | Description
 |:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
 | 32 | RW | 32'h0  | fw_id  | 31:0   | Firmware ID. This value is modified by bootloader or user's firmware. Can be used to simplify firmware version tracking.
 
 @par AXI Slots Configuration Register (0x008).
 
 |Bits|Type| Reset |Field Name| Bits  | Description
 |:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
 | 8  | RO | CFG_TECH  | tech  | 7:0   | Technology ID. Read Only value specifies the target configuration. Possible values: inferred, virtex6, kintex7. Other targets ID could be added in a future.
 | 8  | RO | CFG_NASTI_SLAVES_TOTAL  | slaves  | 15:8   | Total number of AXI slave slots. This value specifies maximum number of slave devices connected to the system bus. If device wasn't connected the dummy signals must be applied to the slave interface otherwise SoC behaviour isn't defined.
 | 8  | RO | CFG_NASTI_MASTER_TOTAL  | masters  | 23:16   | Total number of AXI master slots. This value specifies maximum number of master devices connected to the system bus. Slot signals cannot be unconnected either.
 | 8  | RO | 8'h0  | adc_detect  | 31:24   | ADC clock detector. This value is used by GNSS firmware to detect presence of the ADC clock frequency that allows to detect presence of the RF front-end board.
 
 @par Debug IDT register (0x010).
 
 |Bits|Type| Reset |Field Name| Bits  | Description
 |:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
 | 64 | RW | 64'h0  | idt  | 63:0   | Debug IDT. This is debug register used by GNSS firmware to store debug information.
 
 @par Debug Memory Allocation Pointer register (0x018).
 
 |Bits|Type| Reset |Field Name| Bits  | Description
 |:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
 | 64 | RW | 64'h0  | malloc_addr  | 63:0   | Memory Allocation Pointer. This is debug register used by GNSS firmware to store 'heap' pointer and allows to debug memory management.
 
 @par Debug Memory Allocation Size register (0x020).
 
 |Bits|Type| Reset |Field Name| Bits  | Description
 |:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
 | 64 | RW | 64'h0  | malloc_size  | 63:0   | Memory Allocation size. This is debug register used by GNSS firmware to store total allocated memory size.
 
 @par Debug Firmware1 register (0x028).
 
 |Bits|Type| Reset |Field Name| Bits  | Description
 |:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
 | 64 | RW | 64'h0  | fwdbg1  | 63:0   | Firmware debug1. This is debug register used by GNSS firmware to store temporary information.
 
 @section pnp_descriptior PNP Device descriptors
 Our SoC implementaion provides capability to read in real-time information
 about mapped devices. Such information is packed into special device
 descriptors. Now we can provide 3 types of descriptors:
    - Master device descriptor
    - Slave device descriptor
    - Custom device descriptor
 
 All descriptors mapped sequentually starting from 0xFFFFF040. Each descriptor
 implements field 'size' in Bytes that specifies offset to the next mapped
 descriptor.
 
 @par Master device descriptor
 
 | Bits    | Description
 |:-------:|:------------------------------------------------------------|
 | [7:0]   | Descriptor Size. Read Only value specifies size in Bytes of the current descriptor. This value should be used as offset to the next descriptor. Master descriptor size is hardwired to PNP_CFG_MASTER_DESCR_BYTES value (8'h08).
 | [9:8]   | Descriptor Type. Master descriptor type is hardwired to PNP_CFG_TYPE_MASTER value (2'b01).
 | [31:10] | Reserved.
 | [47:32] | Device ID. Unique Master identificator.
 | [63:48] | Vendor ID. Unique Vendor identificator.
 
 @par Slave device descriptor
 
 | Bits      | Description
 |:---------:|:------------------------------------------------------------|
 | [7:0]     | Descriptor Size. Read Only value specifies size in Bytes of the current descriptor. This value should be used as offset to the next descriptor. Slave descriptor size is hardwired to PNP_CFG_SLAVE_DESCR_BYTES value (8'h10).
 | [9:8]     | Descriptor Type. Slave descriptor type is hardwired to PNP_CFG_TYPE_SLAVE value (2'b10).
 | [15:10]   | Reserved.
 | [23:16]   | IRQ ID. Interrupt line index assigned to the device.
 | [31:24]   | Reserved.
 | [47:32]   | Device ID. Unique Master identificator.
 | [63:48]   | Vendor ID. Unique Vendor identificator.
 | [75:64]   | zero. Hardwired to X"000".
 | [95:76]   | Base Address Mask specifies the memory region allocated for the device.
 | [107:96]  | zero. Hardwired to X"000".
 | [127:108] | Base Address value of the device.
 
 
*/

Line No.	Rev	Author	Line
1	5	sergeykhbr	`/** @page pnp_page Plug'n'Play support module`
2
3			`@section pnp_regs PNP registers mapping`
4			`PNP module acts like a slave AMBA AXI4 device that is directly mapped`
5			`into physical memory. Default address location for our implementation`
6			`is defined as 0xFFFFF000. Memory size is 4 KB.`
7
8			`@par HW ID register (0x000).`
9
10			`\|Bits\|Type\| Reset \|Field Name\| Bits \| Description`
11			`\|:--:\|:--:\|:-----:\|:---------\|:-----:\|:------------------------------------------------------------\|`
12			`\| 32 \| RO \| CFG_HW_ID \| hw_id \| 31:0 \| HW ID. Read only SoC identificator. Now it contains manually specified date in hex-format. Can be changed via CFG_HW_ID configuration parameter.`
13
14			`@par FW ID register (0x004).`
15
16			`\|Bits\|Type\| Reset \|Field Name\| Bits \| Description`
17			`\|:--:\|:--:\|:-----:\|:---------\|:-----:\|:------------------------------------------------------------\|`
18			`\| 32 \| RW \| 32'h0 \| fw_id \| 31:0 \| Firmware ID. This value is modified by bootloader or user's firmware. Can be used to simplify firmware version tracking.`
19
20			`@par AXI Slots Configuration Register (0x008).`
21
22			`\|Bits\|Type\| Reset \|Field Name\| Bits \| Description`
23			`\|:--:\|:--:\|:-----:\|:---------\|:-----:\|:------------------------------------------------------------\|`
24			`\| 8 \| RO \| CFG_TECH \| tech \| 7:0 \| Technology ID. Read Only value specifies the target configuration. Possible values: inferred, virtex6, kintex7. Other targets ID could be added in a future.`
25			`\| 8 \| RO \| CFG_NASTI_SLAVES_TOTAL \| slaves \| 15:8 \| Total number of AXI slave slots. This value specifies maximum number of slave devices connected to the system bus. If device wasn't connected the dummy signals must be applied to the slave interface otherwise SoC behaviour isn't defined.`
26			`\| 8 \| RO \| CFG_NASTI_MASTER_TOTAL \| masters \| 23:16 \| Total number of AXI master slots. This value specifies maximum number of master devices connected to the system bus. Slot signals cannot be unconnected either.`
27			`\| 8 \| RO \| 8'h0 \| adc_detect \| 31:24 \| ADC clock detector. This value is used by GNSS firmware to detect presence of the ADC clock frequency that allows to detect presence of the RF front-end board.`
28
29			`@par Debug IDT register (0x010).`
30
31			`\|Bits\|Type\| Reset \|Field Name\| Bits \| Description`
32			`\|:--:\|:--:\|:-----:\|:---------\|:-----:\|:------------------------------------------------------------\|`
33			`\| 64 \| RW \| 64'h0 \| idt \| 63:0 \| Debug IDT. This is debug register used by GNSS firmware to store debug information.`
34
35			`@par Debug Memory Allocation Pointer register (0x018).`
36
37			`\|Bits\|Type\| Reset \|Field Name\| Bits \| Description`
38			`\|:--:\|:--:\|:-----:\|:---------\|:-----:\|:------------------------------------------------------------\|`
39			`\| 64 \| RW \| 64'h0 \| malloc_addr \| 63:0 \| Memory Allocation Pointer. This is debug register used by GNSS firmware to store 'heap' pointer and allows to debug memory management.`
40
41			`@par Debug Memory Allocation Size register (0x020).`
42
43			`\|Bits\|Type\| Reset \|Field Name\| Bits \| Description`
44			`\|:--:\|:--:\|:-----:\|:---------\|:-----:\|:------------------------------------------------------------\|`
45			`\| 64 \| RW \| 64'h0 \| malloc_size \| 63:0 \| Memory Allocation size. This is debug register used by GNSS firmware to store total allocated memory size.`
46
47			`@par Debug Firmware1 register (0x028).`
48
49			`\|Bits\|Type\| Reset \|Field Name\| Bits \| Description`
50			`\|:--:\|:--:\|:-----:\|:---------\|:-----:\|:------------------------------------------------------------\|`
51			`\| 64 \| RW \| 64'h0 \| fwdbg1 \| 63:0 \| Firmware debug1. This is debug register used by GNSS firmware to store temporary information.`
52
53			`@section pnp_descriptior PNP Device descriptors`
54			`Our SoC implementaion provides capability to read in real-time information`
55			`about mapped devices. Such information is packed into special device`
56			`descriptors. Now we can provide 3 types of descriptors:`
57			`- Master device descriptor`
58			`- Slave device descriptor`
59			`- Custom device descriptor`
60
61			`All descriptors mapped sequentually starting from 0xFFFFF040. Each descriptor`
62			`implements field 'size' in Bytes that specifies offset to the next mapped`
63			`descriptor.`
64
65			`@par Master device descriptor`
66
67			`\| Bits \| Description`
68			`\|:-------:\|:------------------------------------------------------------\|`
69			`\| [7:0] \| Descriptor Size. Read Only value specifies size in Bytes of the current descriptor. This value should be used as offset to the next descriptor. Master descriptor size is hardwired to PNP_CFG_MASTER_DESCR_BYTES value (8'h08).`
70			`\| [9:8] \| Descriptor Type. Master descriptor type is hardwired to PNP_CFG_TYPE_MASTER value (2'b01).`
71			`\| [31:10] \| Reserved.`
72			`\| [47:32] \| Device ID. Unique Master identificator.`
73			`\| [63:48] \| Vendor ID. Unique Vendor identificator.`
74
75			`@par Slave device descriptor`
76
77			`\| Bits \| Description`
78			`\|:---------:\|:------------------------------------------------------------\|`
79			`\| [7:0] \| Descriptor Size. Read Only value specifies size in Bytes of the current descriptor. This value should be used as offset to the next descriptor. Slave descriptor size is hardwired to PNP_CFG_SLAVE_DESCR_BYTES value (8'h10).`
80			`\| [9:8] \| Descriptor Type. Slave descriptor type is hardwired to PNP_CFG_TYPE_SLAVE value (2'b10).`
81			`\| [15:10] \| Reserved.`
82			`\| [23:16] \| IRQ ID. Interrupt line index assigned to the device.`
83			`\| [31:24] \| Reserved.`
84			`\| [47:32] \| Device ID. Unique Master identificator.`
85			`\| [63:48] \| Vendor ID. Unique Vendor identificator.`
86			`\| [75:64] \| zero. Hardwired to X"000".`
87			`\| [95:76] \| Base Address Mask specifies the memory region allocated for the device.`
88			`\| [107:96] \| zero. Hardwired to X"000".`
89			`\| [127:108] \| Base Address value of the device.`
90
91
92			`*/`

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[/] [riscv_vhdl/] [trunk/] [docs/] [doxygen/] [06f_pnp.doxy] - Blame information for rev 5