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/** @page spiflash_page SPI Controller
 
 @section spiflash_overview Overview
 
 This SPI controller is the specially developed module to support the
 following Flash memory ICs:
      \li Microchip 25AA1024 and 25LC1024.
      \li 1636PP52Y
 
 Read/write access to the controller's registers directly generate SPI
 signals sequence (nCS, SDO, SCK) to form read/write transaction request.
 AXI4 bus transaction is holded and CPU (or DMA) waits the response from the
 SPI interface all the time while SPI is active.
 
 The following generic parameters are used to configure the SPI controllers:
 
 | Name  | Default   | Description
 |:------|:---------:|:------------
 | xaddr | 0         | Base address. Bus address bits [31:12] allocated for the controller.
 | xmask | 16#fffff# | Address mask. Bus address mask bits used to specify allocated size (default 4 KB, minimum).
 
 @section spiflash_regs Mapped Registers
 
 SPI controller module acts like a slave AMBA AXI4 device that is directly mapped
 into physical memory. Default address location for this implementation
 is defined as 0x00200000 with allocated memory size 256 KB.
 
 The lower 128 KB region is used for the direct access to the external Flash
 memory via SPI interface. The control registers are mapped at offset 0x20000
 (upper 128 KB).
 
 @par Flash Region 128 KB (0x00000..0x20000).
 
 Read access to this region directly converted into SPI read request.
 4 and 8-bytes read requests is supported by this SPI controller.
 
 Write requests to this region doesn't generate any SPI activity. All write data
 is writing ONLY into the local Page Buffer (256 Bytes length). 4 or 8-bytes write
 access is supported. Address bits [31:8] are ignored and must be specified on
 write access into Flash Page Write register.
 
 @par Scaler register (0x20000).
 
 |Bits|Type| Reset |Field Name| Bits  | Description
 |:--:|:--:|:-----:|:---------|:-----:|:------------------------------------------------------------|
 | 32 | RW | 0     | scaler   | 31:0  | Clock Scaling Rate. RW register is specifies the SPI frequency relative Bus Frequency. Fspi = Fbus / (2*scaler).
 
 @par Flash STATUS (0x20010).
 
 |Bits|Type| Field Name | Bits  | Description
 |:--:|:--:|:-----------|:-----:|:------------------------------------------------------------|
 | 32 | RW |  STATUS    | 7:0   | STATUS. Flash STATUS register read via SPI. Read Command ID = 0x05; Write Command ID = 0x01.
 
 @par Flash ID (0x20018).
 
 |Bits|Type| Field Name| Bits  | Description
 |:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
 | 8  | RO |  ID       | 7:0   | Manufacturer ID. Read Only value read from Flash: 0x29 is the default value of Microchip. Command ID = 0xAB.
 
 @par Flash Write Enable (0x20020).
 
 |Bits|Type| Field Name| Bits  | Description
 |:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
 | 32 | WO |  WE       | 31:0  | Flash Write Enable. Writing to this register generates SPI transasction with command ID = 0x06. Write value is ignored.
 
 @par Flash Page Write (0x20028).
 
 |Bits|Type| Field Name| Bits  | Description
 |:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
 | 8  | WO | ignored   | 7:0   | Ignored.
 | 9  | WO | PAGE_ADDR | 16:8  | Page address. Page Address which is used to store current Page Buffer (256 Bytes) into external Flash. Command ID = 0x02.
 | 15 | WO | ignored   | 31:17 | Ignored.
 
 @par Flash Write Disable (0x20030).
 
 |Bits|Type| Field Name| Bits  | Description
 |:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
 | 32 | WO |  WD       | 31:0  | Flash Write Disable. Writing to this register generates SPI transasction with command ID = 0x04. Write value is ignored.
 
 @par Flash Page Erase (0x20038).
 
 |Bits|Type| Field Name| Bits  | Description
 |:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
 | 24 | WO | PAGE_ADDR | 23:0  | Flash Page Erase. Erase external Flash page with specified address. Command ID = 0x42.
 | 8  | WO | ignored   | 31:24 | Ignored.
 
 @par Flash Sectore Erase (0x20040).
 
 |Bits|Type| Field Name| Bits  | Description
 |:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
 | 24 | WO | SECTOR_ADDR | 23:0  | Flash Sector Erase. Erase external Flash sector with specified address. Command ID = 0xDB.
 | 8  | WO | ignored   | 31:24 | Ignored.
 
 @par Flash Chip Erase (0x20048).
 
 |Bits|Type| Field Name| Bits  | Description
 |:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
 | 32 | WO | ignored   | 31:0   | Chip Erase. Writing any value to this register generates SPI transasction with command ID = 0xC7. Write value is ignored.
 
 @par Deep Power-Down mode (0x20050).
 
 |Bits|Type| Field Name| Bits  | Description
 |:--:|:--:|:----------|:-----:|:------------------------------------------------------------|
 | 32 | WO | ignored   | 31:0   | Deep Power-Down mode. Writing any value to this register generates SPI transasction with command ID = 0xB9 that sends ICs into Power-Down mode. Write value is ignored.
 
 
*/

Line No.	Rev	Author	Line
1	5	sergeykhbr	`/** @page spiflash_page SPI Controller`
2
3			`@section spiflash_overview Overview`
4
5			`This SPI controller is the specially developed module to support the`
6			`following Flash memory ICs:`
7			`\li Microchip 25AA1024 and 25LC1024.`
8			`\li 1636PP52Y`
9
10			`Read/write access to the controller's registers directly generate SPI`
11			`signals sequence (nCS, SDO, SCK) to form read/write transaction request.`
12			`AXI4 bus transaction is holded and CPU (or DMA) waits the response from the`
13			`SPI interface all the time while SPI is active.`
14
15			`The following generic parameters are used to configure the SPI controllers:`
16
17			`\| Name \| Default \| Description`
18			`\|:------\|:---------:\|:------------`
19			`\| xaddr \| 0 \| Base address. Bus address bits [31:12] allocated for the controller.`
20			`\| xmask \| 16#fffff# \| Address mask. Bus address mask bits used to specify allocated size (default 4 KB, minimum).`
21
22			`@section spiflash_regs Mapped Registers`
23
24			`SPI controller module acts like a slave AMBA AXI4 device that is directly mapped`
25			`into physical memory. Default address location for this implementation`
26			`is defined as 0x00200000 with allocated memory size 256 KB.`
27
28			`The lower 128 KB region is used for the direct access to the external Flash`
29			`memory via SPI interface. The control registers are mapped at offset 0x20000`
30			`(upper 128 KB).`
31
32			`@par Flash Region 128 KB (0x00000..0x20000).`
33
34			`Read access to this region directly converted into SPI read request.`
35			`4 and 8-bytes read requests is supported by this SPI controller.`
36
37			`Write requests to this region doesn't generate any SPI activity. All write data`
38			`is writing ONLY into the local Page Buffer (256 Bytes length). 4 or 8-bytes write`
39			`access is supported. Address bits [31:8] are ignored and must be specified on`
40			`write access into Flash Page Write register.`
41
42			`@par Scaler register (0x20000).`
43
44			`\|Bits\|Type\| Reset \|Field Name\| Bits \| Description`
45			`\|:--:\|:--:\|:-----:\|:---------\|:-----:\|:------------------------------------------------------------\|`
46			`\| 32 \| RW \| 0 \| scaler \| 31:0 \| Clock Scaling Rate. RW register is specifies the SPI frequency relative Bus Frequency. Fspi = Fbus / (2*scaler).`
47
48			`@par Flash STATUS (0x20010).`
49
50			`\|Bits\|Type\| Field Name \| Bits \| Description`
51			`\|:--:\|:--:\|:-----------\|:-----:\|:------------------------------------------------------------\|`
52			`\| 32 \| RW \| STATUS \| 7:0 \| STATUS. Flash STATUS register read via SPI. Read Command ID = 0x05; Write Command ID = 0x01.`
53
54			`@par Flash ID (0x20018).`
55
56			`\|Bits\|Type\| Field Name\| Bits \| Description`
57			`\|:--:\|:--:\|:----------\|:-----:\|:------------------------------------------------------------\|`
58			`\| 8 \| RO \| ID \| 7:0 \| Manufacturer ID. Read Only value read from Flash: 0x29 is the default value of Microchip. Command ID = 0xAB.`
59
60			`@par Flash Write Enable (0x20020).`
61
62			`\|Bits\|Type\| Field Name\| Bits \| Description`
63			`\|:--:\|:--:\|:----------\|:-----:\|:------------------------------------------------------------\|`
64			`\| 32 \| WO \| WE \| 31:0 \| Flash Write Enable. Writing to this register generates SPI transasction with command ID = 0x06. Write value is ignored.`
65
66			`@par Flash Page Write (0x20028).`
67
68			`\|Bits\|Type\| Field Name\| Bits \| Description`
69			`\|:--:\|:--:\|:----------\|:-----:\|:------------------------------------------------------------\|`
70			`\| 8 \| WO \| ignored \| 7:0 \| Ignored.`
71			`\| 9 \| WO \| PAGE_ADDR \| 16:8 \| Page address. Page Address which is used to store current Page Buffer (256 Bytes) into external Flash. Command ID = 0x02.`
72			`\| 15 \| WO \| ignored \| 31:17 \| Ignored.`
73
74			`@par Flash Write Disable (0x20030).`
75
76			`\|Bits\|Type\| Field Name\| Bits \| Description`
77			`\|:--:\|:--:\|:----------\|:-----:\|:------------------------------------------------------------\|`
78			`\| 32 \| WO \| WD \| 31:0 \| Flash Write Disable. Writing to this register generates SPI transasction with command ID = 0x04. Write value is ignored.`
79
80			`@par Flash Page Erase (0x20038).`
81
82			`\|Bits\|Type\| Field Name\| Bits \| Description`
83			`\|:--:\|:--:\|:----------\|:-----:\|:------------------------------------------------------------\|`
84			`\| 24 \| WO \| PAGE_ADDR \| 23:0 \| Flash Page Erase. Erase external Flash page with specified address. Command ID = 0x42.`
85			`\| 8 \| WO \| ignored \| 31:24 \| Ignored.`
86
87			`@par Flash Sectore Erase (0x20040).`
88
89			`\|Bits\|Type\| Field Name\| Bits \| Description`
90			`\|:--:\|:--:\|:----------\|:-----:\|:------------------------------------------------------------\|`
91			`\| 24 \| WO \| SECTOR_ADDR \| 23:0 \| Flash Sector Erase. Erase external Flash sector with specified address. Command ID = 0xDB.`
92			`\| 8 \| WO \| ignored \| 31:24 \| Ignored.`
93
94			`@par Flash Chip Erase (0x20048).`
95
96			`\|Bits\|Type\| Field Name\| Bits \| Description`
97			`\|:--:\|:--:\|:----------\|:-----:\|:------------------------------------------------------------\|`
98			`\| 32 \| WO \| ignored \| 31:0 \| Chip Erase. Writing any value to this register generates SPI transasction with command ID = 0xC7. Write value is ignored.`
99
100			`@par Deep Power-Down mode (0x20050).`
101
102			`\|Bits\|Type\| Field Name\| Bits \| Description`
103			`\|:--:\|:--:\|:----------\|:-----:\|:------------------------------------------------------------\|`
104			`\| 32 \| WO \| ignored \| 31:0 \| Deep Power-Down mode. Writing any value to this register generates SPI transasction with command ID = 0xB9 that sends ICs into Power-Down mode. Write value is ignored.`
105
106
107			`*/`

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[/] [riscv_vhdl/] [trunk/] [docs/] [doxygen/] [06g_spiflash.doxy] - Blame information for rev 5