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sergeykhbr |
/******************************************************************************
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* @file
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* @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
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* @author Sergey Khabarov - sergeykhbr@gmail.com
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* @brief AXI4 system bus constants definition
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******************************************************************************/
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#ifndef __AXI_CONST_H__
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#define __AXI_CONST_H__
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#include <inttypes.h>
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typedef uint64_t adr_type;
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static const int AXI4_SYSTEM_CLOCK = 40000000; /// 40 MHz
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#define VENDOR_GNSSSENSOR 0x00F1
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#define GNSSSENSOR_EMPTY 0x5577 /// Dummy device
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#define GNSSSENSOR_ENGINE_STUB 0x0068 /// GNSS Engine stub
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#define GNSSSENSOR_FSE_V2_GPS 0x0069 /// Fast Search Engines Device ID provided by gnsslib
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#define GNSSSENSOR_FSE_V2_GLO 0x006A ///
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#define GNSSSENSOR_FSE_V2_GAL 0x006C ///
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#define GNSSSENSOR_BOOTROM 0x0071 /// Boot ROM Device ID
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#define GNSSSENSOR_FWIMAGE 0x0072 /// FW ROM image Device ID
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#define GNSSSENSOR_SRAM 0x0073 /// Internal SRAM block Device ID
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#define GNSSSENSOR_PNP 0x0074 /// Configuration Registers Module Device ID provided by gnsslib
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#define GNSSSENSOR_SPI_FLASH 0x0075 /// SD-card controller Device ID provided by gnsslib
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#define GNSSSENSOR_GPIO 0x0076 /// General purpose IOs Device ID provided by gnsslib
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#define GNSSSENSOR_RF_CONTROL 0x0077 /// RF front-end controller Device ID provided by gnsslib
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#define GNSSSENSOR_ENGINE 0x0078 /// GNSS Engine Device ID provided by gnsslib
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#define GNSSSENSOR_UART 0x007a /// rs-232 UART Device ID
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#define GNSSSENSOR_ACCELEROMETER 0x007b /// Accelerometer Device ID provided by gnsslib
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#define GNSSSENSOR_GYROSCOPE 0x007c /// Gyroscope Device ID provided by gnsslib
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#define GNSSSENSOR_IRQCTRL 0x007d /// Interrupt controller
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#define GNSSSENSOR_ETHMAC 0x007f
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#define GNSSSENSOR_DSU 0x0080
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#define GNSSSENSOR_GPTIMERS 0x0081
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#define GNSSSENSOR_RECORDER 0x0082
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#define CFG_NASTI_MASTER_CACHED 0
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#define CFG_NASTI_MASTER_UNCACHED 1
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#define CFG_NASTI_MASTER_ETHMAC 2
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#define CFG_NASTI_MASTER_TOTAL 3
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#define MST_DID_EMPTY 0x7755
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#define SLV_DID_EMPTY 0x5577
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// Masters IDs
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#define RISCV_CACHED_TILELINK 0x0500
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#define RISCV_UNCACHED_TILELINK 0x0501
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#define GAISLER_ETH_MAC_MASTER 0x0502
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#define GAISLER_ETH_EDCL_MASTER 0x0503
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#define RISCV_RIVER_CPU 0x0505
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#define PNP_CFG_TYPE_INVALID 0
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#define PNP_CFG_TYPE_MASTER 1
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#define PNP_CFG_TYPE_SLAVE 2
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#define TECH_INFERRED 0
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#define TECH_VIRTEX6 36
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#define TECH_KINTEX7 49
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#ifdef WIN32
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#ifdef __cplusplus
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extern "C" {
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#endif
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void WRITE32(const volatile uint32_t *adr, uint32_t val);
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void WRITE64(const volatile uint64_t *adr, uint64_t val);
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uint8_t READ8(const volatile uint8_t *adr);
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uint16_t READ16(const volatile uint16_t *adr);
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uint32_t READ32(const volatile uint32_t *adr);
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uint64_t READ64(const volatile uint64_t *adr);
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#ifdef __cplusplus
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}
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#endif
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#else
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static inline void WRITE32(const volatile uint32_t *adr, uint32_t val) {
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*((volatile uint32_t *)adr) = val;
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}
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static inline void WRITE64(const volatile uint64_t *adr, uint64_t val) {
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*((volatile uint64_t *)adr) = val;
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}
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static inline uint8_t READ8(const volatile uint8_t *adr) {
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return adr[0];
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}
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static inline uint16_t READ16(const volatile uint16_t *adr) {
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return adr[0];
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}
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static inline uint32_t READ32(const volatile uint32_t *adr) {
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return adr[0];
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}
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static inline uint64_t READ64(const volatile uint64_t *adr) {
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return adr[0];
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}
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#endif
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#endif // __AXI_CONST_H__
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