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sergeykhbr |
// See LICENSE for license details.
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#ifndef RISCV_CSR_ENCODING_H
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#define RISCV_CSR_ENCODING_H
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/** Return address */
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#define COOP_REG_RA 0//(0*sizeof(uint64_t))
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/** Saved registers */
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#define COOP_REG_S0 8//(1*sizeof(uint64_t))
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#define COOP_REG_S1 16//(2*sizeof(uint64_t))
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#define COOP_REG_S2 24//(3*sizeof(uint64_t))
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#define COOP_REG_S3 32//(4*sizeof(uint64_t))
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#define COOP_REG_S4 40//(5*sizeof(uint64_t))
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#define COOP_REG_S5 48//(6*sizeof(uint64_t))
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#define COOP_REG_S6 56//(7*sizeof(uint64_t))
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#define COOP_REG_S7 64//(8*sizeof(uint64_t))
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#define COOP_REG_S8 72//(9*sizeof(uint64_t))
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#define COOP_REG_S9 80//(10*sizeof(uint64_t))
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#define COOP_REG_S10 88//(11*sizeof(uint64_t))
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#define COOP_REG_S11 96//(12*sizeof(uint64_t))
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/** Stack pointer */
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#define COOP_REG_SP 104//(13*sizeof(uint64_t))
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/** Thread pointer */
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#define COOP_REG_TP 112//(14*sizeof(uint64_t))
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/** Return values */
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#define COOP_REG_V0 120//(15*sizeof(uint64_t))
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#define COOP_REG_V1 128//(16*sizeof(uint64_t))
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/** Function Arguments */
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#define COOP_REG_A0 136//(17*sizeof(uint64_t))
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#define COOP_REG_A1 144//(18*sizeof(uint64_t))
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#define COOP_REG_A2 152//(19*sizeof(uint64_t))
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#define COOP_REG_A3 160//(20*sizeof(uint64_t))
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#define COOP_REG_A4 168//(21*sizeof(uint64_t))
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#define COOP_REG_A5 176//(22*sizeof(uint64_t))
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#define COOP_REG_A6 184//(23*sizeof(uint64_t))
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#define COOP_REG_A7 192//(24*sizeof(uint64_t))
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/** Temporary registers */
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#define COOP_REG_T0 200//(25*sizeof(uint64_t))
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#define COOP_REG_T1 208//(26*sizeof(uint64_t))
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#define COOP_REG_T2 216//(27*sizeof(uint64_t))
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#define COOP_REG_T3 224//(28*sizeof(uint64_t))
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#define COOP_REG_T4 232//(29*sizeof(uint64_t))
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/** Global pointer */
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#define COOP_REG_GP 240//(30*sizeof(uint64_t))
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#define _save_context(TO) \
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sd ra, COOP_REG_RA(TO); \
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sd s0, COOP_REG_S0(TO); \
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sd s1, COOP_REG_S1(TO); \
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sd s2, COOP_REG_S2(TO); \
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sd s3, COOP_REG_S3(TO); \
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sd s4, COOP_REG_S4(TO); \
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sd s5, COOP_REG_S5(TO); \
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sd s6, COOP_REG_S6(TO); \
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sd s7, COOP_REG_S7(TO); \
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sd s8, COOP_REG_S8(TO); \
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sd s9, COOP_REG_S9(TO); \
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sd s10, COOP_REG_S10(TO); \
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sd s11, COOP_REG_S11(TO); \
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sd sp, COOP_REG_SP(TO); \
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sd x16, COOP_REG_V0(TO); \
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sd x17, COOP_REG_V1(TO); \
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sd a0, COOP_REG_A0(TO); \
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sd a1, COOP_REG_A1(TO); \
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sd a2, COOP_REG_A2(TO); \
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sd a3, COOP_REG_A3(TO); \
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sd a4, COOP_REG_A4(TO); \
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sd a5, COOP_REG_A5(TO); \
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sd a6, COOP_REG_A6(TO); \
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sd a7, COOP_REG_A7(TO); \
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sd t0, COOP_REG_T0(TO); \
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sd t1, COOP_REG_T1(TO); \
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sd t2, COOP_REG_T2(TO); \
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sd t3, COOP_REG_T3(TO); \
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sd t4, COOP_REG_T4(TO); \
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sd gp, COOP_REG_GP(TO);
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#define _restore_context(FROM) \
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ld ra, COOP_REG_RA(FROM); \
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ld s0, COOP_REG_S0(FROM); \
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ld s1, COOP_REG_S1(FROM); \
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ld s2, COOP_REG_S2(FROM); \
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ld s3, COOP_REG_S3(FROM); \
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ld s4, COOP_REG_S4(FROM); \
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ld s5, COOP_REG_S5(FROM); \
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ld s6, COOP_REG_S6(FROM); \
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ld s7, COOP_REG_S7(FROM); \
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ld s8, COOP_REG_S8(FROM); \
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ld s9, COOP_REG_S9(FROM); \
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ld s10, COOP_REG_S10(FROM); \
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ld s11, COOP_REG_S11(FROM); \
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ld sp, COOP_REG_SP(FROM); \
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ld x16, COOP_REG_V0(FROM); \
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ld x17, COOP_REG_V1(FROM); \
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ld a0, COOP_REG_A0(FROM); \
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ld a1, COOP_REG_A1(FROM); \
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ld a2, COOP_REG_A2(FROM); \
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ld a3, COOP_REG_A3(FROM); \
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ld a4, COOP_REG_A4(FROM); \
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ld a5, COOP_REG_A5(FROM); \
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ld a6, COOP_REG_A6(FROM); \
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ld a7, COOP_REG_A7(FROM); \
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ld t0, COOP_REG_T0(FROM); \
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ld t1, COOP_REG_T1(FROM); \
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ld t2, COOP_REG_T2(FROM); \
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ld t3, COOP_REG_T3(FROM); \
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ld t4, COOP_REG_T4(FROM); \
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ld gp, COOP_REG_GP(FROM);
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#define MSTATUS_IE 0x00000001
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#define MSTATUS_PRV 0x00000006
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#define MSTATUS_IE1 0x00000008
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#define MSTATUS_PRV1 0x00000030
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#define MSTATUS_IE2 0x00000040
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#define MSTATUS_PRV2 0x00000180
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#define MSTATUS_IE3 0x00000200
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#define MSTATUS_PRV3 0x00000C00
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#define MSTATUS_FS 0x00003000
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#define MSTATUS_XS 0x0000C000
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#define MSTATUS_MPRV 0x00010000
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#define MSTATUS_VM 0x003E0000
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#define MSTATUS32_SD 0x80000000
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#define MSTATUS64_SD 0x8000000000000000
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#define SSTATUS_IE 0x00000001
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#define SSTATUS_PIE 0x00000008
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#define SSTATUS_PS 0x00000010
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#define SSTATUS_FS 0x00003000
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#define SSTATUS_XS 0x0000C000
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#define SSTATUS_MPRV 0x00010000
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#define SSTATUS_TIE 0x01000000
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#define SSTATUS32_SD 0x80000000
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#define SSTATUS64_SD 0x8000000000000000
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#define MIP_SSIP 0x00000002
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#define MIP_HSIP 0x00000004
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#define MIP_MSIP 0x00000008
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#define MIP_STIP 0x00000020
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#define MIP_HTIP 0x00000040
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#define MIP_MTIP 0x00000080
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#define SIP_SSIP MIP_SSIP
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#define SIP_STIP MIP_STIP
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#define PRV_U 0
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#define PRV_S 1
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#define PRV_H 2
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#define PRV_M 3
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#define VM_MBARE 0
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#define VM_MBB 1
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#define VM_MBBID 2
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#define VM_SV32 8
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#define VM_SV39 9
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#define VM_SV48 10
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#define UA_RV32 0
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#define UA_RV64 4
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#define UA_RV128 8
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#define IRQ_SOFT 0
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#define IRQ_TIMER 1
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#define IRQ_HOST 2
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#define IRQ_COP 3
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#define IMPL_ROCKET 1
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#define DEFAULT_MTVEC 0x100
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// page table entry (PTE) fields
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#define PTE_V 0x001 // Valid
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#define PTE_TYPE 0x01E // Type
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#define PTE_R 0x020 // Referenced
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#define PTE_D 0x040 // Dirty
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#define PTE_SOFT 0x380 // Reserved for Software
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#define PTE_TYPE_TABLE 0x00
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#define PTE_TYPE_TABLE_GLOBAL 0x02
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#define PTE_TYPE_URX_SR 0x04
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#define PTE_TYPE_URWX_SRW 0x06
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#define PTE_TYPE_UR_SR 0x08
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#define PTE_TYPE_URW_SRW 0x0A
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#define PTE_TYPE_URX_SRX 0x0C
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#define PTE_TYPE_URWX_SRWX 0x0E
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#define PTE_TYPE_SR 0x10
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#define PTE_TYPE_SRW 0x12
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#define PTE_TYPE_SRX 0x14
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#define PTE_TYPE_SRWX 0x16
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#define PTE_TYPE_SR_GLOBAL 0x18
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#define PTE_TYPE_SRW_GLOBAL 0x1A
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#define PTE_TYPE_SRX_GLOBAL 0x1C
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#define PTE_TYPE_SRWX_GLOBAL 0x1E
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#define PTE_PPN_SHIFT 10
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#define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1)
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#define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
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#define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1)
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#define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
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#define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
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#define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1)
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#define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
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#define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \
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((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
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(FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
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((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
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#ifdef __riscv
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#ifdef __riscv64
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# define MSTATUS_SD MSTATUS64_SD
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# define SSTATUS_SD SSTATUS64_SD
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# define RISCV_PGLEVEL_BITS 9
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#else
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# define MSTATUS_SD MSTATUS32_SD
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# define SSTATUS_SD SSTATUS32_SD
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# define RISCV_PGLEVEL_BITS 10
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#endif
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#define RISCV_PGSHIFT 12
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#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
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#ifndef __ASSEMBLER__
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#ifdef __GNUC__
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#define read_csr(reg) ({ unsigned long __tmp; \
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asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
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__tmp; })
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#define write_csr(reg, val) \
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asm volatile ("csrw " #reg ", %0" :: "r"(val))
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#define swap_csr(reg, val) ({ long __tmp; \
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asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
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__tmp; })
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#define set_csr(reg, bit) ({ unsigned long __tmp; \
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if (__builtin_constant_p(bit) && (bit) < 32) \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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__tmp; })
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#define clear_csr(reg, bit) ({ unsigned long __tmp; \
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if (__builtin_constant_p(bit) && (bit) < 32) \
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asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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__tmp; })
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#define rdtime() read_csr(time)
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#define rdcycle() read_csr(cycle)
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#define rdinstret() read_csr(instret)
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#endif
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#endif
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#endif
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#endif
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/* Automatically generated by parse-opcodes */
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#ifndef RISCV_ENCODING_H
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#define RISCV_ENCODING_H
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#define MATCH_ADD 0x33
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#define MASK_ADD 0xfe00707f
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#define MATCH_ADDI 0x13
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#define MASK_ADDI 0x707f
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#define MATCH_ADDIW 0x1b
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#define MASK_ADDIW 0x707f
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#define MATCH_ADDW 0x3b
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#define MASK_ADDW 0xfe00707f
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#define MATCH_AMOADD_D 0x302f
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#define MASK_AMOADD_D 0xf800707f
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#define MATCH_AMOADD_W 0x202f
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#define MASK_AMOADD_W 0xf800707f
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#define MATCH_AMOAND_D 0x6000302f
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#define MASK_AMOAND_D 0xf800707f
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#define MATCH_AMOAND_W 0x6000202f
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#define MASK_AMOAND_W 0xf800707f
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#define MATCH_AMOMAX_D 0xa000302f
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#define MASK_AMOMAX_D 0xf800707f
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#define MATCH_AMOMAX_W 0xa000202f
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#define MASK_AMOMAX_W 0xf800707f
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#define MATCH_AMOMAXU_D 0xe000302f
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#define MASK_AMOMAXU_D 0xf800707f
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#define MATCH_AMOMAXU_W 0xe000202f
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|
|
#define MASK_AMOMAXU_W 0xf800707f
|
| 292 |
|
|
#define MATCH_AMOMIN_D 0x8000302f
|
| 293 |
|
|
#define MASK_AMOMIN_D 0xf800707f
|
| 294 |
|
|
#define MATCH_AMOMIN_W 0x8000202f
|
| 295 |
|
|
#define MASK_AMOMIN_W 0xf800707f
|
| 296 |
|
|
#define MATCH_AMOMINU_D 0xc000302f
|
| 297 |
|
|
#define MASK_AMOMINU_D 0xf800707f
|
| 298 |
|
|
#define MATCH_AMOMINU_W 0xc000202f
|
| 299 |
|
|
#define MASK_AMOMINU_W 0xf800707f
|
| 300 |
|
|
#define MATCH_AMOOR_D 0x4000302f
|
| 301 |
|
|
#define MASK_AMOOR_D 0xf800707f
|
| 302 |
|
|
#define MATCH_AMOOR_W 0x4000202f
|
| 303 |
|
|
#define MASK_AMOOR_W 0xf800707f
|
| 304 |
|
|
#define MATCH_AMOSWAP_D 0x800302f
|
| 305 |
|
|
#define MASK_AMOSWAP_D 0xf800707f
|
| 306 |
|
|
#define MATCH_AMOSWAP_W 0x800202f
|
| 307 |
|
|
#define MASK_AMOSWAP_W 0xf800707f
|
| 308 |
|
|
#define MATCH_AMOXOR_D 0x2000302f
|
| 309 |
|
|
#define MASK_AMOXOR_D 0xf800707f
|
| 310 |
|
|
#define MATCH_AMOXOR_W 0x2000202f
|
| 311 |
|
|
#define MASK_AMOXOR_W 0xf800707f
|
| 312 |
|
|
#define MATCH_AND 0x7033
|
| 313 |
|
|
#define MASK_AND 0xfe00707f
|
| 314 |
|
|
#define MATCH_ANDI 0x7013
|
| 315 |
|
|
#define MASK_ANDI 0x707f
|
| 316 |
|
|
#define MATCH_AUIPC 0x17
|
| 317 |
|
|
#define MASK_AUIPC 0x7f
|
| 318 |
|
|
#define MATCH_BEQ 0x63
|
| 319 |
|
|
#define MASK_BEQ 0x707f
|
| 320 |
|
|
#define MATCH_BGE 0x5063
|
| 321 |
|
|
#define MASK_BGE 0x707f
|
| 322 |
|
|
#define MATCH_BGEU 0x7063
|
| 323 |
|
|
#define MASK_BGEU 0x707f
|
| 324 |
|
|
#define MATCH_BLT 0x4063
|
| 325 |
|
|
#define MASK_BLT 0x707f
|
| 326 |
|
|
#define MATCH_BLTU 0x6063
|
| 327 |
|
|
#define MASK_BLTU 0x707f
|
| 328 |
|
|
#define MATCH_BNE 0x1063
|
| 329 |
|
|
#define MASK_BNE 0x707f
|
| 330 |
|
|
#define MATCH_C_ADD 0x1000
|
| 331 |
|
|
#define MASK_C_ADD 0xf003
|
| 332 |
|
|
#define MATCH_C_ADD3 0xa000
|
| 333 |
|
|
#define MASK_C_ADD3 0xe063
|
| 334 |
|
|
#define MATCH_C_ADDI 0xc002
|
| 335 |
|
|
#define MASK_C_ADDI 0xe003
|
| 336 |
|
|
#define MATCH_C_ADDI4SPN 0xa001
|
| 337 |
|
|
#define MASK_C_ADDI4SPN 0xe003
|
| 338 |
|
|
#define MATCH_C_ADDIW 0xe002
|
| 339 |
|
|
#define MASK_C_ADDIW 0xe003
|
| 340 |
|
|
#define MATCH_C_ADDW 0x9000
|
| 341 |
|
|
#define MASK_C_ADDW 0xf003
|
| 342 |
|
|
#define MATCH_C_AND3 0xa060
|
| 343 |
|
|
#define MASK_C_AND3 0xe063
|
| 344 |
|
|
#define MATCH_C_BEQZ 0x4002
|
| 345 |
|
|
#define MASK_C_BEQZ 0xe003
|
| 346 |
|
|
#define MATCH_C_BNEZ 0x6002
|
| 347 |
|
|
#define MASK_C_BNEZ 0xe003
|
| 348 |
|
|
#define MATCH_C_J 0x2
|
| 349 |
|
|
#define MASK_C_J 0xe003
|
| 350 |
|
|
#define MATCH_C_JAL 0x2002
|
| 351 |
|
|
#define MASK_C_JAL 0xe003
|
| 352 |
|
|
#define MATCH_C_LD 0xe000
|
| 353 |
|
|
#define MASK_C_LD 0xe003
|
| 354 |
|
|
#define MATCH_C_LDSP 0xe001
|
| 355 |
|
|
#define MASK_C_LDSP 0xe003
|
| 356 |
|
|
#define MATCH_C_LI 0x8002
|
| 357 |
|
|
#define MASK_C_LI 0xe003
|
| 358 |
|
|
#define MATCH_C_LUI 0xa002
|
| 359 |
|
|
#define MASK_C_LUI 0xe003
|
| 360 |
|
|
#define MATCH_C_LW 0xc000
|
| 361 |
|
|
#define MASK_C_LW 0xe003
|
| 362 |
|
|
#define MATCH_C_LWSP 0xc001
|
| 363 |
|
|
#define MASK_C_LWSP 0xe003
|
| 364 |
|
|
#define MATCH_C_MV 0x0
|
| 365 |
|
|
#define MASK_C_MV 0xf003
|
| 366 |
|
|
#define MATCH_C_OR3 0xa040
|
| 367 |
|
|
#define MASK_C_OR3 0xe063
|
| 368 |
|
|
#define MATCH_C_SD 0x6000
|
| 369 |
|
|
#define MASK_C_SD 0xe003
|
| 370 |
|
|
#define MATCH_C_SDSP 0x6001
|
| 371 |
|
|
#define MASK_C_SDSP 0xe003
|
| 372 |
|
|
#define MATCH_C_SLLI 0x1
|
| 373 |
|
|
#define MASK_C_SLLI 0xe003
|
| 374 |
|
|
#define MATCH_C_SLLIW 0x8001
|
| 375 |
|
|
#define MASK_C_SLLIW 0xe003
|
| 376 |
|
|
#define MATCH_C_SRAI 0x2000
|
| 377 |
|
|
#define MASK_C_SRAI 0xe003
|
| 378 |
|
|
#define MATCH_C_SRLI 0x2001
|
| 379 |
|
|
#define MASK_C_SRLI 0xe003
|
| 380 |
|
|
#define MATCH_C_SUB 0x8000
|
| 381 |
|
|
#define MASK_C_SUB 0xf003
|
| 382 |
|
|
#define MATCH_C_SUB3 0xa020
|
| 383 |
|
|
#define MASK_C_SUB3 0xe063
|
| 384 |
|
|
#define MATCH_C_SW 0x4000
|
| 385 |
|
|
#define MASK_C_SW 0xe003
|
| 386 |
|
|
#define MATCH_C_SWSP 0x4001
|
| 387 |
|
|
#define MASK_C_SWSP 0xe003
|
| 388 |
|
|
#define MATCH_CSRRC 0x3073
|
| 389 |
|
|
#define MASK_CSRRC 0x707f
|
| 390 |
|
|
#define MATCH_CSRRCI 0x7073
|
| 391 |
|
|
#define MASK_CSRRCI 0x707f
|
| 392 |
|
|
#define MATCH_CSRRS 0x2073
|
| 393 |
|
|
#define MASK_CSRRS 0x707f
|
| 394 |
|
|
#define MATCH_CSRRSI 0x6073
|
| 395 |
|
|
#define MASK_CSRRSI 0x707f
|
| 396 |
|
|
#define MATCH_CSRRW 0x1073
|
| 397 |
|
|
#define MASK_CSRRW 0x707f
|
| 398 |
|
|
#define MATCH_CSRRWI 0x5073
|
| 399 |
|
|
#define MASK_CSRRWI 0x707f
|
| 400 |
|
|
#define MATCH_DIV 0x2004033
|
| 401 |
|
|
#define MASK_DIV 0xfe00707f
|
| 402 |
|
|
#define MATCH_DIVU 0x2005033
|
| 403 |
|
|
#define MASK_DIVU 0xfe00707f
|
| 404 |
|
|
#define MATCH_DIVUW 0x200503b
|
| 405 |
|
|
#define MASK_DIVUW 0xfe00707f
|
| 406 |
|
|
#define MATCH_DIVW 0x200403b
|
| 407 |
|
|
#define MASK_DIVW 0xfe00707f
|
| 408 |
|
|
#define MATCH_FADD_D 0x2000053
|
| 409 |
|
|
#define MASK_FADD_D 0xfe00007f
|
| 410 |
|
|
#define MATCH_FADD_S 0x53
|
| 411 |
|
|
#define MASK_FADD_S 0xfe00007f
|
| 412 |
|
|
#define MATCH_FCLASS_D 0xe2001053
|
| 413 |
|
|
#define MASK_FCLASS_D 0xfff0707f
|
| 414 |
|
|
#define MATCH_FCLASS_S 0xe0001053
|
| 415 |
|
|
#define MASK_FCLASS_S 0xfff0707f
|
| 416 |
|
|
#define MATCH_FCVT_D_L 0xd2200053
|
| 417 |
|
|
#define MASK_FCVT_D_L 0xfff0007f
|
| 418 |
|
|
#define MATCH_FCVT_D_LU 0xd2300053
|
| 419 |
|
|
#define MASK_FCVT_D_LU 0xfff0007f
|
| 420 |
|
|
#define MATCH_FCVT_D_S 0x42000053
|
| 421 |
|
|
#define MASK_FCVT_D_S 0xfff0007f
|
| 422 |
|
|
#define MATCH_FCVT_D_W 0xd2000053
|
| 423 |
|
|
#define MASK_FCVT_D_W 0xfff0007f
|
| 424 |
|
|
#define MATCH_FCVT_D_WU 0xd2100053
|
| 425 |
|
|
#define MASK_FCVT_D_WU 0xfff0007f
|
| 426 |
|
|
#define MATCH_FCVT_L_D 0xc2200053
|
| 427 |
|
|
#define MASK_FCVT_L_D 0xfff0007f
|
| 428 |
|
|
#define MATCH_FCVT_L_S 0xc0200053
|
| 429 |
|
|
#define MASK_FCVT_L_S 0xfff0007f
|
| 430 |
|
|
#define MATCH_FCVT_LU_D 0xc2300053
|
| 431 |
|
|
#define MASK_FCVT_LU_D 0xfff0007f
|
| 432 |
|
|
#define MATCH_FCVT_LU_S 0xc0300053
|
| 433 |
|
|
#define MASK_FCVT_LU_S 0xfff0007f
|
| 434 |
|
|
#define MATCH_FCVT_S_D 0x40100053
|
| 435 |
|
|
#define MASK_FCVT_S_D 0xfff0007f
|
| 436 |
|
|
#define MATCH_FCVT_S_L 0xd0200053
|
| 437 |
|
|
#define MASK_FCVT_S_L 0xfff0007f
|
| 438 |
|
|
#define MATCH_FCVT_S_LU 0xd0300053
|
| 439 |
|
|
#define MASK_FCVT_S_LU 0xfff0007f
|
| 440 |
|
|
#define MATCH_FCVT_S_W 0xd0000053
|
| 441 |
|
|
#define MASK_FCVT_S_W 0xfff0007f
|
| 442 |
|
|
#define MATCH_FCVT_S_WU 0xd0100053
|
| 443 |
|
|
#define MASK_FCVT_S_WU 0xfff0007f
|
| 444 |
|
|
#define MATCH_FCVT_W_D 0xc2000053
|
| 445 |
|
|
#define MASK_FCVT_W_D 0xfff0007f
|
| 446 |
|
|
#define MATCH_FCVT_W_S 0xc0000053
|
| 447 |
|
|
#define MASK_FCVT_W_S 0xfff0007f
|
| 448 |
|
|
#define MATCH_FCVT_WU_D 0xc2100053
|
| 449 |
|
|
#define MASK_FCVT_WU_D 0xfff0007f
|
| 450 |
|
|
#define MATCH_FCVT_WU_S 0xc0100053
|
| 451 |
|
|
#define MASK_FCVT_WU_S 0xfff0007f
|
| 452 |
|
|
#define MATCH_FDIV_D 0x1a000053
|
| 453 |
|
|
#define MASK_FDIV_D 0xfe00007f
|
| 454 |
|
|
#define MATCH_FDIV_S 0x18000053
|
| 455 |
|
|
#define MASK_FDIV_S 0xfe00007f
|
| 456 |
|
|
#define MATCH_FENCE 0xf
|
| 457 |
|
|
#define MASK_FENCE 0x707f
|
| 458 |
|
|
#define MATCH_FENCE_I 0x100f
|
| 459 |
|
|
#define MASK_FENCE_I 0x707f
|
| 460 |
|
|
#define MATCH_FEQ_D 0xa2002053
|
| 461 |
|
|
#define MASK_FEQ_D 0xfe00707f
|
| 462 |
|
|
#define MATCH_FEQ_S 0xa0002053
|
| 463 |
|
|
#define MASK_FEQ_S 0xfe00707f
|
| 464 |
|
|
#define MATCH_FLD 0x3007
|
| 465 |
|
|
#define MASK_FLD 0x707f
|
| 466 |
|
|
#define MATCH_FLE_D 0xa2000053
|
| 467 |
|
|
#define MASK_FLE_D 0xfe00707f
|
| 468 |
|
|
#define MATCH_FLE_S 0xa0000053
|
| 469 |
|
|
#define MASK_FLE_S 0xfe00707f
|
| 470 |
|
|
#define MATCH_FLT_D 0xa2001053
|
| 471 |
|
|
#define MASK_FLT_D 0xfe00707f
|
| 472 |
|
|
#define MATCH_FLT_S 0xa0001053
|
| 473 |
|
|
#define MASK_FLT_S 0xfe00707f
|
| 474 |
|
|
#define MATCH_FLW 0x2007
|
| 475 |
|
|
#define MASK_FLW 0x707f
|
| 476 |
|
|
#define MATCH_FMADD_D 0x2000043
|
| 477 |
|
|
#define MASK_FMADD_D 0x600007f
|
| 478 |
|
|
#define MATCH_FMADD_S 0x43
|
| 479 |
|
|
#define MASK_FMADD_S 0x600007f
|
| 480 |
|
|
#define MATCH_FMAX_D 0x2a001053
|
| 481 |
|
|
#define MASK_FMAX_D 0xfe00707f
|
| 482 |
|
|
#define MATCH_FMAX_S 0x28001053
|
| 483 |
|
|
#define MASK_FMAX_S 0xfe00707f
|
| 484 |
|
|
#define MATCH_FMIN_D 0x2a000053
|
| 485 |
|
|
#define MASK_FMIN_D 0xfe00707f
|
| 486 |
|
|
#define MATCH_FMIN_S 0x28000053
|
| 487 |
|
|
#define MASK_FMIN_S 0xfe00707f
|
| 488 |
|
|
#define MATCH_FMSUB_D 0x2000047
|
| 489 |
|
|
#define MASK_FMSUB_D 0x600007f
|
| 490 |
|
|
#define MATCH_FMSUB_S 0x47
|
| 491 |
|
|
#define MASK_FMSUB_S 0x600007f
|
| 492 |
|
|
#define MATCH_FMUL_D 0x12000053
|
| 493 |
|
|
#define MASK_FMUL_D 0xfe00007f
|
| 494 |
|
|
#define MATCH_FMUL_S 0x10000053
|
| 495 |
|
|
#define MASK_FMUL_S 0xfe00007f
|
| 496 |
|
|
#define MATCH_FMV_D_X 0xf2000053
|
| 497 |
|
|
#define MASK_FMV_D_X 0xfff0707f
|
| 498 |
|
|
#define MATCH_FMV_S_X 0xf0000053
|
| 499 |
|
|
#define MASK_FMV_S_X 0xfff0707f
|
| 500 |
|
|
#define MATCH_FMV_X_D 0xe2000053
|
| 501 |
|
|
#define MASK_FMV_X_D 0xfff0707f
|
| 502 |
|
|
#define MATCH_FMV_X_S 0xe0000053
|
| 503 |
|
|
#define MASK_FMV_X_S 0xfff0707f
|
| 504 |
|
|
#define MATCH_FNMADD_D 0x200004f
|
| 505 |
|
|
#define MASK_FNMADD_D 0x600007f
|
| 506 |
|
|
#define MATCH_FNMADD_S 0x4f
|
| 507 |
|
|
#define MASK_FNMADD_S 0x600007f
|
| 508 |
|
|
#define MATCH_FNMSUB_D 0x200004b
|
| 509 |
|
|
#define MASK_FNMSUB_D 0x600007f
|
| 510 |
|
|
#define MATCH_FNMSUB_S 0x4b
|
| 511 |
|
|
#define MASK_FNMSUB_S 0x600007f
|
| 512 |
|
|
#define MATCH_FSD 0x3027
|
| 513 |
|
|
#define MASK_FSD 0x707f
|
| 514 |
|
|
#define MATCH_FSGNJ_D 0x22000053
|
| 515 |
|
|
#define MASK_FSGNJ_D 0xfe00707f
|
| 516 |
|
|
#define MATCH_FSGNJ_S 0x20000053
|
| 517 |
|
|
#define MASK_FSGNJ_S 0xfe00707f
|
| 518 |
|
|
#define MATCH_FSGNJN_D 0x22001053
|
| 519 |
|
|
#define MASK_FSGNJN_D 0xfe00707f
|
| 520 |
|
|
#define MATCH_FSGNJN_S 0x20001053
|
| 521 |
|
|
#define MASK_FSGNJN_S 0xfe00707f
|
| 522 |
|
|
#define MATCH_FSGNJX_D 0x22002053
|
| 523 |
|
|
#define MASK_FSGNJX_D 0xfe00707f
|
| 524 |
|
|
#define MATCH_FSGNJX_S 0x20002053
|
| 525 |
|
|
#define MASK_FSGNJX_S 0xfe00707f
|
| 526 |
|
|
#define MATCH_FSQRT_D 0x5a000053
|
| 527 |
|
|
#define MASK_FSQRT_D 0xfff0007f
|
| 528 |
|
|
#define MATCH_FSQRT_S 0x58000053
|
| 529 |
|
|
#define MASK_FSQRT_S 0xfff0007f
|
| 530 |
|
|
#define MATCH_FSUB_D 0xa000053
|
| 531 |
|
|
#define MASK_FSUB_D 0xfe00007f
|
| 532 |
|
|
#define MATCH_FSUB_S 0x8000053
|
| 533 |
|
|
#define MASK_FSUB_S 0xfe00007f
|
| 534 |
|
|
#define MATCH_FSW 0x2027
|
| 535 |
|
|
#define MASK_FSW 0x707f
|
| 536 |
|
|
#define MATCH_HRTS 0x20500073
|
| 537 |
|
|
#define MASK_HRTS 0xffffffff
|
| 538 |
|
|
#define MATCH_JAL 0x6f
|
| 539 |
|
|
#define MASK_JAL 0x7f
|
| 540 |
|
|
#define MATCH_JALR 0x67
|
| 541 |
|
|
#define MASK_JALR 0x707f
|
| 542 |
|
|
#define MATCH_LB 0x3
|
| 543 |
|
|
#define MASK_LB 0x707f
|
| 544 |
|
|
#define MATCH_LBU 0x4003
|
| 545 |
|
|
#define MASK_LBU 0x707f
|
| 546 |
|
|
#define MATCH_LD 0x3003
|
| 547 |
|
|
#define MASK_LD 0x707f
|
| 548 |
|
|
#define MATCH_LH 0x1003
|
| 549 |
|
|
#define MASK_LH 0x707f
|
| 550 |
|
|
#define MATCH_LHU 0x5003
|
| 551 |
|
|
#define MASK_LHU 0x707f
|
| 552 |
|
|
#define MATCH_LR_D 0x1000302f
|
| 553 |
|
|
#define MASK_LR_D 0xf9f0707f
|
| 554 |
|
|
#define MATCH_LR_W 0x1000202f
|
| 555 |
|
|
#define MASK_LR_W 0xf9f0707f
|
| 556 |
|
|
#define MATCH_LUI 0x37
|
| 557 |
|
|
#define MASK_LUI 0x7f
|
| 558 |
|
|
#define MATCH_LW 0x2003
|
| 559 |
|
|
#define MASK_LW 0x707f
|
| 560 |
|
|
#define MATCH_LWU 0x6003
|
| 561 |
|
|
#define MASK_LWU 0x707f
|
| 562 |
|
|
#define MATCH_MRTH 0x30600073
|
| 563 |
|
|
#define MASK_MRTH 0xffffffff
|
| 564 |
|
|
#define MATCH_MRTS 0x30500073
|
| 565 |
|
|
#define MASK_MRTS 0xffffffff
|
| 566 |
|
|
#define MATCH_MUL 0x2000033
|
| 567 |
|
|
#define MASK_MUL 0xfe00707f
|
| 568 |
|
|
#define MATCH_MULH 0x2001033
|
| 569 |
|
|
#define MASK_MULH 0xfe00707f
|
| 570 |
|
|
#define MATCH_MULHSU 0x2002033
|
| 571 |
|
|
#define MASK_MULHSU 0xfe00707f
|
| 572 |
|
|
#define MATCH_MULHU 0x2003033
|
| 573 |
|
|
#define MASK_MULHU 0xfe00707f
|
| 574 |
|
|
#define MATCH_MULW 0x200003b
|
| 575 |
|
|
#define MASK_MULW 0xfe00707f
|
| 576 |
|
|
#define MATCH_OR 0x6033
|
| 577 |
|
|
#define MASK_OR 0xfe00707f
|
| 578 |
|
|
#define MATCH_ORI 0x6013
|
| 579 |
|
|
#define MASK_ORI 0x707f
|
| 580 |
|
|
#define MATCH_REM 0x2006033
|
| 581 |
|
|
#define MASK_REM 0xfe00707f
|
| 582 |
|
|
#define MATCH_REMU 0x2007033
|
| 583 |
|
|
#define MASK_REMU 0xfe00707f
|
| 584 |
|
|
#define MATCH_REMUW 0x200703b
|
| 585 |
|
|
#define MASK_REMUW 0xfe00707f
|
| 586 |
|
|
#define MATCH_REMW 0x200603b
|
| 587 |
|
|
#define MASK_REMW 0xfe00707f
|
| 588 |
|
|
#define MATCH_SB 0x23
|
| 589 |
|
|
#define MASK_SB 0x707f
|
| 590 |
|
|
#define MATCH_SBREAK 0x100073
|
| 591 |
|
|
#define MASK_SBREAK 0xffffffff
|
| 592 |
|
|
#define MATCH_SC_D 0x1800302f
|
| 593 |
|
|
#define MASK_SC_D 0xf800707f
|
| 594 |
|
|
#define MATCH_SC_W 0x1800202f
|
| 595 |
|
|
#define MASK_SC_W 0xf800707f
|
| 596 |
|
|
#define MATCH_SCALL 0x73
|
| 597 |
|
|
#define MASK_SCALL 0xffffffff
|
| 598 |
|
|
#define MATCH_SD 0x3023
|
| 599 |
|
|
#define MASK_SD 0x707f
|
| 600 |
|
|
#define MATCH_SFENCE_VM 0x10100073
|
| 601 |
|
|
#define MASK_SFENCE_VM 0xfff07fff
|
| 602 |
|
|
#define MATCH_SH 0x1023
|
| 603 |
|
|
#define MASK_SH 0x707f
|
| 604 |
|
|
#define MATCH_SLL 0x1033
|
| 605 |
|
|
#define MASK_SLL 0xfe00707f
|
| 606 |
|
|
#define MATCH_SLLI 0x1013
|
| 607 |
|
|
#define MASK_SLLI 0xfc00707f
|
| 608 |
|
|
#define MATCH_SLLIW 0x101b
|
| 609 |
|
|
#define MASK_SLLIW 0xfe00707f
|
| 610 |
|
|
#define MATCH_SLLW 0x103b
|
| 611 |
|
|
#define MASK_SLLW 0xfe00707f
|
| 612 |
|
|
#define MATCH_SLT 0x2033
|
| 613 |
|
|
#define MASK_SLT 0xfe00707f
|
| 614 |
|
|
#define MATCH_SLTI 0x2013
|
| 615 |
|
|
#define MASK_SLTI 0x707f
|
| 616 |
|
|
#define MATCH_SLTIU 0x3013
|
| 617 |
|
|
#define MASK_SLTIU 0x707f
|
| 618 |
|
|
#define MATCH_SLTU 0x3033
|
| 619 |
|
|
#define MASK_SLTU 0xfe00707f
|
| 620 |
|
|
#define MATCH_SRA 0x40005033
|
| 621 |
|
|
#define MASK_SRA 0xfe00707f
|
| 622 |
|
|
#define MATCH_SRAI 0x40005013
|
| 623 |
|
|
#define MASK_SRAI 0xfc00707f
|
| 624 |
|
|
#define MATCH_SRAIW 0x4000501b
|
| 625 |
|
|
#define MASK_SRAIW 0xfe00707f
|
| 626 |
|
|
#define MATCH_SRAW 0x4000503b
|
| 627 |
|
|
#define MASK_SRAW 0xfe00707f
|
| 628 |
|
|
#define MATCH_SRET 0x10000073
|
| 629 |
|
|
#define MASK_SRET 0xffffffff
|
| 630 |
|
|
#define MATCH_SRL 0x5033
|
| 631 |
|
|
#define MASK_SRL 0xfe00707f
|
| 632 |
|
|
#define MATCH_SRLI 0x5013
|
| 633 |
|
|
#define MASK_SRLI 0xfc00707f
|
| 634 |
|
|
#define MATCH_SRLIW 0x501b
|
| 635 |
|
|
#define MASK_SRLIW 0xfe00707f
|
| 636 |
|
|
#define MATCH_SRLW 0x503b
|
| 637 |
|
|
#define MASK_SRLW 0xfe00707f
|
| 638 |
|
|
#define MATCH_SUB 0x40000033
|
| 639 |
|
|
#define MASK_SUB 0xfe00707f
|
| 640 |
|
|
#define MATCH_SUBW 0x4000003b
|
| 641 |
|
|
#define MASK_SUBW 0xfe00707f
|
| 642 |
|
|
#define MATCH_SW 0x2023
|
| 643 |
|
|
#define MASK_SW 0x707f
|
| 644 |
|
|
#define MATCH_WFI 0x10200073
|
| 645 |
|
|
#define MASK_WFI 0xffffffff
|
| 646 |
|
|
#define MATCH_XOR 0x4033
|
| 647 |
|
|
#define MASK_XOR 0xfe00707f
|
| 648 |
|
|
#define MATCH_XORI 0x4013
|
| 649 |
|
|
#define MASK_XORI 0x707f
|
| 650 |
|
|
#define CSR_FFLAGS 0x1
|
| 651 |
|
|
#define CSR_FRM 0x2
|
| 652 |
|
|
#define CSR_FCSR 0x3
|
| 653 |
|
|
#define CSR_CYCLE 0xc00
|
| 654 |
|
|
#define CSR_TIME 0xc01
|
| 655 |
|
|
#define CSR_INSTRET 0xc02
|
| 656 |
|
|
#define CSR_STATS 0xc0
|
| 657 |
|
|
#define CSR_UARCH0 0xcc0
|
| 658 |
|
|
#define CSR_UARCH1 0xcc1
|
| 659 |
|
|
#define CSR_UARCH2 0xcc2
|
| 660 |
|
|
#define CSR_UARCH3 0xcc3
|
| 661 |
|
|
#define CSR_UARCH4 0xcc4
|
| 662 |
|
|
#define CSR_UARCH5 0xcc5
|
| 663 |
|
|
#define CSR_UARCH6 0xcc6
|
| 664 |
|
|
#define CSR_UARCH7 0xcc7
|
| 665 |
|
|
#define CSR_UARCH8 0xcc8
|
| 666 |
|
|
#define CSR_UARCH9 0xcc9
|
| 667 |
|
|
#define CSR_UARCH10 0xcca
|
| 668 |
|
|
#define CSR_UARCH11 0xccb
|
| 669 |
|
|
#define CSR_UARCH12 0xccc
|
| 670 |
|
|
#define CSR_UARCH13 0xccd
|
| 671 |
|
|
#define CSR_UARCH14 0xcce
|
| 672 |
|
|
#define CSR_UARCH15 0xccf
|
| 673 |
|
|
#define CSR_SSTATUS 0x100
|
| 674 |
|
|
#define CSR_STVEC 0x101
|
| 675 |
|
|
#define CSR_SIE 0x104
|
| 676 |
|
|
#define CSR_SSCRATCH 0x140
|
| 677 |
|
|
#define CSR_SEPC 0x141
|
| 678 |
|
|
#define CSR_SIP 0x144
|
| 679 |
|
|
#define CSR_SPTBR 0x180
|
| 680 |
|
|
#define CSR_SASID 0x181
|
| 681 |
|
|
#define CSR_CYCLEW 0x900
|
| 682 |
|
|
#define CSR_TIMEW 0x901
|
| 683 |
|
|
#define CSR_INSTRETW 0x902
|
| 684 |
|
|
#define CSR_STIME 0xd01
|
| 685 |
|
|
#define CSR_SCAUSE 0xd42
|
| 686 |
|
|
#define CSR_SBADADDR 0xd43
|
| 687 |
|
|
#define CSR_STIMEW 0xa01
|
| 688 |
|
|
#define CSR_MSTATUS 0x300
|
| 689 |
|
|
#define CSR_MTVEC 0x301
|
| 690 |
|
|
#define CSR_MTDELEG 0x302
|
| 691 |
|
|
#define CSR_MIE 0x304
|
| 692 |
|
|
#define CSR_MTIMECMP 0x321
|
| 693 |
|
|
#define CSR_MSCRATCH 0x340
|
| 694 |
|
|
#define CSR_MEPC 0x341
|
| 695 |
|
|
#define CSR_MCAUSE 0x342
|
| 696 |
|
|
#define CSR_MBADADDR 0x343
|
| 697 |
|
|
#define CSR_MIP 0x344
|
| 698 |
|
|
#define CSR_MTIME 0x701
|
| 699 |
|
|
#define CSR_MCPUID 0xf00
|
| 700 |
|
|
#define CSR_MIMPID 0xf01
|
| 701 |
|
|
#define CSR_MHARTID 0xf10
|
| 702 |
|
|
#define CSR_MTOHOST 0x780
|
| 703 |
|
|
#define CSR_MFROMHOST 0x781
|
| 704 |
|
|
#define CSR_MRESET 0x782
|
| 705 |
|
|
#define CSR_SEND_IPI 0x783
|
| 706 |
|
|
#define CSR_CYCLEH 0xc80
|
| 707 |
|
|
#define CSR_TIMEH 0xc81
|
| 708 |
|
|
#define CSR_INSTRETH 0xc82
|
| 709 |
|
|
#define CSR_CYCLEHW 0x980
|
| 710 |
|
|
#define CSR_TIMEHW 0x981
|
| 711 |
|
|
#define CSR_INSTRETHW 0x982
|
| 712 |
|
|
#define CSR_STIMEH 0xd81
|
| 713 |
|
|
#define CSR_STIMEHW 0xa81
|
| 714 |
|
|
#define CSR_MTIMECMPH 0x361
|
| 715 |
|
|
#define CSR_MTIMEH 0x741
|
| 716 |
|
|
#define CAUSE_MISALIGNED_FETCH 0x0
|
| 717 |
|
|
#define CAUSE_FAULT_FETCH 0x1
|
| 718 |
|
|
#define CAUSE_ILLEGAL_INSTRUCTION 0x2
|
| 719 |
|
|
#define CAUSE_BREAKPOINT 0x3
|
| 720 |
|
|
#define CAUSE_MISALIGNED_LOAD 0x4
|
| 721 |
|
|
#define CAUSE_FAULT_LOAD 0x5
|
| 722 |
|
|
#define CAUSE_MISALIGNED_STORE 0x6
|
| 723 |
|
|
#define CAUSE_FAULT_STORE 0x7
|
| 724 |
|
|
#define CAUSE_USER_ECALL 0x8
|
| 725 |
|
|
#define CAUSE_SUPERVISOR_ECALL 0x9
|
| 726 |
|
|
#define CAUSE_HYPERVISOR_ECALL 0xa
|
| 727 |
|
|
#define CAUSE_MACHINE_ECALL 0xb
|
| 728 |
|
|
#endif
|
| 729 |
|
|
#ifdef DECLARE_INSN
|
| 730 |
|
|
DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
|
| 731 |
|
|
DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
|
| 732 |
|
|
DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
|
| 733 |
|
|
DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
|
| 734 |
|
|
DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
|
| 735 |
|
|
DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
|
| 736 |
|
|
DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
|
| 737 |
|
|
DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
|
| 738 |
|
|
DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
|
| 739 |
|
|
DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
|
| 740 |
|
|
DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
|
| 741 |
|
|
DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
|
| 742 |
|
|
DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
|
| 743 |
|
|
DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
|
| 744 |
|
|
DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
|
| 745 |
|
|
DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
|
| 746 |
|
|
DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
|
| 747 |
|
|
DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
|
| 748 |
|
|
DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
|
| 749 |
|
|
DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
|
| 750 |
|
|
DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
|
| 751 |
|
|
DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
|
| 752 |
|
|
DECLARE_INSN(and, MATCH_AND, MASK_AND)
|
| 753 |
|
|
DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
|
| 754 |
|
|
DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
|
| 755 |
|
|
DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
|
| 756 |
|
|
DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
|
| 757 |
|
|
DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
|
| 758 |
|
|
DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
|
| 759 |
|
|
DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
|
| 760 |
|
|
DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
|
| 761 |
|
|
DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
|
| 762 |
|
|
DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3)
|
| 763 |
|
|
DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
|
| 764 |
|
|
DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
|
| 765 |
|
|
DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
|
| 766 |
|
|
DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
|
| 767 |
|
|
DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3)
|
| 768 |
|
|
DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
|
| 769 |
|
|
DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
|
| 770 |
|
|
DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
|
| 771 |
|
|
DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
|
| 772 |
|
|
DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
|
| 773 |
|
|
DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
|
| 774 |
|
|
DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
|
| 775 |
|
|
DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
|
| 776 |
|
|
DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
|
| 777 |
|
|
DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
|
| 778 |
|
|
DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
|
| 779 |
|
|
DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3)
|
| 780 |
|
|
DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
|
| 781 |
|
|
DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
|
| 782 |
|
|
DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
|
| 783 |
|
|
DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW)
|
| 784 |
|
|
DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
|
| 785 |
|
|
DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
|
| 786 |
|
|
DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
|
| 787 |
|
|
DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3)
|
| 788 |
|
|
DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
|
| 789 |
|
|
DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
|
| 790 |
|
|
DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
|
| 791 |
|
|
DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
|
| 792 |
|
|
DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
|
| 793 |
|
|
DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
|
| 794 |
|
|
DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
|
| 795 |
|
|
DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
|
| 796 |
|
|
DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
|
| 797 |
|
|
DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
|
| 798 |
|
|
DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
|
| 799 |
|
|
DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
|
| 800 |
|
|
DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
|
| 801 |
|
|
DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
|
| 802 |
|
|
DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
|
| 803 |
|
|
DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
|
| 804 |
|
|
DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
|
| 805 |
|
|
DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
|
| 806 |
|
|
DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
|
| 807 |
|
|
DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
|
| 808 |
|
|
DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
|
| 809 |
|
|
DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
|
| 810 |
|
|
DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
|
| 811 |
|
|
DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
|
| 812 |
|
|
DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
|
| 813 |
|
|
DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
|
| 814 |
|
|
DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
|
| 815 |
|
|
DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
|
| 816 |
|
|
DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
|
| 817 |
|
|
DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
|
| 818 |
|
|
DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
|
| 819 |
|
|
DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
|
| 820 |
|
|
DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
|
| 821 |
|
|
DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
|
| 822 |
|
|
DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
|
| 823 |
|
|
DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
|
| 824 |
|
|
DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
|
| 825 |
|
|
DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
|
| 826 |
|
|
DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
|
| 827 |
|
|
DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
|
| 828 |
|
|
DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
|
| 829 |
|
|
DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
|
| 830 |
|
|
DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
|
| 831 |
|
|
DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
|
| 832 |
|
|
DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
|
| 833 |
|
|
DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
|
| 834 |
|
|
DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
|
| 835 |
|
|
DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
|
| 836 |
|
|
DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
|
| 837 |
|
|
DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
|
| 838 |
|
|
DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
|
| 839 |
|
|
DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
|
| 840 |
|
|
DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
|
| 841 |
|
|
DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
|
| 842 |
|
|
DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
|
| 843 |
|
|
DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
|
| 844 |
|
|
DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
|
| 845 |
|
|
DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
|
| 846 |
|
|
DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
|
| 847 |
|
|
DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
|
| 848 |
|
|
DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
|
| 849 |
|
|
DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
|
| 850 |
|
|
DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
|
| 851 |
|
|
DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
|
| 852 |
|
|
DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
|
| 853 |
|
|
DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
|
| 854 |
|
|
DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
|
| 855 |
|
|
DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
|
| 856 |
|
|
DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
|
| 857 |
|
|
DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
|
| 858 |
|
|
DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
|
| 859 |
|
|
DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
|
| 860 |
|
|
DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
|
| 861 |
|
|
DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
|
| 862 |
|
|
DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
|
| 863 |
|
|
DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
|
| 864 |
|
|
DECLARE_INSN(hrts, MATCH_HRTS, MASK_HRTS)
|
| 865 |
|
|
DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
|
| 866 |
|
|
DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
|
| 867 |
|
|
DECLARE_INSN(lb, MATCH_LB, MASK_LB)
|
| 868 |
|
|
DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
|
| 869 |
|
|
DECLARE_INSN(ld, MATCH_LD, MASK_LD)
|
| 870 |
|
|
DECLARE_INSN(lh, MATCH_LH, MASK_LH)
|
| 871 |
|
|
DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
|
| 872 |
|
|
DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
|
| 873 |
|
|
DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
|
| 874 |
|
|
DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
|
| 875 |
|
|
DECLARE_INSN(lw, MATCH_LW, MASK_LW)
|
| 876 |
|
|
DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
|
| 877 |
|
|
DECLARE_INSN(mrth, MATCH_MRTH, MASK_MRTH)
|
| 878 |
|
|
DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS)
|
| 879 |
|
|
DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
|
| 880 |
|
|
DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
|
| 881 |
|
|
DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
|
| 882 |
|
|
DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
|
| 883 |
|
|
DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
|
| 884 |
|
|
DECLARE_INSN(or, MATCH_OR, MASK_OR)
|
| 885 |
|
|
DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
|
| 886 |
|
|
DECLARE_INSN(rem, MATCH_REM, MASK_REM)
|
| 887 |
|
|
DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
|
| 888 |
|
|
DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
|
| 889 |
|
|
DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
|
| 890 |
|
|
DECLARE_INSN(sb, MATCH_SB, MASK_SB)
|
| 891 |
|
|
DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
|
| 892 |
|
|
DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
|
| 893 |
|
|
DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
|
| 894 |
|
|
DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
|
| 895 |
|
|
DECLARE_INSN(sd, MATCH_SD, MASK_SD)
|
| 896 |
|
|
DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
|
| 897 |
|
|
DECLARE_INSN(sh, MATCH_SH, MASK_SH)
|
| 898 |
|
|
DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
|
| 899 |
|
|
DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
|
| 900 |
|
|
DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
|
| 901 |
|
|
DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
|
| 902 |
|
|
DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
|
| 903 |
|
|
DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
|
| 904 |
|
|
DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
|
| 905 |
|
|
DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
|
| 906 |
|
|
DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
|
| 907 |
|
|
DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
|
| 908 |
|
|
DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
|
| 909 |
|
|
DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
|
| 910 |
|
|
DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
|
| 911 |
|
|
DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
|
| 912 |
|
|
DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
|
| 913 |
|
|
DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
|
| 914 |
|
|
DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
|
| 915 |
|
|
DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
|
| 916 |
|
|
DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
|
| 917 |
|
|
DECLARE_INSN(sw, MATCH_SW, MASK_SW)
|
| 918 |
|
|
DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
|
| 919 |
|
|
DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
|
| 920 |
|
|
DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
|
| 921 |
|
|
#endif
|
| 922 |
|
|
#ifdef DECLARE_CSR
|
| 923 |
|
|
DECLARE_CSR(fflags, CSR_FFLAGS)
|
| 924 |
|
|
DECLARE_CSR(frm, CSR_FRM)
|
| 925 |
|
|
DECLARE_CSR(fcsr, CSR_FCSR)
|
| 926 |
|
|
DECLARE_CSR(cycle, CSR_CYCLE)
|
| 927 |
|
|
DECLARE_CSR(time, CSR_TIME)
|
| 928 |
|
|
DECLARE_CSR(instret, CSR_INSTRET)
|
| 929 |
|
|
DECLARE_CSR(stats, CSR_STATS)
|
| 930 |
|
|
DECLARE_CSR(uarch0, CSR_UARCH0)
|
| 931 |
|
|
DECLARE_CSR(uarch1, CSR_UARCH1)
|
| 932 |
|
|
DECLARE_CSR(uarch2, CSR_UARCH2)
|
| 933 |
|
|
DECLARE_CSR(uarch3, CSR_UARCH3)
|
| 934 |
|
|
DECLARE_CSR(uarch4, CSR_UARCH4)
|
| 935 |
|
|
DECLARE_CSR(uarch5, CSR_UARCH5)
|
| 936 |
|
|
DECLARE_CSR(uarch6, CSR_UARCH6)
|
| 937 |
|
|
DECLARE_CSR(uarch7, CSR_UARCH7)
|
| 938 |
|
|
DECLARE_CSR(uarch8, CSR_UARCH8)
|
| 939 |
|
|
DECLARE_CSR(uarch9, CSR_UARCH9)
|
| 940 |
|
|
DECLARE_CSR(uarch10, CSR_UARCH10)
|
| 941 |
|
|
DECLARE_CSR(uarch11, CSR_UARCH11)
|
| 942 |
|
|
DECLARE_CSR(uarch12, CSR_UARCH12)
|
| 943 |
|
|
DECLARE_CSR(uarch13, CSR_UARCH13)
|
| 944 |
|
|
DECLARE_CSR(uarch14, CSR_UARCH14)
|
| 945 |
|
|
DECLARE_CSR(uarch15, CSR_UARCH15)
|
| 946 |
|
|
DECLARE_CSR(sstatus, CSR_SSTATUS)
|
| 947 |
|
|
DECLARE_CSR(stvec, CSR_STVEC)
|
| 948 |
|
|
DECLARE_CSR(sie, CSR_SIE)
|
| 949 |
|
|
DECLARE_CSR(sscratch, CSR_SSCRATCH)
|
| 950 |
|
|
DECLARE_CSR(sepc, CSR_SEPC)
|
| 951 |
|
|
DECLARE_CSR(sip, CSR_SIP)
|
| 952 |
|
|
DECLARE_CSR(sptbr, CSR_SPTBR)
|
| 953 |
|
|
DECLARE_CSR(sasid, CSR_SASID)
|
| 954 |
|
|
DECLARE_CSR(cyclew, CSR_CYCLEW)
|
| 955 |
|
|
DECLARE_CSR(timew, CSR_TIMEW)
|
| 956 |
|
|
DECLARE_CSR(instretw, CSR_INSTRETW)
|
| 957 |
|
|
DECLARE_CSR(stime, CSR_STIME)
|
| 958 |
|
|
DECLARE_CSR(scause, CSR_SCAUSE)
|
| 959 |
|
|
DECLARE_CSR(sbadaddr, CSR_SBADADDR)
|
| 960 |
|
|
DECLARE_CSR(stimew, CSR_STIMEW)
|
| 961 |
|
|
DECLARE_CSR(mstatus, CSR_MSTATUS)
|
| 962 |
|
|
DECLARE_CSR(mtvec, CSR_MTVEC)
|
| 963 |
|
|
DECLARE_CSR(mtdeleg, CSR_MTDELEG)
|
| 964 |
|
|
DECLARE_CSR(mie, CSR_MIE)
|
| 965 |
|
|
DECLARE_CSR(mtimecmp, CSR_MTIMECMP)
|
| 966 |
|
|
DECLARE_CSR(mscratch, CSR_MSCRATCH)
|
| 967 |
|
|
DECLARE_CSR(mepc, CSR_MEPC)
|
| 968 |
|
|
DECLARE_CSR(mcause, CSR_MCAUSE)
|
| 969 |
|
|
DECLARE_CSR(mbadaddr, CSR_MBADADDR)
|
| 970 |
|
|
DECLARE_CSR(mip, CSR_MIP)
|
| 971 |
|
|
DECLARE_CSR(mtime, CSR_MTIME)
|
| 972 |
|
|
DECLARE_CSR(mcpuid, CSR_MCPUID)
|
| 973 |
|
|
DECLARE_CSR(mimpid, CSR_MIMPID)
|
| 974 |
|
|
DECLARE_CSR(mhartid, CSR_MHARTID)
|
| 975 |
|
|
DECLARE_CSR(mtohost, CSR_MTOHOST)
|
| 976 |
|
|
DECLARE_CSR(mfromhost, CSR_MFROMHOST)
|
| 977 |
|
|
DECLARE_CSR(mreset, CSR_MRESET)
|
| 978 |
|
|
DECLARE_CSR(send_ipi, CSR_SEND_IPI)
|
| 979 |
|
|
DECLARE_CSR(cycleh, CSR_CYCLEH)
|
| 980 |
|
|
DECLARE_CSR(timeh, CSR_TIMEH)
|
| 981 |
|
|
DECLARE_CSR(instreth, CSR_INSTRETH)
|
| 982 |
|
|
DECLARE_CSR(cyclehw, CSR_CYCLEHW)
|
| 983 |
|
|
DECLARE_CSR(timehw, CSR_TIMEHW)
|
| 984 |
|
|
DECLARE_CSR(instrethw, CSR_INSTRETHW)
|
| 985 |
|
|
DECLARE_CSR(stimeh, CSR_STIMEH)
|
| 986 |
|
|
DECLARE_CSR(stimehw, CSR_STIMEHW)
|
| 987 |
|
|
DECLARE_CSR(mtimecmph, CSR_MTIMECMPH)
|
| 988 |
|
|
DECLARE_CSR(mtimeh, CSR_MTIMEH)
|
| 989 |
|
|
#endif
|
| 990 |
|
|
#ifdef DECLARE_CAUSE
|
| 991 |
|
|
DECLARE_CAUSE("fflags", CAUSE_FFLAGS)
|
| 992 |
|
|
DECLARE_CAUSE("frm", CAUSE_FRM)
|
| 993 |
|
|
DECLARE_CAUSE("fcsr", CAUSE_FCSR)
|
| 994 |
|
|
DECLARE_CAUSE("cycle", CAUSE_CYCLE)
|
| 995 |
|
|
DECLARE_CAUSE("time", CAUSE_TIME)
|
| 996 |
|
|
DECLARE_CAUSE("instret", CAUSE_INSTRET)
|
| 997 |
|
|
DECLARE_CAUSE("stats", CAUSE_STATS)
|
| 998 |
|
|
DECLARE_CAUSE("uarch0", CAUSE_UARCH0)
|
| 999 |
|
|
DECLARE_CAUSE("uarch1", CAUSE_UARCH1)
|
| 1000 |
|
|
DECLARE_CAUSE("uarch2", CAUSE_UARCH2)
|
| 1001 |
|
|
DECLARE_CAUSE("uarch3", CAUSE_UARCH3)
|
| 1002 |
|
|
DECLARE_CAUSE("uarch4", CAUSE_UARCH4)
|
| 1003 |
|
|
DECLARE_CAUSE("uarch5", CAUSE_UARCH5)
|
| 1004 |
|
|
DECLARE_CAUSE("uarch6", CAUSE_UARCH6)
|
| 1005 |
|
|
DECLARE_CAUSE("uarch7", CAUSE_UARCH7)
|
| 1006 |
|
|
DECLARE_CAUSE("uarch8", CAUSE_UARCH8)
|
| 1007 |
|
|
DECLARE_CAUSE("uarch9", CAUSE_UARCH9)
|
| 1008 |
|
|
DECLARE_CAUSE("uarch10", CAUSE_UARCH10)
|
| 1009 |
|
|
DECLARE_CAUSE("uarch11", CAUSE_UARCH11)
|
| 1010 |
|
|
DECLARE_CAUSE("uarch12", CAUSE_UARCH12)
|
| 1011 |
|
|
DECLARE_CAUSE("uarch13", CAUSE_UARCH13)
|
| 1012 |
|
|
DECLARE_CAUSE("uarch14", CAUSE_UARCH14)
|
| 1013 |
|
|
DECLARE_CAUSE("uarch15", CAUSE_UARCH15)
|
| 1014 |
|
|
DECLARE_CAUSE("sstatus", CAUSE_SSTATUS)
|
| 1015 |
|
|
DECLARE_CAUSE("stvec", CAUSE_STVEC)
|
| 1016 |
|
|
DECLARE_CAUSE("sie", CAUSE_SIE)
|
| 1017 |
|
|
DECLARE_CAUSE("sscratch", CAUSE_SSCRATCH)
|
| 1018 |
|
|
DECLARE_CAUSE("sepc", CAUSE_SEPC)
|
| 1019 |
|
|
DECLARE_CAUSE("sip", CAUSE_SIP)
|
| 1020 |
|
|
DECLARE_CAUSE("sptbr", CAUSE_SPTBR)
|
| 1021 |
|
|
DECLARE_CAUSE("sasid", CAUSE_SASID)
|
| 1022 |
|
|
DECLARE_CAUSE("cyclew", CAUSE_CYCLEW)
|
| 1023 |
|
|
DECLARE_CAUSE("timew", CAUSE_TIMEW)
|
| 1024 |
|
|
DECLARE_CAUSE("instretw", CAUSE_INSTRETW)
|
| 1025 |
|
|
DECLARE_CAUSE("stime", CAUSE_STIME)
|
| 1026 |
|
|
DECLARE_CAUSE("scause", CAUSE_SCAUSE)
|
| 1027 |
|
|
DECLARE_CAUSE("sbadaddr", CAUSE_SBADADDR)
|
| 1028 |
|
|
DECLARE_CAUSE("stimew", CAUSE_STIMEW)
|
| 1029 |
|
|
DECLARE_CAUSE("mstatus", CAUSE_MSTATUS)
|
| 1030 |
|
|
DECLARE_CAUSE("mtvec", CAUSE_MTVEC)
|
| 1031 |
|
|
DECLARE_CAUSE("mtdeleg", CAUSE_MTDELEG)
|
| 1032 |
|
|
DECLARE_CAUSE("mie", CAUSE_MIE)
|
| 1033 |
|
|
DECLARE_CAUSE("mtimecmp", CAUSE_MTIMECMP)
|
| 1034 |
|
|
DECLARE_CAUSE("mscratch", CAUSE_MSCRATCH)
|
| 1035 |
|
|
DECLARE_CAUSE("mepc", CAUSE_MEPC)
|
| 1036 |
|
|
DECLARE_CAUSE("mcause", CAUSE_MCAUSE)
|
| 1037 |
|
|
DECLARE_CAUSE("mbadaddr", CAUSE_MBADADDR)
|
| 1038 |
|
|
DECLARE_CAUSE("mip", CAUSE_MIP)
|
| 1039 |
|
|
DECLARE_CAUSE("mtime", CAUSE_MTIME)
|
| 1040 |
|
|
DECLARE_CAUSE("mcpuid", CAUSE_MCPUID)
|
| 1041 |
|
|
DECLARE_CAUSE("mimpid", CAUSE_MIMPID)
|
| 1042 |
|
|
DECLARE_CAUSE("mhartid", CAUSE_MHARTID)
|
| 1043 |
|
|
DECLARE_CAUSE("mtohost", CAUSE_MTOHOST)
|
| 1044 |
|
|
DECLARE_CAUSE("mfromhost", CAUSE_MFROMHOST)
|
| 1045 |
|
|
DECLARE_CAUSE("mreset", CAUSE_MRESET)
|
| 1046 |
|
|
DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI)
|
| 1047 |
|
|
DECLARE_CAUSE("cycleh", CAUSE_CYCLEH)
|
| 1048 |
|
|
DECLARE_CAUSE("timeh", CAUSE_TIMEH)
|
| 1049 |
|
|
DECLARE_CAUSE("instreth", CAUSE_INSTRETH)
|
| 1050 |
|
|
DECLARE_CAUSE("cyclehw", CAUSE_CYCLEHW)
|
| 1051 |
|
|
DECLARE_CAUSE("timehw", CAUSE_TIMEHW)
|
| 1052 |
|
|
DECLARE_CAUSE("instrethw", CAUSE_INSTRETHW)
|
| 1053 |
|
|
DECLARE_CAUSE("stimeh", CAUSE_STIMEH)
|
| 1054 |
|
|
DECLARE_CAUSE("stimehw", CAUSE_STIMEHW)
|
| 1055 |
|
|
DECLARE_CAUSE("mtimecmph", CAUSE_MTIMECMPH)
|
| 1056 |
|
|
DECLARE_CAUSE("mtimeh", CAUSE_MTIMEH)
|
| 1057 |
|
|
#endif
|
