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sergeykhbr |
-----------------------------------------------------------------------------
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--! @file
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--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
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--! @author Sergey Khabarov - sergeykhbr@gmail.com
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--! @brief Implementation of the grethaxi device.
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--! @details This is Ethernet MAC device with the AMBA AXI inteface
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--! and EDCL debugging functionality.
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------------------------------------------------------------------------------
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--! Standard library
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library commonlib;
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use commonlib.types_common.all;
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--! AMBA system bus specific library.
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library ambalib;
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--! AXI4 configuration constants.
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use ambalib.types_amba4.all;
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--! Ethernet specific declarations.
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library ethlib;
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use ethlib.types_eth.all;
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entity grethaxi is
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generic(
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xaddr : integer := 0;
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xmask : integer := 16#FFFFF#;
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xirq : integer := 0;
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memtech : integer := 0;
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ifg_gap : integer := 24;
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attempt_limit : integer := 16;
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backoff_limit : integer := 10;
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slot_time : integer := 128;
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mdcscaler : integer range 0 to 255 := 25;
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enable_mdio : integer range 0 to 1 := 0;
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fifosize : integer range 4 to 512 := 8;
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nsync : integer range 1 to 2 := 2;
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edcl : integer range 0 to 3 := 0;
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edclbufsz : integer range 1 to 64 := 1;
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macaddrh : integer := 16#00005E#;
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macaddrl : integer := 16#000000#;
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ipaddrh : integer := 16#c0a8#;
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ipaddrl : integer := 16#0135#;
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phyrstadr : integer range 0 to 32 := 0;
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rmii : integer range 0 to 1 := 0;
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oepol : integer range 0 to 1 := 0;
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scanen : integer range 0 to 1 := 0;
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ft : integer range 0 to 2 := 0;
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edclft : integer range 0 to 2 := 0;
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mdint_pol : integer range 0 to 1 := 0;
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enable_mdint : integer range 0 to 1 := 0;
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multicast : integer range 0 to 1 := 0;
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edclsepahbg : integer range 0 to 1 := 0;
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ramdebug : integer range 0 to 2 := 0;
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mdiohold : integer := 1;
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maxsize : integer := 1500;
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gmiimode : integer range 0 to 1 := 0
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);
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port(
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rst : in std_ulogic;
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clk : in std_ulogic;
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msti : in nasti_master_in_type;
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msto : out nasti_master_out_type;
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mstcfg : out nasti_master_config_type;
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msto2 : out nasti_master_out_type;
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mstcfg2 : out nasti_master_config_type;
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slvi : in nasti_slave_in_type;
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slvo : out nasti_slave_out_type;
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slvcfg : out nasti_slave_config_type;
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ethi : in eth_in_type;
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etho : out eth_out_type;
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irq : out std_logic
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);
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end entity;
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architecture arch_grethaxi of grethaxi is
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constant bufsize : std_logic_vector(2 downto 0) :=
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conv_std_logic_vector(log2(edclbufsz), 3);
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constant xslvconfig : nasti_slave_config_type := (
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descrtype => PNP_CFG_TYPE_SLAVE,
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descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
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irq_idx => xirq,
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xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
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xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
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vid => VENDOR_GNSSSENSOR,
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did => GNSSSENSOR_ETHMAC
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);
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constant xmstconfig : nasti_master_config_type := (
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descrsize => PNP_CFG_MASTER_DESCR_BYTES,
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descrtype => PNP_CFG_TYPE_MASTER,
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vid => VENDOR_GNSSSENSOR,
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did => GAISLER_ETH_MAC_MASTER
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);
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constant xmstconfig2 : nasti_master_config_type := (
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descrsize => PNP_CFG_MASTER_DESCR_BYTES,
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descrtype => PNP_CFG_TYPE_MASTER,
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vid => VENDOR_GNSSSENSOR,
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did => GAISLER_ETH_EDCL_MASTER
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);
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type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
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of std_logic_vector(15 downto 0);
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type registers is record
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bank_slv : nasti_slave_bank_type;
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ctrl : eth_control_type;
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end record;
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signal r, rin : registers;
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signal imac_cmd : eth_command_type;
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signal omac_status : eth_mac_status_type;
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signal omac_rdbgdata : std_logic_vector(31 downto 0);
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signal omac_tmsto : eth_tx_ahb_in_type;
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signal imac_tmsti : eth_tx_ahb_out_type;
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signal omac_tmsto2 : eth_tx_ahb_in_type;
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signal imac_tmsti2 : eth_tx_ahb_out_type;
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signal omac_rmsto : eth_rx_ahb_in_type;
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signal imac_rmsti : eth_rx_ahb_out_type;
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begin
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comb : process(r, ethi, slvi, omac_rdbgdata, omac_status, rst) is
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variable v : registers;
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variable vcmd : eth_command_type;
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variable raddr_reg : local_addr_array_type;
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variable waddr_reg : local_addr_array_type;
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variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
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variable wdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
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variable wdata32 : std_logic_vector(31 downto 0);
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variable wstrb : std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
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variable val : std_logic_vector(8*CFG_ALIGN_BYTES-1 downto 0);
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begin
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v := r;
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vcmd := eth_command_none;
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procedureAxi4(slvi, xslvconfig, r.bank_slv, v.bank_slv);
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for n in 0 to CFG_WORDS_ON_BUS-1 loop
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raddr_reg(n) := r.bank_slv.raddr(n)(17 downto log2(CFG_ALIGN_BYTES));
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val := (others => '0');
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if (ramdebug = 0) or (raddr_reg(n)(15 downto 14) = "00") then
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case raddr_reg(n)(3 downto 0) is
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when "0000" => --ctrl reg
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if ramdebug /= 0 then
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val(13) := r.ctrl.ramdebugen;
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end if;
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if (edcl /= 0) then
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val(31) := '1';
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val(30 downto 28) := bufsize;
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val(14) := r.ctrl.edcldis;
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val(12) := r.ctrl.disableduplex;
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end if;
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if enable_mdint = 1 then
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val(26) := '1';
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val(10) := r.ctrl.pstatirqen;
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end if;
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if multicast = 1 then
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val(25) := '1';
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val(11) := r.ctrl.mcasten;
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end if;
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if rmii = 1 then
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val(7) := omac_status.speed;
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end if;
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val(6) := omac_status.reset;
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val(5) := r.ctrl.prom;
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val(4) := omac_status.full_duplex;
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val(3) := r.ctrl.rx_irqen;
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val(2) := r.ctrl.tx_irqen;
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val(1) := omac_status.rxen;
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val(0) := omac_status.txen;
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when "0001" => --status/int source reg
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val(9) := not (omac_status.edcltx_idle or omac_status.edclrx_idle);
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if enable_mdint = 1 then
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val(8) := omac_status.phystat;
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end if;
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val(7) := omac_status.invaddr;
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val(6) := omac_status.toosmall;
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val(5) := omac_status.txahberr;
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val(4) := omac_status.rxahberr;
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val(3) := omac_status.tx_int;
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val(2) := omac_status.rx_int;
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val(1) := omac_status.tx_err;
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val(0) := omac_status.rx_err;
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when "0010" => --mac addr lsb
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val := r.ctrl.mac_addr(31 downto 0);
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when "0011" => --mac addr msb/mdio address
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val(15 downto 0) := r.ctrl.mac_addr(47 downto 32);
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when "0100" => --mdio ctrl/status
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val(31 downto 16) := omac_status.mdio.cmd.data;
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val(15 downto 11) := r.ctrl.mdio_phyadr;
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val(10 downto 6) := omac_status.mdio.cmd.regadr;
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val(3) := omac_status.mdio.busy;
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val(2) := omac_status.mdio.linkfail;
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val(1) := omac_status.mdio.cmd.read;
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val(0) := omac_status.mdio.cmd.write;
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when "0101" => --tx descriptor
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val(31 downto 10) := r.ctrl.txdesc;
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val(9 downto 3) := omac_status.txdsel;
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when "0110" => --rx descriptor
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val(31 downto 10) := r.ctrl.rxdesc;
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val(9 downto 3) := omac_status.rxdsel;
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when "0111" => --edcl ip
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if (edcl /= 0) then
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val := r.ctrl.edclip;
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end if;
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when "1000" =>
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if multicast = 1 then
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val := r.ctrl.hash(63 downto 32);
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end if;
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when "1001" =>
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if multicast = 1 then
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val := r.ctrl.hash(31 downto 0);
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end if;
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when "1010" =>
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if edcl /= 0 then
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val(15 downto 0) := r.ctrl.emacaddr(47 downto 32);
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end if;
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when "1011" =>
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if edcl /= 0 then
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val := r.ctrl.emacaddr(31 downto 0);
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end if;
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when others => null;
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end case;
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elsif raddr_reg(n)(15 downto 14) = "01" then
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if ramdebug /= 0 then
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vcmd.dbg_access_id := DBG_ACCESS_TX_BUFFER;
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vcmd.dbg_rd_ena := r.ctrl.ramdebugen;
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vcmd.dbg_addr := raddr_reg(n)(13 downto 0);
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val := omac_rdbgdata;
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end if;
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elsif raddr_reg(n)(15 downto 14) = "10" then
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if ramdebug /= 0 then
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vcmd.dbg_access_id := DBG_ACCESS_RX_BUFFER;
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vcmd.dbg_rd_ena := r.ctrl.ramdebugen;
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vcmd.dbg_addr := raddr_reg(n)(13 downto 0);
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val := omac_rdbgdata;
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end if;
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elsif raddr_reg(n)(15 downto 14) = "11" then
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if (ramdebug = 2) and (edcl /= 0) then
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vcmd.dbg_access_id := DBG_ACCESS_EDCL_BUFFER;
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vcmd.dbg_rd_ena := r.ctrl.ramdebugen;
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vcmd.dbg_addr := raddr_reg(n)(13 downto 0);
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val := omac_rdbgdata;
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end if;
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end if;
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rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := val;
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end loop;
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if slvi.w_valid = '1' and
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r.bank_slv.wstate = wtrans and
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r.bank_slv.wresp = NASTI_RESP_OKAY then
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wdata := slvi.w_data;
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wstrb := slvi.w_strb;
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for n in 0 to CFG_WORDS_ON_BUS-1 loop
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waddr_reg(n) := r.bank_slv.waddr(n)(17 downto 2);
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wdata32 := wdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n);
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if wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n) /= "0000" then
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if (ramdebug = 0) or (waddr_reg(n)(15 downto 14) = "00") then
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case waddr_reg(n)(3 downto 0) is
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when "0000" => --ctrl reg
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if ramdebug /= 0 then
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v.ctrl.ramdebugen := wdata32(13);
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end if;
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if edcl /= 0 then
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v.ctrl.edcldis := wdata32(14);
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v.ctrl.disableduplex := wdata32(12);
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end if;
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if multicast = 1 then
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v.ctrl.mcasten := wdata32(11);
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end if;
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if enable_mdint = 1 then
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v.ctrl.pstatirqen := wdata32(10);
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end if;
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if rmii = 1 then
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vcmd.set_speed := wdata32(7);
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vcmd.clr_speed := not wdata32(7);
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end if;
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vcmd.set_reset := wdata32(6);
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vcmd.clr_reset := not wdata32(6);
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v.ctrl.prom := wdata32(5);
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vcmd.set_full_duplex := wdata32(4);
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vcmd.clr_full_duplex := not wdata32(4);
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v.ctrl.rx_irqen := wdata32(3);
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v.ctrl.tx_irqen := wdata32(2);
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vcmd.set_rxena := wdata32(1);
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vcmd.clr_rxena := not wdata32(1);
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vcmd.set_txena := wdata32(0);
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vcmd.clr_txena := not wdata32(0);
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when "0001" => --status/int source reg
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if enable_mdint = 1 then
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vcmd.clr_status_phystat := wdata32(8);
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end if;
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vcmd.clr_status_invaddr := wdata32(7);
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vcmd.clr_status_toosmall := wdata32(6);
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vcmd.clr_status_txahberr := wdata32(5);
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vcmd.clr_status_rxahberr := wdata32(4);
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vcmd.clr_status_tx_int := wdata32(3);
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vcmd.clr_status_rx_int := wdata32(2);
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vcmd.clr_status_tx_err := wdata32(1);
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vcmd.clr_status_rx_err := wdata32(0);
|
315 |
|
|
when "0010" => --mac addr lsb
|
316 |
|
|
v.ctrl.mac_addr(31 downto 0) := wdata32(31 downto 0);
|
317 |
|
|
when "0011" => --mac addr msb
|
318 |
|
|
v.ctrl.mac_addr(47 downto 32) := wdata32(15 downto 0);
|
319 |
|
|
when "0100" => --mdio ctrl/status
|
320 |
|
|
if enable_mdio = 1 then
|
321 |
|
|
vcmd.mdio_cmd.valid := not omac_status.mdio.busy;
|
322 |
|
|
if omac_status.mdio.busy = '0' then
|
323 |
|
|
v.ctrl.mdio_phyadr := wdata32(15 downto 11);
|
324 |
|
|
end if;
|
325 |
|
|
vcmd.mdio_cmd.data := wdata32(31 downto 16);
|
326 |
|
|
vcmd.mdio_cmd.regadr := wdata32(10 downto 6);
|
327 |
|
|
vcmd.mdio_cmd.read := wdata32(1);
|
328 |
|
|
vcmd.mdio_cmd.write := wdata32(0);
|
329 |
|
|
end if;
|
330 |
|
|
when "0101" => --tx descriptor
|
331 |
|
|
vcmd.set_txdsel := '1';
|
332 |
|
|
vcmd.txdsel := wdata32(9 downto 3);
|
333 |
|
|
v.ctrl.txdesc := wdata32(31 downto 10);
|
334 |
|
|
when "0110" => --rx descriptor
|
335 |
|
|
vcmd.set_rxdsel := '1';
|
336 |
|
|
vcmd.rxdsel := wdata32(9 downto 3);
|
337 |
|
|
v.ctrl.rxdesc := wdata32(31 downto 10);
|
338 |
|
|
when "0111" => --edcl ip
|
339 |
|
|
if (edcl /= 0) then
|
340 |
|
|
v.ctrl.edclip := wdata32;
|
341 |
|
|
end if;
|
342 |
|
|
when "1000" => --hash msb
|
343 |
|
|
if multicast = 1 then
|
344 |
|
|
v.ctrl.hash(63 downto 32) := wdata32;
|
345 |
|
|
end if;
|
346 |
|
|
when "1001" => --hash lsb
|
347 |
|
|
if multicast = 1 then
|
348 |
|
|
v.ctrl.hash(31 downto 0) := wdata32;
|
349 |
|
|
end if;
|
350 |
|
|
when "1010" =>
|
351 |
|
|
if edcl /= 0 then
|
352 |
|
|
v.ctrl.emacaddr(47 downto 32) := wdata32(15 downto 0);
|
353 |
|
|
end if;
|
354 |
|
|
when "1011" =>
|
355 |
|
|
if edcl /= 0 then
|
356 |
|
|
v.ctrl.emacaddr(31 downto 0) := wdata32;
|
357 |
|
|
end if;
|
358 |
|
|
when others => null;
|
359 |
|
|
end case;
|
360 |
|
|
elsif waddr_reg(n)(15 downto 14) = "01" then
|
361 |
|
|
if ramdebug /= 0 then
|
362 |
|
|
vcmd.dbg_access_id := DBG_ACCESS_TX_BUFFER;
|
363 |
|
|
vcmd.dbg_wr_ena := r.ctrl.ramdebugen;
|
364 |
|
|
vcmd.dbg_addr := waddr_reg(n)(13 downto 0);
|
365 |
|
|
vcmd.dbg_wdata := wdata32;
|
366 |
|
|
end if;
|
367 |
|
|
elsif waddr_reg(n)(15 downto 14) = "10" then
|
368 |
|
|
if ramdebug /= 0 then
|
369 |
|
|
vcmd.dbg_access_id := DBG_ACCESS_RX_BUFFER;
|
370 |
|
|
vcmd.dbg_wr_ena := r.ctrl.ramdebugen;
|
371 |
|
|
vcmd.dbg_addr := waddr_reg(n)(13 downto 0);
|
372 |
|
|
vcmd.dbg_wdata := wdata32;
|
373 |
|
|
end if;
|
374 |
|
|
elsif waddr_reg(n)(15 downto 14) = "11" then
|
375 |
|
|
if (ramdebug = 2) and (edcl /= 0) then
|
376 |
|
|
vcmd.dbg_access_id := DBG_ACCESS_EDCL_BUFFER;
|
377 |
|
|
vcmd.dbg_wr_ena := r.ctrl.ramdebugen;
|
378 |
|
|
vcmd.dbg_addr := waddr_reg(n)(13 downto 0);
|
379 |
|
|
vcmd.dbg_wdata := wdata32;
|
380 |
|
|
end if;
|
381 |
|
|
end if;
|
382 |
|
|
end if;
|
383 |
|
|
end loop;
|
384 |
|
|
end if;
|
385 |
|
|
|
386 |
|
|
slvo <= functionAxi4Output(r.bank_slv, rdata);
|
387 |
|
|
|
388 |
|
|
|
389 |
|
|
------------------------------------------------------------------------------
|
390 |
|
|
-- RESET ----------------------------------------------------------------------
|
391 |
|
|
-------------------------------------------------------------------------------
|
392 |
|
|
if rst = '0' then
|
393 |
|
|
v.bank_slv := NASTI_SLAVE_BANK_RESET;
|
394 |
|
|
v.ctrl.tx_irqen := '0';
|
395 |
|
|
v.ctrl.rx_irqen := '0';
|
396 |
|
|
v.ctrl.prom := '0';
|
397 |
|
|
v.ctrl.pstatirqen := '0';
|
398 |
|
|
v.ctrl.mcasten := '0';
|
399 |
|
|
v.ctrl.ramdebugen := '0';
|
400 |
|
|
if edcl = 3 then
|
401 |
|
|
v.ctrl.edcldis := ethi.edcldisable;
|
402 |
|
|
elsif edcl /= 0 then
|
403 |
|
|
v.ctrl.edcldis := '0';
|
404 |
|
|
end if;
|
405 |
|
|
v.ctrl.disableduplex := '0';
|
406 |
|
|
if phyrstadr /= 32 then
|
407 |
|
|
v.ctrl.mdio_phyadr := conv_std_logic_vector(phyrstadr, 5);
|
408 |
|
|
else
|
409 |
|
|
v.ctrl.mdio_phyadr := ethi.phyrstaddr;
|
410 |
|
|
end if;
|
411 |
|
|
|
412 |
|
|
v.ctrl.mac_addr := (others => '0');
|
413 |
|
|
|
414 |
|
|
v.ctrl.txdesc := (others => '0');
|
415 |
|
|
v.ctrl.rxdesc := (others => '0');
|
416 |
|
|
v.ctrl.hash := (others => '0');
|
417 |
|
|
v.ctrl.edclip := conv_std_logic_vector(ipaddrh, 16) &
|
418 |
|
|
conv_std_logic_vector(ipaddrl, 16);
|
419 |
|
|
v.ctrl.emacaddr := conv_std_logic_vector(macaddrh, 24) &
|
420 |
|
|
conv_std_logic_vector(macaddrl, 24);
|
421 |
|
|
if edcl > 1 then
|
422 |
|
|
v.ctrl.edclip(3 downto 0) := ethi.edcladdr;
|
423 |
|
|
v.ctrl.emacaddr(3 downto 0) := ethi.edcladdr;
|
424 |
|
|
end if;
|
425 |
|
|
end if;
|
426 |
|
|
|
427 |
|
|
|
428 |
|
|
rin <= v;
|
429 |
|
|
imac_cmd <= vcmd;
|
430 |
|
|
end process;
|
431 |
|
|
|
432 |
|
|
slvcfg <= xslvconfig;
|
433 |
|
|
mstcfg <= xmstconfig;
|
434 |
|
|
mstcfg2 <= xmstconfig2;
|
435 |
|
|
|
436 |
|
|
eth64 : grethc64 generic map (
|
437 |
|
|
memtech => memtech,
|
438 |
|
|
ifg_gap => ifg_gap,
|
439 |
|
|
attempt_limit => attempt_limit,
|
440 |
|
|
backoff_limit => backoff_limit,
|
441 |
|
|
mdcscaler => mdcscaler,
|
442 |
|
|
enable_mdio => enable_mdio,
|
443 |
|
|
fifosize => fifosize,
|
444 |
|
|
nsync => nsync,
|
445 |
|
|
edcl => edcl,
|
446 |
|
|
edclbufsz => edclbufsz,
|
447 |
|
|
macaddrh => macaddrh,
|
448 |
|
|
macaddrl => macaddrl,
|
449 |
|
|
ipaddrh => ipaddrh,
|
450 |
|
|
ipaddrl => ipaddrl,
|
451 |
|
|
phyrstadr => phyrstadr,
|
452 |
|
|
rmii => rmii,
|
453 |
|
|
oepol => oepol,
|
454 |
|
|
scanen => scanen,
|
455 |
|
|
mdint_pol => mdint_pol,
|
456 |
|
|
enable_mdint => enable_mdint,
|
457 |
|
|
multicast => multicast,
|
458 |
|
|
edclsepahbg => edclsepahbg,
|
459 |
|
|
ramdebug => ramdebug,
|
460 |
|
|
mdiohold => mdiohold,
|
461 |
|
|
maxsize => maxsize,
|
462 |
|
|
gmiimode => gmiimode
|
463 |
|
|
) port map (
|
464 |
|
|
rst => rst,
|
465 |
|
|
clk => clk,
|
466 |
|
|
ctrli => r.ctrl,
|
467 |
|
|
cmdi => imac_cmd,
|
468 |
|
|
statuso => omac_status,
|
469 |
|
|
rdbgdatao => omac_rdbgdata,
|
470 |
|
|
--irq
|
471 |
|
|
irq => irq,
|
472 |
|
|
--ethernet input signals
|
473 |
|
|
rmii_clk => ethi.rmii_clk,
|
474 |
|
|
tx_clk => ethi.tx_clk,
|
475 |
|
|
rx_clk => ethi.rx_clk,
|
476 |
|
|
tx_dv => ethi.tx_dv,
|
477 |
|
|
rxd => ethi.rxd,
|
478 |
|
|
rx_dv => ethi.rx_dv,
|
479 |
|
|
rx_er => ethi.rx_er,
|
480 |
|
|
rx_col => ethi.rx_col,
|
481 |
|
|
rx_en => ethi.rx_en,
|
482 |
|
|
rx_crs => ethi.rx_crs,
|
483 |
|
|
mdio_i => ethi.mdio_i,
|
484 |
|
|
phyrstaddr => ethi.phyrstaddr,
|
485 |
|
|
mdint => ethi.mdint,
|
486 |
|
|
--ethernet output signals
|
487 |
|
|
reset => etho.reset,
|
488 |
|
|
txd => etho.txd,
|
489 |
|
|
tx_en => etho.tx_en,
|
490 |
|
|
tx_er => etho.tx_er,
|
491 |
|
|
mdc => etho.mdc,
|
492 |
|
|
mdio_o => etho.mdio_o,
|
493 |
|
|
mdio_oe => etho.mdio_oe,
|
494 |
|
|
testrst => '0',
|
495 |
|
|
testen => '0',
|
496 |
|
|
testoen => '0',
|
497 |
|
|
edcladdr => ethi.edcladdr,
|
498 |
|
|
edclsepahb => ethi.edclsepahb,
|
499 |
|
|
edcldisable => ethi.edcldisable,
|
500 |
|
|
speed => etho.speed,
|
501 |
|
|
tmsto => omac_tmsto,
|
502 |
|
|
tmsti => imac_tmsti,
|
503 |
|
|
tmsto2 => omac_tmsto2,
|
504 |
|
|
tmsti2 => imac_tmsti2,
|
505 |
|
|
rmsto => omac_rmsto,
|
506 |
|
|
rmsti => imac_rmsti
|
507 |
|
|
);
|
508 |
|
|
|
509 |
|
|
etho.tx_clk <= '0';
|
510 |
|
|
etho.gbit <= '0';
|
511 |
|
|
|
512 |
|
|
--! AXI Master interface providing DMA access
|
513 |
|
|
axi0 : eth_axi_mst port map (
|
514 |
|
|
rst,
|
515 |
|
|
clk,
|
516 |
|
|
msti,
|
517 |
|
|
msto,
|
518 |
|
|
omac_tmsto,
|
519 |
|
|
imac_tmsti,
|
520 |
|
|
omac_rmsto,
|
521 |
|
|
imac_rmsti
|
522 |
|
|
);
|
523 |
|
|
|
524 |
|
|
edclmst_on : if edclsepahbg = 1 generate
|
525 |
|
|
axi1 : eth_axi_mst port map (
|
526 |
|
|
rst,
|
527 |
|
|
clk,
|
528 |
|
|
msti,
|
529 |
|
|
msto2,
|
530 |
|
|
omac_tmsto2,
|
531 |
|
|
imac_tmsti2,
|
532 |
|
|
eth_rx_in_none,
|
533 |
|
|
open
|
534 |
|
|
);
|
535 |
|
|
end generate;
|
536 |
|
|
edclmst_off : if edclsepahbg = 0 generate
|
537 |
|
|
msto2 <= nasti_master_out_none;
|
538 |
|
|
imac_tmsti2.grant <= '0';
|
539 |
|
|
imac_tmsti2.data <= (others => '0');
|
540 |
|
|
imac_tmsti2.ready <= '0';
|
541 |
|
|
imac_tmsti2.error <= '0';
|
542 |
|
|
imac_tmsti2.retry <= '0';
|
543 |
|
|
end generate;
|
544 |
|
|
|
545 |
|
|
|
546 |
|
|
regs : process(clk) is
|
547 |
|
|
begin
|
548 |
|
|
if rising_edge(clk) then r <= rin; end if;
|
549 |
|
|
end process;
|
550 |
|
|
|
551 |
|
|
end architecture;
|
552 |
|
|
|