Subversion Repositories riscv_vhdl

------------------------------------------------------------------------------

--  This file is a part of the GRLIB VHDL IP LIBRARY

--  Copyright (C) 2003 - 2008, Gaisler Research

--  Copyright (C) 2008 - 2014, Aeroflex Gaisler

--  Copyright (C) 2015 - 2016, Cobham Gaisler

--

--  This program is free software; you can redistribute it and/or modify

--  it under the terms of the GNU General Public License as published by

--  the Free Software Foundation; either version 2 of the License, or

--  (at your option) any later version.

--

--  This program is distributed in the hope that it will be useful,

--  but WITHOUT ANY WARRANTY; without even the implied warranty of

--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

--  GNU General Public License for more details.

--

--  You should have received a copy of the GNU General Public License

--  along with this program; if not, write to the Free Software

--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

-----------------------------------------------------------------------------

-- Entity:  grethc

-- File:  grethc.vhd

-- Author:  Marko Isomaki 

-- Description: Ethernet Media Access Controller with Ethernet Debug

--              Communication Link

------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library commonlib;

use commonlib.types_common.all;

library techmap;

use techmap.gencomp.all;

use techmap.types_mem.all;

library ethlib;

use ethlib.types_eth.all;

entity grethc64 is

  generic(

    memtech        : integer := 0;

    ifg_gap        : integer := 24;

    attempt_limit  : integer := 16;

    backoff_limit  : integer := 10;

    mdcscaler      : integer range 0 to 255 := 25;

    enable_mdio    : integer range 0 to 1 := 0;

    fifosize       : integer range 4 to 512 := 8;

    nsync          : integer range 1 to 2 := 2;

    edcl           : integer range 0 to 3 := 0;

    edclbufsz      : integer range 1 to 64 := 1;

    macaddrh       : integer := 16#00005E#;

    macaddrl       : integer := 16#000000#;

    ipaddrh        : integer := 16#c0a8#;

    ipaddrl        : integer := 16#0035#;

    phyrstadr      : integer range 0 to 32 := 0;

    rmii           : integer range 0 to 1  := 0;

    oepol          : integer range 0 to 1  := 0;

    scanen         : integer range 0 to 1  := 0;

    mdint_pol      : integer range 0 to 1  := 0;

    enable_mdint   : integer range 0 to 1  := 0;

    multicast      : integer range 0 to 1  := 0;

    edclsepahbg    : integer range 0 to 1  := 0;

    ramdebug       : integer range 0 to 2  := 0;

    mdiohold       : integer := 1;

    maxsize        : integer := 1500;

    gmiimode       : integer range 0 to 1 := 0

    );

  port(

    rst           : in  std_ulogic;

    clk           : in  std_ulogic;

    ctrli         : in eth_control_type;

    cmdi          : in eth_command_type;

    statuso       : out eth_mac_status_type;

    --! Debug value read from internal buffers suing external bus interface

    rdbgdatao     : out  std_logic_vector(31 downto 0);

    --irq

    irq            : out  std_logic;

    --ethernet input signals

    rmii_clk       : in   std_ulogic;

    tx_clk         : in   std_ulogic;

    rx_clk         : in   std_ulogic;

    tx_dv          : in   std_ulogic;

    rxd            : in   std_logic_vector(3 downto 0);

    rx_dv          : in   std_ulogic;

    rx_er          : in   std_ulogic;

    rx_col         : in   std_ulogic;

    rx_en          : in   std_ulogic;

    rx_crs         : in   std_ulogic;

    mdio_i         : in   std_ulogic;

    phyrstaddr     : in   std_logic_vector(4 downto 0);

    mdint          : in   std_ulogic;

    --ethernet output signals

    reset          : out  std_ulogic;

    txd            : out  std_logic_vector(3 downto 0);

    tx_en          : out  std_ulogic;

    tx_er          : out  std_ulogic;

    mdc            : out  std_ulogic;

    mdio_o         : out  std_ulogic;

    mdio_oe        : out  std_ulogic;

    --scantest

    testrst        : in   std_ulogic;

    testen         : in   std_ulogic;

    testoen        : in   std_ulogic;

    edcladdr       : in   std_logic_vector(3 downto 0) := "0000";

    edclsepahb     : in   std_ulogic;

    edcldisable    : in   std_ulogic;

    speed          : out  std_ulogic;

    tmsto          : out eth_tx_ahb_in_type;

    tmsti          : in eth_tx_ahb_out_type;

    tmsto2         : out eth_tx_ahb_in_type;

    tmsti2         : in eth_tx_ahb_out_type;

    rmsto          : out eth_rx_ahb_in_type;

    rmsti          : in eth_rx_ahb_out_type

  );

end entity;

architecture rtl of grethc64 is

  procedure sel_op_mode(

    capbil : in std_logic_vector(4 downto 0);

    speed  : out std_ulogic;

    duplex : out std_ulogic) is

    variable vspeed  : std_ulogic;

    variable vduplex : std_ulogic;

  begin

    vspeed := '0'; vduplex := '0';

    vspeed := capbil(4) or capbil(3) or capbil(2);

    vduplex := (vspeed and capbil(3)) or ((not vspeed) and capbil(1));

    speed := vspeed;

    duplex := vduplex;

  end procedure;

  --host constants

  constant fabits          : integer := log2(fifosize);

  constant burstlength     : integer := setburstlength(fifosize);

  constant burstbits       : integer := log2(burstlength);

  constant ctrlopcode      : std_logic_vector(15 downto 0) := X"8808";

  constant broadcast       : std_logic_vector(47 downto 0) := X"FFFFFFFFFFFF";

--  constant maxsizetx       : integer := 1514;

  constant index           : integer := log2(edclbufsz);

  constant receiveOK       : std_logic_vector(3 downto 0) := "0000";

  constant frameCheckError : std_logic_vector(3 downto 0) := "0100";

  constant alignmentError  : std_logic_vector(3 downto 0) := "0001";

  constant frameTooLong    : std_logic_vector(3 downto 0) := "0010";

  constant overrun         : std_logic_vector(3 downto 0) := "1000";

  constant minpload        : std_logic_vector(10 downto 0) :=

                             conv_std_logic_vector(60, 11);

  --mdio constants

  constant divisor : std_logic_vector(7 downto 0) :=

    conv_std_logic_vector(mdcscaler, 8);

  --receiver constants

  constant maxsizerx : unsigned(15 downto 0) :=

    to_unsigned(maxsize + 18 - 4, 16);

  --tranceiver constants

  constant maxsizetx : unsigned(15 downto 0) :=

    to_unsigned(maxsize + 18 - 4, 16);

  --edcl constants

  type szvct is array (0 to 6) of integer;

  constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);

  constant blbits : szvct := (6, 7, 7, 8, 8, 8, 8);

  constant winsz : szvct := (4, 4, 8, 8, 16, 32, 64);

  constant macaddrt : std_logic_vector(47 downto 0) :=

    conv_std_logic_vector(macaddrh, 24) & conv_std_logic_vector(macaddrl, 24);

  constant bpbits : integer := blbits(log2(edclbufsz));

  constant wsz : integer := winsz(log2(edclbufsz));

  constant bselbits : integer := log2(wsz);

  constant eabits: integer := log2(edclbufsz) + 8;

  constant ebufmax : std_logic_vector(bpbits-1 downto 0) := (others => '1');

  constant bufsize : std_logic_vector(2 downto 0) :=

                       conv_std_logic_vector(log2(edclbufsz), 3);

  constant ebufsize : integer := ebuf(log2(edclbufsz));

  constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);

  constant txfabits : integer := log2(txfifosize);

  constant txfifosizev : std_logic_vector(txfabits downto 0) :=

    conv_std_logic_vector(txfifosize, txfabits+1);

  constant rxburstlen      : std_logic_vector(fabits downto 0) :=

    conv_std_logic_vector(burstlength, fabits+1);

  constant txburstlen      : std_logic_vector(txfabits downto 0) :=

    conv_std_logic_vector(burstlength, txfabits+1);

  type edclrstate_type is (idle, wrda, wrdsa, wrsa, wrtype, ip, ipdata,

                           oplength, arp, iplength, ipcrc, arpop, udp, spill);

  type duplexstate_type is (start, waitop, nextop, selmode, done);

  --host types

  type txd_state_type is (idle, read_desc, check_desc, req, fill_fifo,

                          check_result, write_result, readhdr, start, wrbus1,

                          etdone, getlen, ahberror, fill_fifo2, wrbus2);

  type rxd_state_type is (idle, read_desc, check_desc, read_req, read_fifo,

                          discard, write_status, write_status2);

  --mdio types

  type mdio_state_type is (idle, preamble, startst, op, op2, phyadr, regadr,

                           ta, ta2, ta3, data, dataend);

  type fifo_access_in_type is record

    renable   : std_ulogic;

    raddress  : std_logic_vector(fabits-1 downto 0);

    write     : std_ulogic;

    waddress  : std_logic_vector(fabits-1 downto 0);

    datain    : std_logic_vector(31 downto 0);

  end record;

  type fifo_access_out_type is record

    data      : std_logic_vector(31 downto 0);

  end record;

  type tx_fifo_access_in_type is record

    renable   : std_ulogic;

    raddress  : std_logic_vector(txfabits-1 downto 0);

    write     : std_ulogic;

    waddress  : std_logic_vector(txfabits-1 downto 0);

    datain    : std_logic_vector(31 downto 0);

  end record;

  type tx_fifo_access_out_type is record

    data      : std_logic_vector(31 downto 0);

  end record;

  type edcl_ram_in_type is record

    renable   : std_ulogic;

    raddress  : std_logic_vector(eabits-1 downto 0);

    writem    : std_ulogic;

    writel    : std_ulogic;

    waddressm : std_logic_vector(eabits-1 downto 0);

    waddressl : std_logic_vector(eabits-1 downto 0);

    datain    : std_logic_vector(31 downto 0);

  end record;

  type edcl_ram_out_type is record

    data      : std_logic_vector(31 downto 0);

  end record;

  type reg_type is record

    --user registers

    status      : eth_mac_status_type;

    --master tx interface

    tmsto           : eth_tx_ahb_in_type;

    tmsto2          : eth_tx_ahb_in_type;

    txdstate        : txd_state_type;

    txwrap          : std_ulogic;

    txden           : std_ulogic;

    txirq           : std_ulogic;

    txaddr          : std_logic_vector(31 downto 2);

    txlength        : std_logic_vector(10 downto 0);

    txburstcnt      : std_logic_vector(burstbits downto 0);

    tfwpnt          : std_logic_vector(txfabits-1 downto 0);

    tfrpnt          : std_logic_vector(txfabits-1 downto 0);

    tfcnt           : std_logic_vector(txfabits downto 0);

    txcnt           : std_logic_vector(10 downto 0);

    txstart         : std_ulogic;

    txirqgen        : std_ulogic;

    txstatus        : std_logic_vector(1 downto 0);

    txvalid         : std_ulogic;

    txdata          : std_logic_vector(31 downto 0);

    writeok         : std_ulogic;

    txread          : std_logic_vector(nsync-1 downto 0);

    txrestart       : std_logic_vector(nsync downto 0);

    txdone          : std_logic_vector(nsync downto 0);

    txstart_sync    : std_ulogic;

    txreadack       : std_ulogic;

    txdataav        : std_ulogic;

    txburstav       : std_ulogic;

    --master rx interface

    rxrenable       : std_ulogic;

    rmsto           : eth_rx_ahb_in_type;

    rxdstate        : rxd_state_type;

    rxstatus        : std_logic_vector(4 downto 0);

    rxaddr          : std_logic_vector(31 downto 2);

    rxlength        : std_logic_vector(10 downto 0);

    rxbytecount     : std_logic_vector(10 downto 0);

    rxwrap          : std_ulogic;

    rxirq           : std_ulogic;

    rfwpnt          : std_logic_vector(fabits-1 downto 0);

    rfrpnt          : std_logic_vector(fabits-1 downto 0);

    rfcnt           : std_logic_vector(fabits downto 0);

    rxcnt           : std_logic_vector(10 downto 0);

    rxdoneold       : std_ulogic;

    rxdoneack       : std_ulogic;

    rxdone          : std_logic_vector(nsync-1 downto 0);

    rxstart         : std_logic_vector(nsync downto 0);

    rxwrite         : std_logic_vector(nsync-1 downto 0);

    rxwriteack      : std_ulogic;

    rxburstcnt      : std_logic_vector(burstbits downto 0);

    addrok          : std_ulogic;

    addrdone        : std_ulogic;

    ctrlpkt         : std_ulogic;

    check           : std_ulogic;

    checkdata       : std_logic_vector(31 downto 0);

    usesizefield    : std_ulogic;

    rxden           : std_ulogic;

    gotframe        : std_ulogic;

    bcast           : std_ulogic;

    msbgood         : std_ulogic;

    rxburstav       : std_ulogic;

    hashlookup      : std_ulogic;

    mcast           : std_ulogic;

    mcastacc        : std_ulogic;

    --mdio

    mdccnt          : std_logic_vector(7 downto 0);

    mdioclk         : std_ulogic;

    mdioclkold      : std_logic_vector(mdiohold-1 downto 0);

    mdio_state      : mdio_state_type;

    mdioo           : std_ulogic;

    mdioi           : std_ulogic;

    mdioen          : std_ulogic;

    cnt             : std_logic_vector(4 downto 0);

    duplexstate     : duplexstate_type;

    init_busy       : std_ulogic;

    ext             : std_ulogic;

    extcap          : std_ulogic;

    regaddr         : std_logic_vector(4 downto 0);

    phywr           : std_ulogic;

    rstphy          : std_ulogic;

    capbil          : std_logic_vector(4 downto 0);

    rstaneg         : std_ulogic;

    mdint_sync      : std_logic_vector(2 downto 0);

    --edcl

    erenable        : std_ulogic;

    edclrstate      : edclrstate_type;

    edclactive      : std_ulogic;

    nak             : std_ulogic;

    ewr             : std_ulogic;

    write           : std_logic_vector(wsz-1 downto 0);

    seq             : std_logic_vector(13 downto 0);

    abufs           : std_logic_vector(bselbits downto 0);

    tpnt            : std_logic_vector(bselbits-1 downto 0);

    rpnt            : std_logic_vector(bselbits-1 downto 0);

    tcnt            : std_logic_vector(bpbits-1 downto 0);

    rcntm           : std_logic_vector(bpbits-1 downto 0);

    rcntl           : std_logic_vector(bpbits-1 downto 0);

    ipcrc           : std_logic_vector(17 downto 0);

    applength       : std_logic_vector(15 downto 0);

    oplen           : std_logic_vector(9 downto 0);

    udpsrc          : std_logic_vector(15 downto 0);

    ecnt            : std_logic_vector(3 downto 0);

    tarp            : std_ulogic;

    tnak            : std_ulogic;

    tedcl           : std_ulogic;

    edclbcast       : std_ulogic;

    edclsepahb      : std_ulogic;

  end record;

  --host signals

  signal arst             : std_ulogic;

  signal irst             : std_ulogic;

  signal vcc              : std_ulogic;

  signal txi              : host_tx_type;

  signal txo              : tx_host_type;

  signal rxi              : host_rx_type;

  signal rxo              : rx_host_type;

    --rx ahb fifo

  signal rxrenable      : std_ulogic;

  signal rxraddress     : std_logic_vector(10 downto 0);

  signal rxwrite        : std_ulogic;

  signal rxwdata        : std_logic_vector(31 downto 0);

  signal rxwaddress     : std_logic_vector(10 downto 0);

  signal rxrdata        : std_logic_vector(31 downto 0);

    --tx ahb fifo  

  signal txrenable      : std_ulogic;

  signal txraddress     : std_logic_vector(10 downto 0);

  signal txwrite        : std_ulogic;

  signal txwdata        : std_logic_vector(31 downto 0);

  signal txwaddress     : std_logic_vector(10 downto 0);

  signal txrdata        : std_logic_vector(31 downto 0);

    --edcl buf     

  signal erenable       : std_ulogic;

  signal eraddress      : std_logic_vector(15 downto 0);

  signal ewritem        : std_ulogic;

  signal ewritel        : std_ulogic;

  signal ewaddressm     : std_logic_vector(15 downto 0);

  signal ewaddressl     : std_logic_vector(15 downto 0);

  signal ewdata         : std_logic_vector(31 downto 0);

  signal erdata         : std_logic_vector(31 downto 0);

  signal r, rin           : reg_type;

begin

  --reset generators for transmitter and receiver

  vcc <= '1';

  arst <= testrst when (scanen = 1) and (testen = '1')

          else rst and not r.status.reset;

  irst <= rst and not r.status.reset;

  comb : process(rst, irst, ctrli, cmdi, r, rmsti, tmsti, txo, rxo,

                 erdata, rxrdata, txrdata, mdio_i, phyrstaddr,

                 testen, testrst, edcladdr, mdint, tmsti2, edcldisable,

                 edclsepahb) is

    variable v             : reg_type;

    variable vpirq         : std_ulogic;

    variable vrdbgdata     : std_logic_vector(31 downto 0);

    variable txvalid       : std_ulogic;

    variable vtxfi         : tx_fifo_access_in_type;

    variable vrxfi         : fifo_access_in_type;

    variable lengthav      : std_ulogic;

    variable txdone        : std_ulogic;

    variable txread        : std_ulogic;

    variable txrestart     : std_ulogic;

    variable rxstart       : std_ulogic;

    variable rxdone        : std_ulogic;

    variable vrxwrite      : std_ulogic;

    variable ovrunstop     : std_ulogic;

    --mdio

    variable mdioindex     : integer range 0 to 31;

    variable mclk          : std_ulogic;  --rising mdio clk edge

    variable nmclk         : std_ulogic;  --falling mdio clk edge

    variable mclkvec       : std_logic_vector(mdiohold downto 0);

    --edcl

    variable veri          : edcl_ram_in_type;

    variable swap          : std_ulogic;

    variable setmz         : std_ulogic;

    variable ipcrctmp      : std_logic_vector(15 downto 0);

    variable ipcrctmp2     : std_logic_vector(17 downto 0);

    variable vrxenable     : std_ulogic;

    variable crctmp        : std_ulogic;

    variable vecnt         : integer;

  begin

    v := r; vrdbgdata := (others => '0'); vpirq := '0';

    v.check := '0'; lengthav := r.rxdoneold;-- or r.usesizefield;

    ovrunstop := '0'; vrxfi.raddress := v.rfrpnt;

    if edcl /= 0 then

      veri.renable := r.erenable;

      veri.datain := rxo.dataout;

      veri.writem := '0'; veri.writel := '0';

      veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl;

    end if;

    vtxfi.renable := '0';

    vtxfi.datain := tmsti.data;

    vtxfi.raddress := r.tfrpnt; vtxfi.write := '0';

    vtxfi.waddress := r.tfwpnt;

    vrxfi.datain := rxo.dataout;

    vrxfi.write := '0'; vrxfi.waddress := r.rfwpnt;

    vrxfi.renable := r.rxrenable; vrxenable := r.status.rxen;

    --synchronization

    v.txdone(0)     := txo.done;

    v.txread(0)     := txo.read;

    v.txrestart(0)  := txo.restart;

    v.rxstart(0)    := rxo.start;

    v.rxdone(0)     := rxo.done;

    v.rxwrite(0)    := rxo.write;

    if nsync = 2 then

      v.txdone(1)     := r.txdone(0);

      v.txread(1)     := r.txread(0);

      v.txrestart(1)  := r.txrestart(0);

      v.rxstart(1)    := r.rxstart(0);

      v.rxdone(1)     := r.rxdone(0);

      v.rxwrite(1)    := r.rxwrite(0);

    end if;

    if enable_mdint = 1 then

      v.mdint_sync(0) := mdint;

      v.mdint_sync(1) := r.mdint_sync(0);

      v.mdint_sync(2) := r.mdint_sync(1);

    end if;

    txdone     := r.txdone(nsync)     xor r.txdone(nsync-1);

    txread     := r.txreadack         xor r.txread(nsync-1);

    txrestart  := r.txrestart(nsync)  xor r.txrestart(nsync-1);

    rxstart    := r.rxstart(nsync)    xor r.rxstart(nsync-1);

    rxdone     := r.rxdoneack         xor r.rxdone(nsync-1);

    vrxwrite   := r.rxwriteack        xor r.rxwrite(nsync-1);

    if txdone = '1' then

      v.txstatus := txo.status;

    end if;

-------------------------------------------------------------------------------

-- HOST INTERFACE -------------------------------------------------------------

-------------------------------------------------------------------------------

    --SLAVE INTERFACE

    if cmdi.set_speed = '1' then v.status.speed := '1';

    elsif cmdi.clr_speed = '1' then v.status.speed := '0';

    end if;

    if cmdi.set_reset = '1' then v.status.reset := '1';

    elsif cmdi.clr_reset = '1' then v.status.reset := '0';

    end if;

    if cmdi.set_full_duplex = '1' then v.status.full_duplex := '1';

    elsif cmdi.clr_full_duplex = '1' then v.status.full_duplex := '0';

    end if;

    if cmdi.set_rxena = '1' then v.status.rxen := '1';

    elsif cmdi.clr_rxena = '1' then v.status.rxen := '0';

    end if;

    if cmdi.set_txena = '1' then v.status.txen := '1';

    elsif cmdi.clr_txena = '1' then v.status.txen := '0';

    end if;

    if cmdi.clr_status_phystat = '1' then v.status.phystat  := '0'; end if;

    if cmdi.clr_status_invaddr = '1' then v.status.invaddr  := '0'; end if;

    if cmdi.clr_status_toosmall = '1' then v.status.toosmall := '0'; end if;

    if cmdi.clr_status_txahberr = '1' then v.status.txahberr := '0'; end if;

    if cmdi.clr_status_rxahberr = '1' then v.status.rxahberr := '0';  end if;

    if cmdi.clr_status_tx_int = '1' then v.status.tx_int := '0'; end if;

    if cmdi.clr_status_rx_int = '1' then v.status.rx_int := '0'; end if;

    if cmdi.clr_status_tx_err = '1' then v.status.tx_err := '0'; end if;

    if cmdi.clr_status_rx_err = '1' then v.status.rx_err := '0'; end if;

    if cmdi.mdio_cmd.valid = '1' then

       v.status.mdio.cmd.data   := cmdi.mdio_cmd.data;

       v.status.mdio.cmd.regadr := cmdi.mdio_cmd.regadr;

       v.status.mdio.cmd.read   := cmdi.mdio_cmd.read;

       v.status.mdio.cmd.write  := cmdi.mdio_cmd.write;

       v.status.mdio.busy       := cmdi.mdio_cmd.read or cmdi.mdio_cmd.write;

    end if;

    if cmdi.dbg_access_id = DBG_ACCESS_TX_BUFFER then

       vtxfi.write    := cmdi.dbg_wr_ena;

       vtxfi.waddress := cmdi.dbg_addr(txfabits+1 downto 2);

       vtxfi.datain   := cmdi.dbg_wdata;

       vtxfi.raddress := cmdi.dbg_addr(txfabits+1 downto 2);

       vtxfi.renable  := cmdi.dbg_rd_ena;

       vrdbgdata      := txrdata;

    end if;

    if cmdi.dbg_access_id = DBG_ACCESS_RX_BUFFER then

       vrxfi.write    := cmdi.dbg_wr_ena;

       vrxfi.waddress := cmdi.dbg_addr(fabits+1 downto 2);

       vrxfi.datain   := cmdi.dbg_wdata;

       vrxfi.raddress := cmdi.dbg_addr(fabits+1 downto 2);

       vrxfi.renable  := cmdi.dbg_rd_ena;

       vrdbgdata      := rxrdata;

    end if;

    if cmdi.dbg_access_id = DBG_ACCESS_EDCL_BUFFER then

       veri.writem    := cmdi.dbg_wr_ena;

       veri.writel    := cmdi.dbg_wr_ena;

       veri.waddressm := cmdi.dbg_addr(eabits+1 downto 2);

       veri.waddressl := cmdi.dbg_addr(eabits+1 downto 2);

       veri.datain    := cmdi.dbg_wdata;

       veri.raddress  := cmdi.dbg_addr(eabits+1 downto 2);

       veri.renable   := cmdi.dbg_rd_ena;

       vrdbgdata      := erdata;

    end if;

   --PHY STATUS DETECTION

   if enable_mdint = 1 then

     if mdint_pol = 0 then

       if (r.mdint_sync(2) and not r.mdint_sync(1)) = '1' then

         v.status.phystat := '1';

         if ctrli.pstatirqen = '1' then

           vpirq := '1';

         end if;

       end if;

     else

       if (r.mdint_sync(1) and not r.mdint_sync(2)) = '1' then

         v.status.phystat := '1';

         if ctrli.pstatirqen = '1' then

           vpirq := '1';

         end if;

       end if;

     end if;

   end if;

   --MASTER INTERFACE

   v.txburstav := '0';

   if (txfifosizev - r.tfcnt) >= txburstlen then