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sergeykhbr |
-----------------------------------------------------------------------------
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--! @file
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--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
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--! @author Sergey Khabarov - sergeykhbr@gmail.com
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--! @brief This file implements RF-controller entity axi_rfctrl.
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library commonlib;
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use commonlib.types_common.all;
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--! AMBA system bus specific library
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library ambalib;
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--! AXI4 configuration constants.
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use ambalib.types_amba4.all;
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--! @brief RF-front controller based on MAX2769 ICs.
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--! @details This unit implements SPI interface with MAX2769 ICs
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--! and interacts with the antenna control signals.
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entity axi_rfctrl is
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generic (
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xaddr : integer := 0;
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xmask : integer := 16#fffff#
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);
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port (
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nrst : in std_logic;
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clk : in std_logic;
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o_cfg : out nasti_slave_config_type;
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i_axi : in nasti_slave_in_type;
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o_axi : out nasti_slave_out_type;
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i_gps_ld : in std_logic;
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i_glo_ld : in std_logic;
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--! @name Synthezator's SPI interface signals:
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--! @brief Connects to MAX2769 IC.
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--! @{
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outSCLK : out std_logic;
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outSDATA : out std_logic;
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outCSn : out std_logic_vector(1 downto 0);
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--! @}
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--! @name Antenna control signals:
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--! @brief RF front-end IO analog signals.
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--! @{
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inExtAntStat : in std_logic;
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inExtAntDetect : in std_logic;
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outExtAntEna : out std_logic;
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outIntAntContr : out std_logic
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--! @}
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);
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end;
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architecture rtl of axi_rfctrl is
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constant xconfig : nasti_slave_config_type := (
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descrtype => PNP_CFG_TYPE_SLAVE,
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descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
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irq_idx => 0,
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xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
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xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
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vid => VENDOR_GNSSSENSOR,
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did => GNSSSENSOR_RF_CONTROL
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);
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type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
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of integer;
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type registers is record
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bank_axi : nasti_slave_bank_type;
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conf1 : std_logic_vector(27 downto 0);
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conf2 : std_logic_vector(27 downto 0);
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conf3 : std_logic_vector(27 downto 0);
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pllconf : std_logic_vector(27 downto 0);
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div : std_logic_vector(27 downto 0);
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fdiv : std_logic_vector(27 downto 0);
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strm : std_logic_vector(27 downto 0);
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clkdiv : std_logic_vector(27 downto 0);
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test1 : std_logic_vector(27 downto 0);
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test2 : std_logic_vector(27 downto 0);
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scale : std_logic_vector(31 downto 0);
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load_run : std_ulogic;
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select_spi : std_logic_vector(1 downto 0);
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loading : std_ulogic;
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ScaleCnt : std_logic_vector(31 downto 0);
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SClkPosedge : std_ulogic;
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SClkNegedge : std_ulogic;
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SCLK : std_ulogic;
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BitCnt : integer range 0 to 33;
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CS : std_ulogic; --!! not inversed!!
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WordSelector : std_logic_vector(8 downto 0);
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SendWord : std_logic_vector(31 downto 0);
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ExtAntEna : std_ulogic;
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IntAntContr : std_ulogic;
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end record;
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signal r, rin : registers;
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begin
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comblogic : process(nrst, r, i_axi, i_glo_ld, i_gps_ld, inExtAntStat, inExtAntDetect)
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variable raddr_reg : local_addr_array_type;
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variable waddr_reg : local_addr_array_type;
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variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
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variable tmp : std_logic_vector(31 downto 0);
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variable wstrb : std_logic_vector(CFG_ALIGN_BYTES-1 downto 0);
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variable v : registers;
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variable readdata : std_logic_vector(31 downto 0);
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variable wNewWord : std_ulogic;
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begin
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v := r;
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v.load_run := '0';
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procedureAxi4(i_axi, xconfig, r.bank_axi, v.bank_axi);
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-- read registers:
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for n in 0 to CFG_WORDS_ON_BUS-1 loop
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raddr_reg(n) := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
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tmp := (others => '0');
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case raddr_reg(n) is
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when 0 => tmp := "0000" & r.conf1;
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when 1 => tmp := "0000" & r.conf2;
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when 2 => tmp := "0000" & r.conf3;
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when 3 => tmp := "0000" & r.pllconf;
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when 4 => tmp := "0000" & r.div;
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when 5 => tmp := "0000" & r.fdiv;
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when 6 => tmp := "0000" & r.strm;
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when 7 => tmp := "0000" & r.clkdiv;
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when 8 => tmp := "0000" & r.test1;
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when 9 => tmp := "0000" & r.test2;
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when 10 => tmp := r.scale;
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when 11 =>
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tmp(9 downto 0):= conv_std_logic_vector(r.BitCnt,6) & '0' & r.loading & i_glo_ld & i_gps_ld;
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when 15 =>
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tmp(5 downto 0) := inExtAntStat & inExtAntDetect & "00"& r.IntAntContr & r.ExtAntEna;
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when others =>
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end case;
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rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
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end loop;
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-- write registers
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if i_axi.w_valid = '1' and
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r.bank_axi.wstate = wtrans and
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r.bank_axi.wresp = NASTI_RESP_OKAY then
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for n in 0 to CFG_WORDS_ON_BUS-1 loop
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waddr_reg(n) := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
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tmp := i_axi.w_data(32*(n+1)-1 downto 32*n);
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wstrb := i_axi.w_strb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n);
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if conv_integer(wstrb) /= 0 then
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case waddr_reg(n) is
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when 0 => v.conf1 := tmp(27 downto 0);
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when 1 => v.conf2 := tmp(27 downto 0);
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when 2 => v.conf3 := tmp(27 downto 0);
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when 3 => v.pllconf := tmp(27 downto 0);
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when 4 => v.div := tmp(27 downto 0);
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when 5 => v.fdiv := tmp(27 downto 0);
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when 6 => v.strm := tmp(27 downto 0);
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when 7 => v.clkdiv := tmp(27 downto 0);
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when 8 => v.test1 := tmp(27 downto 0);
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when 9 => v.test2 := tmp(27 downto 0);
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when 10 =>
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if tmp(31 downto 1) = zero32(31 downto 1) then
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v.scale := conv_std_logic_vector(2,32);
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else
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v.scale := tmp;
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end if;
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when 11 =>
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v.load_run := '1';
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v.ScaleCnt := (others => '0');
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v.BitCnt := 0;
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if tmp = zero32 then
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v.select_spi := "01";
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elsif tmp = conv_std_logic_vector(1,32) then
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v.select_spi := "10";
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else
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v.select_spi := "00";
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end if;
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when 15 =>
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v.ExtAntEna := tmp(0);
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v.IntAntContr := tmp(1);
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when others =>
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end case;
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end if;
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end loop;
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end if;
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-- loading procedure:
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if((r.SClkNegedge='1') and (r.BitCnt=33)) then wNewWord := '1';
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else wNewWord := '0'; end if;
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if(r.load_run='1') then v.loading := '1';
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elsif((wNewWord='1')and(r.WordSelector="000000000")) then v.loading := '0'; end if;
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if((r.loading and r.SClkNegedge)='1') then v.ScaleCnt := (others => '0');
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elsif(r.loading='1') then v.ScaleCnt := r.ScaleCnt+1; end if;
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-- scaler pulse:
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if((r.scale/=zero32)and(r.ScaleCnt=r.scale)) then v.SClkNegedge := '1';
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else v.SClkNegedge := '0'; end if;
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if((r.scale/=zero32)and(r.ScaleCnt=('0'& r.scale(31 downto 1)))) then v.SClkPosedge := '1';
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else v.SClkPosedge := '0'; end if;
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-- SCLK former:
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if(r.SClkPosedge='1') then v.SCLK := '1';
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elsif(r.SClkNegedge='1') then v.SCLK := '0'; end if;
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-- Not inversed CS signal:
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if((r.SClkNegedge='1')and(r.BitCnt=33)) then v.BitCnt := 0;
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elsif(r.SClkNegedge='1') then v.BitCnt := r.BitCnt + 1; end if;
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if((r.BitCnt=0)or((r.BitCnt=33))) then v.CS := '0';
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else v.CS := '1'; end if;
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-- Word multiplexer:
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if(r.load_run='1') then v.WordSelector := "000000001";
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elsif(wNewWord='1') then v.WordSelector := r.WordSelector(7 downto 0) & '0'; end if;
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if(r.load_run='1') then v.SendWord := r.conf1 & "0000";
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elsif((wNewWord='1')and(r.WordSelector(0)='1')) then v.SendWord := r.conf2 & "0001";
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elsif((wNewWord='1')and(r.WordSelector(1)='1')) then v.SendWord := r.conf3 & "0010";
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elsif((wNewWord='1')and(r.WordSelector(2)='1')) then v.SendWord := r.pllconf & "0011";
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elsif((wNewWord='1')and(r.WordSelector(3)='1')) then v.SendWord := r.div & "0100";
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elsif((wNewWord='1')and(r.WordSelector(4)='1')) then v.SendWord := r.fdiv & "0101";
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elsif((wNewWord='1')and(r.WordSelector(5)='1')) then v.SendWord := r.strm & "0110";
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elsif((wNewWord='1')and(r.WordSelector(6)='1')) then v.SendWord := r.clkdiv & "0111";
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elsif((wNewWord='1')and(r.WordSelector(7)='1')) then v.SendWord := r.test1 & "1000";
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elsif((wNewWord='1')and(r.WordSelector(8)='1')) then v.SendWord := r.test2 & "1001";
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elsif((r.SClkNegedge='1')and(r.BitCnt/=0)and(r.BitCnt/=33)) then v.SendWord := r.SendWord(30 downto 0)&'0'; end if;
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-- reset operation
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if nrst = '0' then
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v.bank_axi := NASTI_SLAVE_BANK_RESET;
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v.load_run := '0';
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v.conf1 := (others => '0');
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v.conf2 := (others => '0');
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v.conf3 := (others => '0');
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v.pllconf := (others => '0');
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v.div := (others => '0');
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v.fdiv := (others => '0');
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v.strm := (others => '0');
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v.clkdiv := (others => '0');
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v.test1 := (others => '0');
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v.test2 := (others => '0');
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v.scale := (others => '0');
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v.SCLK := '0';
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v.BitCnt := 0;
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v.CS := '0';
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v.select_spi := (others => '0');
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v.ExtAntEna := '0';
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v.SendWord := (others=>'0');
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v.loading := '0';
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v.ScaleCnt := (others => '0');
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v.WordSelector := (others => '0');
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v.IntAntContr := '0';
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end if;
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rin <= v;
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o_axi <= functionAxi4Output(r.bank_axi, rdata);
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end process;
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o_cfg <= xconfig;
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outSCLK <= r.SCLK;
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outCSn(0) <= not(r.CS and r.select_spi(0));
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outCSn(1) <= not(r.CS and r.select_spi(1));
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outSDATA <= r.SendWord(31);
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outExtAntEna <= r.ExtAntEna;
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outIntAntContr <= r.IntAntContr;
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-- registers:
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regs : process(clk) begin
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process;
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end;
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