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sergeykhbr |
-----------------------------------------------------------------------------
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--! @file
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--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
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--! @author Sergey Khabarov - sergeykhbr@gmail.com
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--! @brief Plug'n'Play support device with AXI4 interface.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library techmap;
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use techmap.gencomp.all;
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library commonlib;
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use commonlib.types_common.all;
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--! AMBA system bus specific library.
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library ambalib;
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--! AXI4 configuration constants.
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use ambalib.types_amba4.all;
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--! @brief Hardware Configuration storage with the AMBA AXI4 interface.
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entity nasti_pnp is
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generic (
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xaddr : integer := 0;
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xmask : integer := 16#fffff#;
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tech : integer := 0;
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hw_id : std_logic_vector(31 downto 0) := X"20170101"
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);
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port (
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sys_clk : in std_logic;
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adc_clk : in std_logic;
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nrst : in std_logic;
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mstcfg : in nasti_master_cfg_vector;
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slvcfg : in nasti_slave_cfg_vector;
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cfg : out nasti_slave_config_type;
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i : in nasti_slave_in_type;
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o : out nasti_slave_out_type
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);
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end;
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architecture arch_nasti_pnp of nasti_pnp is
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constant xconfig : nasti_slave_config_type := (
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descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
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descrtype => PNP_CFG_TYPE_SLAVE,
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irq_idx => 0,
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xaddr => conv_std_logic_vector(xaddr, CFG_NASTI_CFG_ADDR_BITS),
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xmask => conv_std_logic_vector(xmask, CFG_NASTI_CFG_ADDR_BITS),
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vid => VENDOR_GNSSSENSOR,
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did => GNSSSENSOR_PNP
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);
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type local_addr_array_type is array (0 to CFG_WORDS_ON_BUS-1)
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of integer;
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type master_config_map is array (0 to 2*CFG_NASTI_MASTER_TOTAL-1)
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of std_logic_vector(31 downto 0);
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type slave_config_map is array (0 to 4*CFG_NASTI_SLAVES_TOTAL-1)
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of std_logic_vector(31 downto 0);
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type bank_type is record
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fw_id : std_logic_vector(31 downto 0);
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idt : std_logic_vector(63 downto 0); --! debug counter
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malloc_addr : std_logic_vector(63 downto 0); --! dynamic allocation addr
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malloc_size : std_logic_vector(63 downto 0); --! dynamic allocation size
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fwdbg1 : std_logic_vector(63 downto 0); --! FW marker for the debug porposes
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adc_detect : std_logic_vector(7 downto 0);
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end record;
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type registers is record
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bank_axi : nasti_slave_bank_type;
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bank0 : bank_type;
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end record;
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constant RESET_VALUE : registers := (
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NASTI_SLAVE_BANK_RESET,
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((others => '0'), (others => '0'), (others => '0'),
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(others => '0'), (others => '0'), (others => '0'))
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);
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signal r, rin : registers;
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--! @brief Detector of the ADC clock.
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--! @details If this register won't equal to 0xFF, then we suppose RF front-end
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--! not connected and FW should print message to enable 'i_int_clkrf'
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--! jumper to make possible generation of the 1 msec interrupts.
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signal r_adc_detect : std_logic_vector(7 downto 0);
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begin
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comblogic : process(i, slvcfg, mstcfg, r, r_adc_detect, nrst)
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variable v : registers;
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variable mstmap : master_config_map;
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variable slvmap : slave_config_map;
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variable raddr_reg : local_addr_array_type;
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variable waddr_reg : local_addr_array_type;
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variable rdata : std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
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variable rtmp : std_logic_vector(31 downto 0);
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variable wtmp : std_logic_vector(31 downto 0);
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variable wstrb : std_logic_vector(CFG_ALIGN_BYTES-1 downto 0);
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begin
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v := r;
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v.bank0.adc_detect := r_adc_detect;
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for k in 0 to CFG_NASTI_MASTER_TOTAL-1 loop
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mstmap(2*k) := "00" & X"00000" & mstcfg(k).descrtype & mstcfg(k).descrsize;
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mstmap(2*k+1) := mstcfg(k).vid & mstcfg(k).did;
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end loop;
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for k in 0 to CFG_NASTI_SLAVES_TOTAL-1 loop
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slvmap(4*k) := X"00" &
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conv_std_logic_vector(slvcfg(k).irq_idx,8) & "000000" &
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slvcfg(k).descrtype & slvcfg(k).descrsize;
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slvmap(4*k+1) := slvcfg(k).vid & slvcfg(k).did;
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slvmap(4*k+2) := slvcfg(k).xmask & X"000";
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slvmap(4*k+3) := slvcfg(k).xaddr & X"000";
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end loop;
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procedureAxi4(i, xconfig, r.bank_axi, v.bank_axi);
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for n in 0 to CFG_WORDS_ON_BUS-1 loop
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raddr_reg(n) := conv_integer(r.bank_axi.raddr(n)(11 downto 2));
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rtmp := (others => '0');
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if raddr_reg(n) = 0 then
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rtmp := hw_id;
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elsif raddr_reg(n) = 1 then
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rtmp := r.bank0.fw_id;
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elsif raddr_reg(n) = 2 then
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rtmp := r.bank0.adc_detect
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& conv_std_logic_vector(CFG_NASTI_MASTER_TOTAL,8)
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& conv_std_logic_vector(CFG_NASTI_SLAVES_TOTAL,8)
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& conv_std_logic_vector(tech,8);
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elsif raddr_reg(n) = 3 then
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-- reserved
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elsif raddr_reg(n) = 4 then
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rtmp := r.bank0.idt(31 downto 0);
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elsif raddr_reg(n) = 5 then
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rtmp := r.bank0.idt(63 downto 32);
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elsif raddr_reg(n) = 6 then
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rtmp := r.bank0.malloc_addr(31 downto 0);
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elsif raddr_reg(n) = 7 then
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rtmp := r.bank0.malloc_addr(63 downto 32);
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elsif raddr_reg(n) = 8 then
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rtmp := r.bank0.malloc_size(31 downto 0);
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elsif raddr_reg(n) = 9 then
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rtmp := r.bank0.malloc_size(63 downto 32);
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elsif raddr_reg(n) = 10 then
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rtmp := r.bank0.fwdbg1(31 downto 0);
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elsif raddr_reg(n) = 11 then
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rtmp := r.bank0.fwdbg1(63 downto 32);
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elsif raddr_reg(n) >= 16 and raddr_reg(n) < 16+2*CFG_NASTI_MASTER_TOTAL then
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rtmp := mstmap(raddr_reg(n) - 16);
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elsif raddr_reg(n) >= 16+2*CFG_NASTI_MASTER_TOTAL
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and raddr_reg(n) < 16+2*CFG_NASTI_MASTER_TOTAL+4*CFG_NASTI_SLAVES_TOTAL then
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rtmp := slvmap(raddr_reg(n) - 16 - 2*CFG_NASTI_MASTER_TOTAL);
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end if;
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rdata(32*(n+1)-1 downto 32*n) := rtmp;
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end loop;
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if i.w_valid = '1' and
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r.bank_axi.wstate = wtrans and
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r.bank_axi.wresp = NASTI_RESP_OKAY then
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for n in 0 to CFG_WORDS_ON_BUS-1 loop
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waddr_reg(n) := conv_integer(r.bank_axi.waddr(n)(11 downto 2));
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wtmp := i.w_data(32*(n+1)-1 downto 32*n);
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wstrb := i.w_strb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n);
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if conv_integer(wstrb) /= 0 then
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case waddr_reg(n) is
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when 1 => v.bank0.fw_id := wtmp;
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when 4 => v.bank0.idt(31 downto 0) := wtmp;
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when 5 => v.bank0.idt(63 downto 32) := wtmp;
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when 6 => v.bank0.malloc_addr(31 downto 0) := wtmp;
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when 7 => v.bank0.malloc_addr(63 downto 32) := wtmp;
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when 8 => v.bank0.malloc_size(31 downto 0) := wtmp;
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when 9 => v.bank0.malloc_size(63 downto 32) := wtmp;
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when 10 => v.bank0.fwdbg1(31 downto 0) := wtmp;
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when 11 => v.bank0.fwdbg1(63 downto 32) := wtmp;
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when others =>
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end case;
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end if;
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end loop;
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end if;
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o <= functionAxi4Output(r.bank_axi, rdata);
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if nrst = '0' then
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v := RESET_VALUE;
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end if;
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rin <= v;
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end process;
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cfg <= xconfig;
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-- registers:
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regs : process(sys_clk)
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begin
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if rising_edge(sys_clk) then
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r <= rin;
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end if;
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end process;
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-- ADC clock detector:
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regsadc : process(adc_clk)
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begin
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if rising_edge(adc_clk) then
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if nrst = '0' then
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r_adc_detect <= (others => '0');
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else
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r_adc_detect <= r_adc_detect(6 downto 0) & nrst;
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end if;
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end if;
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end process;
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end;
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