| 1 |
5 |
sergeykhbr |
git submodule foreach git pull origin master
|
| 2 |
|
|
make CONFIG=GnssConfig verilog
|
| 3 |
|
|
ModelSim: Global define for behav.srams.v +define+RANDOMIZE=1
|
| 4 |
|
|
ModelSim: Global define for rocketchip.GnssConfig.v +define+RANDOMIZE_REG_INIT=1
|
| 5 |
|
|
|
| 6 |
|
|
// VCD stimulus in ModelSim from SystemC.
|
| 7 |
|
|
// ModelSim uses only 1-bit signals, so convert VCD -> WLF -> VCD.
|
| 8 |
|
|
vcd2wlf E:/Projects/GitProjects/riscv_vhdl/debugger/win32build/Debug/intdiv.vcd -o e:/indiv.wlf
|
| 9 |
|
|
wlf2vcd e:/indiv.wlf -o e:/intdiv.vcd
|
| 10 |
|
|
vsim -t 1ps -vcdstim E:/intdiv.vcd riverlib.intdiv -do "add wave sim:/intdiv/*; run 10000000"
|
| 11 |
|
|
vsim -view e:/indiv.wlf -- Add wlf-data to wave-viewer.
|
| 12 |
|
|
add wave o_fetch:/SystemC/*
|
| 13 |
|
|
// Comparision
|
| 14 |
|
|
compare start o_mem sim
|
| 15 |
|
|
compare add -wave sim:/memaccess/o_mem_addr
|
| 16 |
|
|
compare run
|
| 17 |
|
|
compare end
|
| 18 |
|
|
|
| 19 |
|
|
//////////////////////////////
|
| 20 |
|
|
// SCALA modifications
|
| 21 |
|
|
rocketchip/Configs.scals
|
| 22 |
|
|
+class GnssConfig extends Config(new BaseConfig)
|
| 23 |
|
|
|
| 24 |
|
|
/* @brief: Enable rwx permssions and make cachable < 0x80000000
|
| 25 |
|
|
*
|
| 26 |
|
|
* This must enable rwx permissions for all memory regions
|
| 27 |
|
|
*/
|
| 28 |
|
|
//Check that build output memory mapping contains Debug regions
|
| 29 |
|
|
0x0 - 0x1000 Debug rwx
|
| 30 |
|
|
//Let's fake all memories will be mapped to this region manager
|
| 31 |
|
|
rocket/TLB.scala
|
| 32 |
|
|
val prot_r = fastCheck(_.supportsGet) !!! fastCheck need to change
|
| 33 |
|
|
val prot_w = fastCheck(_.supportsPutFull)
|
| 34 |
|
|
val prot_x = fastCheck(_.executable)
|
| 35 |
|
|
-+ val cacheable = ~mpu_physaddr(31)//fastCheck(_.supportsAcquire)
|
| 36 |
|
|
uncore/tilelink2/parameters.scala
|
| 37 |
|
|
- def find(address: BigInt) = managers.find(_.address.exists(_.contains(address)))
|
| 38 |
|
|
+ def find(address: BigInt) = managers.find(_.address.exists(_.contains(BigInt(0x0))))
|
| 39 |
|
|
|
| 40 |
|
|
// The safe version will check the entire address
|
| 41 |
|
|
- def findSafe(address: UInt) = Vec(managers.map(_.address.map(_.contains(address)).reduce(_ || _)))
|
| 42 |
|
|
+ def findSafe(address: UInt) = Vec(managers.map(_.address.map(_.contains(UInt(0x0))).reduce(_ || _)))
|
| 43 |
|
|
// The fast version assumes the address is valid
|
| 44 |
|
|
- def findFast(address: UInt) = Vec(managers.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
|
| 45 |
|
|
+ def findFast(address: UInt) = Vec(managers.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(UInt(0x0))).reduce(_ || _)))
|
| 46 |
|
|
|
| 47 |
|
|
|
| 48 |
|
|
////////////////////////////
|
| 49 |
|
|
// Generated Verilog fixes
|
| 50 |
|
|
// Use search [0:127] !!;
|
| 51 |
|
|
module BTB add reset:
|
| 52 |
|
|
if(reset) begin
|
| 53 |
|
|
`ifndef SYNTHESIS
|
| 54 |
|
|
for (initvar=0; initvar<128; initvar=initvar+1) begin
|
| 55 |
|
|
_T_2578[initvar] <= 2'b00;
|
| 56 |
|
|
end
|
| 57 |
|
|
`endif
|
| 58 |
|
|
end else if(T_2209_T_2234_en & T_2209_T_2234_mask) begin
|
| 59 |
|
|
_T_2578[T_2209_T_2234_addr] <= T_2209_T_2234_data;
|
| 60 |
|
|
end
|
| 61 |
|
|
|
| 62 |
|
|
|
| 63 |
|
|
CSRFile:: reset "reg_mideleg" and "reg_medeleg" b
|
| 64 |
|
|
if(reset) begin
|
| 65 |
|
|
reg_mideleg <= 64'd0;
|
| 66 |
|
|
end else begin
|
| 67 |
|
|
if(wen) begin
|
| 68 |
|
|
if(T_6079) begin
|
| 69 |
|
|
reg_mideleg <= T_7516;
|
| 70 |
|
|
end
|
| 71 |
|
|
end
|
| 72 |
|
|
end
|
| 73 |
|
|
if(reset) begin
|
| 74 |
|
|
reg_medeleg <= 64'd0;
|
| 75 |
|
|
end else begin
|
| 76 |
|
|
if(wen) begin
|
| 77 |
|
|
if(T_6081) begin
|
| 78 |
|
|
reg_medeleg <= T_7517;
|
| 79 |
|
|
end
|
| 80 |
|
|
end
|
| 81 |
|
|
end
|
| 82 |
|
|
|
| 83 |
|
|
|
| 84 |
|
|
/* @brief how to find registers info
|
| 85 |
|
|
*
|
| 86 |
|
|
* Find the following code in module Rocket(..)
|
| 87 |
|
|
*/
|
| 88 |
|
|
`ifdef PRINTF_COND
|
| 89 |
|
|
if (`PRINTF_COND) begin
|
| 90 |
|
|
`endif
|
| 91 |
|
|
if (T_8604) begin
|
| 92 |
|
|
$fwrite(32'h80000002,"C%d: %d [%d] pc=[%h] W[r%d=%h][%d] R[r%d=%h] R[r%d=%h] inst=[%h] DASM(%h)\n",\
|
| 93 |
|
|
io_hartid, - core
|
| 94 |
|
|
T_8594, - csr_io_time
|
| 95 |
|
|
wb_valid,
|
| 96 |
|
|
wb_reg_pc, - pc
|
| 97 |
|
|
T_8596, - register write idx r0..r31
|
| 98 |
|
|
rf_wdata, - new value
|
| 99 |
|
|
rf_wen, -
|
| 100 |
|
|
T_8597, - register read1 idx
|
| 101 |
|
|
T_8599, - read1 value
|
| 102 |
|
|
T_8600, - register read2 idx
|
| 103 |
|
|
T_8602, - read2 value
|
| 104 |
|
|
wb_reg_inst, - inst
|
| 105 |
|
|
wb_reg_inst);
|
| 106 |
|
|
end
|
| 107 |
|
|
`ifdef PRINTF_COND
|
| 108 |
|
|
|
| 109 |
|
|
|
| 110 |
|
|
|
| 111 |
|
|
---------------------------------------------
|
| 112 |
|
|
HOW TO build toolchain for soft-float?
|
| 113 |
|
|
---------------------------------------------
|
| 114 |
|
|
cd riscv-tools/riscv-gnu-toolchain
|
| 115 |
|
|
./configure --prefix=/home/teeshina/riscv/gcc-softloat --disable-float
|
| 116 |
|
|
mkdir /home/teeshina/riscv/gcc-softloat
|
| 117 |
|
|
export PATH=/home/teeshina/riscv/gcc-softloat/bin:$PATH
|
| 118 |
|
|
make
|
