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sergeykhbr |
-----------------------------------------------------------------------------
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--! @file
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--! @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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--! @author Sergey Khabarov - sergeykhbr@gmail.com
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--! @brief Instruction Cache.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library commonlib;
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use commonlib.types_common.all;
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--! RIVER CPU specific library.
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library riverlib;
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--! RIVER CPU configuration constants.
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use riverlib.river_cfg.all;
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entity ICache is
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port (
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i_clk : in std_logic; -- CPU clock
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i_nrst : in std_logic; -- Reset. Active LOW.
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-- Control path:
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i_req_ctrl_valid : in std_logic;
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i_req_ctrl_addr : in std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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o_req_ctrl_ready : out std_logic;
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o_resp_ctrl_valid : out std_logic;
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o_resp_ctrl_addr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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o_resp_ctrl_data : out std_logic_vector(31 downto 0);
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i_resp_ctrl_ready : in std_logic;
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-- Memory interface:
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i_req_mem_ready : in std_logic;
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o_req_mem_valid : out std_logic;
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o_req_mem_write : out std_logic;
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o_req_mem_addr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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o_req_mem_strob : out std_logic_vector(BUS_DATA_BYTES-1 downto 0);
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o_req_mem_data : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
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i_resp_mem_data_valid : in std_logic;
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i_resp_mem_data : in std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
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-- Debug Signals:
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o_istate : out std_logic_vector(1 downto 0)
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);
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end;
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architecture arch_ICache of ICache is
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constant State_Idle : std_logic_vector(1 downto 0) := "00";
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constant State_WaitGrant : std_logic_vector(1 downto 0) := "01";
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constant State_WaitResp : std_logic_vector(1 downto 0) := "10";
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constant State_WaitAccept : std_logic_vector(1 downto 0) := "11";
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constant Hit_Line1 : integer := 0;
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constant Hit_Line2 : integer := 1;
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constant Hit_Response : integer := 2;
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constant Hit_Total : integer := 3;
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constant ILINE_TOTAL : integer := 2;
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type line_type is record
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addr : std_logic_vector(BUS_ADDR_WIDTH-4 downto 0);
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data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
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end record;
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type iline_vector is array (0 to ILINE_TOTAL-1) of line_type;
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type line_signal_type is record
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hit : std_logic_vector(ILINE_TOTAL downto 0); -- Hit_Total = ILINE_TOTAL + 1
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hit_hold : std_logic_vector(ILINE_TOTAL-1 downto 0);
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hit_data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
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hold_data : std_logic_vector(BUS_DATA_WIDTH-1 downto 0);
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end record;
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type line_signal_vector is array (0 to ILINE_TOTAL-1) of line_signal_type;
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type RegistersType is record
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iline : iline_vector;
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iline_addr_req : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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addr_processing : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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state : std_logic_vector(1 downto 0);
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double_req : std_logic;
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delay_valid : std_logic;
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delay_data : std_logic_vector(31 downto 0);
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end record;
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type adr_type is array (0 to 1) of std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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signal r, rin : RegistersType;
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begin
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comb : process(i_nrst, i_req_ctrl_valid, i_req_ctrl_addr,
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i_resp_ctrl_ready, i_req_mem_ready,
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i_resp_mem_data_valid, i_resp_mem_data, r)
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variable v : RegistersType;
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variable w_need_mem_req : std_logic;
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variable wb_hit_word : std_logic_vector(31 downto 0);
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variable wb_l : line_signal_vector;
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variable w_reuse_lastline : std_logic;
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variable w_wait_response : std_logic;
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variable w_o_req_ctrl_ready : std_logic;
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variable w_o_req_mem_valid : std_logic;
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variable wb_o_req_mem_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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variable w_req_ctrl_valid : std_logic;
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variable w_req_fire : std_logic;
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variable w_o_resp_valid : std_logic;
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variable wb_o_resp_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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variable wb_o_resp_data : std_logic_vector(31 downto 0);
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variable wb_req_addr : adr_type;
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variable wb_hold_addr : adr_type;
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begin
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v := r;
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w_wait_response := '0';
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if r.state = State_WaitResp and i_resp_mem_data_valid = '0' then
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w_wait_response := '1';
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end if;
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w_req_ctrl_valid := not w_wait_response
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and (i_req_ctrl_valid or r.double_req);
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wb_req_addr(0) := i_req_ctrl_addr;
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wb_req_addr(1) := i_req_ctrl_addr + 2;
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wb_hold_addr(0) := r.addr_processing;
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wb_hold_addr(1) := r.addr_processing + 2;
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for i in 0 to ILINE_TOTAL-1 loop
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wb_l(i).hit := (others => '0');
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wb_l(i).hit_data := (others => '0');
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if wb_req_addr(i)(BUS_ADDR_WIDTH-1 downto 3) = r.iline(0).addr then
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wb_l(i).hit(Hit_Line1) := w_req_ctrl_valid;
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wb_l(i).hit_data := r.iline(0).data;
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elsif wb_req_addr(i)(BUS_ADDR_WIDTH-1 downto 3) = r.iline(1).addr then
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wb_l(i).hit(Hit_Line2) := w_req_ctrl_valid;
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wb_l(i).hit_data := r.iline(1).data;
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elsif wb_req_addr(i)(BUS_ADDR_WIDTH-1 downto 3) =
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r.iline_addr_req(BUS_ADDR_WIDTH-1 downto 3) then
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wb_l(i).hit(Hit_Response) := i_resp_mem_data_valid;
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wb_l(i).hit_data := i_resp_mem_data;
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end if;
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wb_l(i).hit_hold := (others => '0');
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wb_l(i).hold_data := (others => '0');
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if wb_hold_addr(i)(BUS_ADDR_WIDTH-1 downto 3) = r.iline(0).addr then
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wb_l(i).hit_hold(Hit_Line1) := '1';
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wb_l(i).hold_data := r.iline(0).data;
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elsif wb_hold_addr(i)(BUS_ADDR_WIDTH-1 downto 3) = r.iline(1).addr then
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wb_l(i).hit_hold(Hit_Line2) := '1';
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wb_l(i).hold_data := r.iline(1).data;
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elsif wb_hold_addr(i)(BUS_ADDR_WIDTH-1 downto 3) =
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r.iline_addr_req(BUS_ADDR_WIDTH-1 downto 3) then
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wb_l(i).hold_data := i_resp_mem_data;
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end if;
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end loop;
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wb_hit_word := (others => '0');
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w_need_mem_req := '1';
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if wb_l(0).hit /= "000" and wb_l(1).hit /= "000" then
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w_need_mem_req := '0';
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end if;
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case r.addr_processing(2 downto 1) is
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when "00" =>
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wb_hit_word := wb_l(0).hold_data(31 downto 0);
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when "01" =>
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wb_hit_word := wb_l(0).hold_data(47 downto 16);
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when "10" =>
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wb_hit_word := wb_l(0).hold_data(63 downto 32);
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when others =>
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wb_hit_word := wb_l(1).hold_data(15 downto 0) &
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wb_l(0).hold_data(63 downto 48);
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end case;
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if w_req_ctrl_valid = '1' and w_need_mem_req = '0' then
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v.delay_valid := '1';
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case i_req_ctrl_addr(2 downto 1) is
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when "00" =>
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v.delay_data := wb_l(0).hit_data(31 downto 0);
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when "01" =>
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v.delay_data := wb_l(0).hit_data(47 downto 16);
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when "10" =>
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v.delay_data := wb_l(0).hit_data(63 downto 32);
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when others =>
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v.delay_data := wb_l(1).hit_data(15 downto 0) &
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wb_l(0).hit_data(63 downto 48);
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end case;
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elsif i_resp_ctrl_ready = '1' then
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v.delay_valid := '0';
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v.delay_data := (others => '0');
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end if;
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w_o_req_mem_valid := w_need_mem_req and w_req_ctrl_valid;
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if r.double_req = '1' then
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if (r.addr_processing(BUS_ADDR_WIDTH-1 downto 3) =
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r.iline_addr_req(BUS_ADDR_WIDTH-1 downto 3))
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or (r.addr_processing(BUS_ADDR_WIDTH-1 downto 3) =
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wb_hold_addr(0)(BUS_ADDR_WIDTH-1 downto 3)) then
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wb_o_req_mem_addr := wb_hold_addr(1)(BUS_ADDR_WIDTH-1 downto 3) & "000";
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else
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wb_o_req_mem_addr := wb_hold_addr(0)(BUS_ADDR_WIDTH-1 downto 3) & "000";
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end if;
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elsif wb_l(0).hit = "000" then
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wb_o_req_mem_addr := wb_req_addr(0)(BUS_ADDR_WIDTH-1 downto 3) & "000";
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else
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wb_o_req_mem_addr := wb_req_addr(1)(BUS_ADDR_WIDTH-1 downto 3) & "000";
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end if;
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w_o_req_ctrl_ready := not w_need_mem_req or (i_req_mem_ready and not w_wait_response);
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w_req_fire := w_req_ctrl_valid and w_o_req_ctrl_ready;
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if (w_o_req_mem_valid and i_req_mem_ready and not w_wait_response) = '1'
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or r.double_req = '1' then
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v.iline_addr_req := wb_o_req_mem_addr;
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end if;
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case r.state is
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when State_Idle =>
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if i_req_ctrl_valid = '1' then
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if w_need_mem_req = '0' then
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v.state := State_WaitAccept;
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elsif i_req_mem_ready = '1' then
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v.state := State_WaitResp;
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else
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v.state := State_WaitGrant;
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end if;
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end if;
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when State_WaitGrant =>
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if i_req_mem_ready = '1' then
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v.state := State_WaitResp;
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elsif w_need_mem_req = '0' then
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--! Fetcher can change request address while request wasn't
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--! accepteed.
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v.state := State_WaitAccept;
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end if;
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when State_WaitResp =>
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if i_resp_mem_data_valid = '1' then
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if i_resp_ctrl_ready = '0' then
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v.state := State_WaitAccept;
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elsif w_req_ctrl_valid = '0' then
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v.state := State_Idle;
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else
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-- New request
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if w_need_mem_req = '0' then
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v.state := State_WaitAccept;
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elsif i_req_mem_ready = '1' then
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v.state := State_WaitResp;
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else
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v.state := State_WaitGrant;
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end if;
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end if;
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end if;
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when State_WaitAccept =>
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if i_resp_ctrl_ready = '1' then
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if w_req_ctrl_valid = '0' then
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v.state := State_Idle;
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else
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if w_need_mem_req = '0' then
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v.state := State_WaitAccept;
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elsif i_req_mem_ready = '1' then
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v.state := State_WaitResp;
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else
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v.state := State_WaitGrant;
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end if;
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end if;
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end if;
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when others =>
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end case;
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if w_req_fire = '1' then
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v.double_req := '0';
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if i_req_ctrl_addr(2 downto 1) = "11"
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and wb_l(0).hit = "000" and wb_l(1).hit = "000"
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and r.double_req = '0' then
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v.double_req := '1';
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end if;
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if r.double_req = '0' then
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v.addr_processing := i_req_ctrl_addr;
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end if;
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end if;
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w_reuse_lastline := '0';
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if i_resp_mem_data_valid = '1' then
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--! Condition to avoid removing the last line:
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if i_resp_ctrl_ready = '1' then
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if (wb_l(0).hit(Hit_Line2) or wb_l(1).hit(Hit_Line2)) = '1'
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and r.iline(1).addr /= i_req_ctrl_addr(BUS_ADDR_WIDTH-1 downto 3) then
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w_reuse_lastline := w_need_mem_req;
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end if;
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else
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if (wb_l(0).hit_hold(Hit_Line2) or wb_l(1).hit_hold(Hit_Line2)) = '1'
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and (wb_l(0).hit_hold(Hit_Line1) or wb_l(1).hit_hold(Hit_Line1)) = '0'
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and r.iline(1).addr /= r.iline_addr_req(BUS_ADDR_WIDTH-1 downto 3) then
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w_reuse_lastline := '1';
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end if;
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end if;
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if w_reuse_lastline = '0' then
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v.iline(1).addr := r.iline(0).addr;
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v.iline(1).data := r.iline(0).data;
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end if;
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v.iline(0).addr := r.iline_addr_req(BUS_ADDR_WIDTH-1 downto 3);
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v.iline(0).data := i_resp_mem_data;
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end if;
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if r.state = State_WaitAccept then
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w_o_resp_valid := not r.double_req;
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else
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|
w_o_resp_valid := i_resp_mem_data_valid and not r.double_req;
|
308 |
|
|
end if;
|
309 |
|
|
if r.delay_valid = '1' then
|
310 |
|
|
wb_o_resp_data := r.delay_data;
|
311 |
|
|
else
|
312 |
|
|
wb_o_resp_data := wb_hit_word;
|
313 |
|
|
end if;
|
314 |
|
|
wb_o_resp_addr := r.addr_processing;
|
315 |
|
|
|
316 |
|
|
|
317 |
|
|
if i_nrst = '0' then
|
318 |
|
|
v.iline(0).addr := (others => '1');
|
319 |
|
|
v.iline(0).data := (others => '0');
|
320 |
|
|
v.iline(1).addr := (others => '1');
|
321 |
|
|
v.iline(1).data := (others => '0');
|
322 |
|
|
v.iline_addr_req := (others => '0');
|
323 |
|
|
v.addr_processing := (others => '0');
|
324 |
|
|
v.state := State_Idle;
|
325 |
|
|
v.double_req := '0';
|
326 |
|
|
v.delay_valid := '0';
|
327 |
|
|
v.delay_data := (others => '0');
|
328 |
|
|
end if;
|
329 |
|
|
|
330 |
|
|
o_req_ctrl_ready <= w_o_req_ctrl_ready;
|
331 |
|
|
|
332 |
|
|
o_req_mem_valid <= w_o_req_mem_valid;
|
333 |
|
|
o_req_mem_addr <= wb_o_req_mem_addr;
|
334 |
|
|
o_req_mem_write <= '0';
|
335 |
|
|
o_req_mem_strob <= (others => '0');
|
336 |
|
|
o_req_mem_data <= (others => '0');
|
337 |
|
|
|
338 |
|
|
o_resp_ctrl_valid <= w_o_resp_valid;
|
339 |
|
|
o_resp_ctrl_data <= wb_o_resp_data;
|
340 |
|
|
o_resp_ctrl_addr <= wb_o_resp_addr;
|
341 |
|
|
o_istate <= r.state;
|
342 |
|
|
|
343 |
|
|
rin <= v;
|
344 |
|
|
end process;
|
345 |
|
|
|
346 |
|
|
-- registers:
|
347 |
|
|
regs : process(i_clk)
|
348 |
|
|
begin
|
349 |
|
|
if rising_edge(i_clk) then
|
350 |
|
|
r <= rin;
|
351 |
|
|
end if;
|
352 |
|
|
end process;
|
353 |
|
|
|
354 |
|
|
end;
|