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sergeykhbr |
-----------------------------------------------------------------------------
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--! @file
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--! @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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--! @author Sergey Khabarov - sergeykhbr@gmail.com
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--! @brief Debug port must be connected to DSU.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library commonlib;
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use commonlib.types_common.all;
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--! RIVER CPU specific library.
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library riverlib;
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--! RIVER CPU configuration constants.
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use riverlib.river_cfg.all;
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entity DbgPort is
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port (
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i_clk : in std_logic; -- CPU clock
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i_nrst : in std_logic; -- Reset. Active LOW.
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-- "RIVER" Debug interface
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i_dport_valid : in std_logic; -- Debug access from DSU is valid
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i_dport_write : in std_logic; -- Write command flag
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i_dport_region : in std_logic_vector(1 downto 0); -- Registers region ID: 0=CSR; 1=IREGS; 2=Control
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i_dport_addr : in std_logic_vector(11 downto 0); -- Register idx
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i_dport_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0);-- Write value
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o_dport_ready : out std_logic; -- Response is ready
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o_dport_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0);-- Response value
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-- CPU debugging signals:
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o_core_addr : out std_logic_vector(11 downto 0); -- Address of the sub-region register
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o_core_wdata : out std_logic_vector(RISCV_ARCH-1 downto 0);-- Write data
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o_csr_ena : out std_logic; -- Region 0: Access to CSR bank is enabled.
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o_csr_write : out std_logic; -- Region 0: CSR write enable
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i_csr_rdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Region 0: CSR read value
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o_ireg_ena : out std_logic; -- Region 1: Access to integer register bank is enabled
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o_ireg_write : out std_logic; -- Region 1: Integer registers bank write pulse
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o_npc_write : out std_logic; -- Region 1: npc write enable
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i_ireg_rdata : in std_logic_vector(RISCV_ARCH-1 downto 0);-- Region 1: Integer register read value
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i_pc : in std_logic_vector(BUS_ADDR_WIDTH-1 downto 0); -- Region 1: Instruction pointer
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i_npc : in std_logic_vector(BUS_ADDR_WIDTH-1 downto 0); -- Region 1: Next Instruction pointer
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i_e_valid : in std_logic; -- Stepping control signal
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i_e_call : in std_logic; -- pseudo-instruction CALL
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i_e_ret : in std_logic; -- pseudo-instruction RET
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i_m_valid : in std_logic; -- To compute number of valid executed instruction
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o_clock_cnt : out std_logic_vector(63 downto 0); -- Number of clocks excluding halt state
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o_executed_cnt : out std_logic_vector(63 downto 0); -- Number of executed instructions
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o_halt : out std_logic; -- Halt signal is equal to hold pipeline
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i_ebreak : in std_logic; -- ebreak instruction decoded
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o_break_mode : out std_logic; -- Behaviour on EBREAK instruction: 0 = halt; 1 = generate trap
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o_br_fetch_valid : out std_logic; -- Fetch injection address/instr are valid
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o_br_address_fetch : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0); -- Fetch injection address to skip ebreak instruciton only once
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o_br_instr_fetch : out std_logic_vector(31 downto 0); -- Real instruction value that was replaced by ebreak
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-- Debug signals:
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i_istate : in std_logic_vector(1 downto 0); -- ICache state machine value
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i_dstate : in std_logic_vector(1 downto 0); -- DCache state machine value
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i_cstate : in std_logic_vector(1 downto 0); -- CacheTop state machine value
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i_instr_buf : in std_logic_vector(DBG_FETCH_TRACE_SIZE*64-1 downto 0) -- trace last fetched instructions
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);
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end;
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architecture arch_DbgPort of DbgPort is
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constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
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constant one64 : std_logic_vector(63 downto 0) := X"0000000000000001";
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constant STACKTR_ADRSZ : integer := log2(CFG_STACK_TRACE_BUF_SIZE);
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type RegistersType is record
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ready : std_logic;
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halt : std_logic;
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breakpoint : std_logic;
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stepping_mode : std_logic;
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stepping_mode_cnt : std_logic_vector(RISCV_ARCH-1 downto 0);
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trap_on_break : std_logic;
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br_address_fetch : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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br_instr_fetch : std_logic_vector(31 downto 0);
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br_fetch_valid : std_logic;
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rdata : std_logic_vector(RISCV_ARCH-1 downto 0);
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stepping_mode_steps : std_logic_vector(RISCV_ARCH-1 downto 0); -- Number of steps before halt in stepping mode
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clock_cnt : std_logic_vector(63 downto 0); -- Timer in clocks.
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executed_cnt : std_logic_vector(63 downto 0); -- Number of valid executed instructions
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stack_trace_cnt : integer range 0 to CFG_STACK_TRACE_BUF_SIZE-1; -- Stack trace buffer counter
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rd_trbuf_ena : std_logic;
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rd_trbuf_addr0 : std_logic;
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end record;
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signal r, rin : RegistersType;
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signal wb_stack_raddr : std_logic_vector(STACKTR_ADRSZ-1 downto 0);
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signal wb_stack_rdata : std_logic_vector(2*BUS_ADDR_WIDTH-1 downto 0);
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signal w_stack_we : std_logic;
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signal wb_stack_waddr : std_logic_vector(STACKTR_ADRSZ-1 downto 0);
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signal wb_stack_wdata : std_logic_vector(2*BUS_ADDR_WIDTH-1 downto 0);
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component StackTraceBuffer is
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generic (
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abits : integer := 5;
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dbits : integer := 64
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);
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port (
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i_clk : in std_logic;
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i_raddr : in std_logic_vector(abits-1 downto 0);
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o_rdata : out std_logic_vector(dbits-1 downto 0);
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i_we : in std_logic;
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i_waddr : in std_logic_vector(abits-1 downto 0);
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i_wdata : in std_logic_vector(dbits-1 downto 0)
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);
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end component;
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begin
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stacktr_ena : if CFG_STACK_TRACE_BUF_SIZE /= 0 generate
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stacktr0 : StackTraceBuffer generic map (
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abits => STACKTR_ADRSZ,
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dbits => 2*BUS_ADDR_WIDTH
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) port map (
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i_clk => i_clk,
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i_raddr => wb_stack_raddr,
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o_rdata => wb_stack_rdata,
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i_we => w_stack_we,
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i_waddr => wb_stack_waddr,
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i_wdata => wb_stack_wdata
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);
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end generate;
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comb : process(i_nrst, i_dport_valid, i_dport_write, i_dport_region,
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i_dport_addr, i_dport_wdata, i_ireg_rdata, i_csr_rdata,
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i_pc, i_npc, i_e_valid, i_m_valid, i_ebreak, r,
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wb_stack_rdata, i_e_call, i_e_ret, i_istate, i_dstate,
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i_cstate, i_instr_buf)
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variable v : RegistersType;
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variable wb_o_core_addr : std_logic_vector(11 downto 0);
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variable wb_o_core_wdata : std_logic_vector(RISCV_ARCH-1 downto 0);
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variable wb_rdata : std_logic_vector(63 downto 0);
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variable wb_o_rdata : std_logic_vector(63 downto 0);
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variable wb_idx : integer range 0 to 4095;
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variable w_o_csr_ena : std_logic;
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variable w_o_csr_write : std_logic;
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variable w_o_ireg_ena : std_logic;
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variable w_o_ireg_write : std_logic;
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variable w_o_npc_write : std_logic;
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variable w_cur_halt : std_logic;
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begin
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v := r;
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wb_o_core_addr := (others => '0');
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wb_o_core_wdata := (others => '0');
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wb_rdata := (others => '0');
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wb_o_rdata := (others => '0');
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wb_idx := conv_integer(i_dport_addr);
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w_o_csr_ena := '0';
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w_o_csr_write := '0';
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w_o_ireg_ena := '0';
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w_o_ireg_write := '0';
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w_o_npc_write := '0';
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v.br_fetch_valid := '0';
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v.rd_trbuf_ena := '0';
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wb_stack_raddr <= (others => '0');
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w_stack_we <= '0';
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wb_stack_waddr <= (others => '0');
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wb_stack_wdata <= (others => '0');
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v.ready := i_dport_valid;
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w_cur_halt := '0';
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if i_e_valid = '1' then
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if r.stepping_mode_cnt /= zero64(RISCV_ARCH-1 downto 0) then
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v.stepping_mode_cnt := r.stepping_mode_cnt - 1;
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if r.stepping_mode_cnt = one64 then
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v.halt := '1';
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w_cur_halt := '1';
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v.stepping_mode := '0';
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end if;
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end if;
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end if;
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if r.halt = '0' then
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v.clock_cnt := r.clock_cnt + 1;
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end if;
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if i_m_valid = '1' then
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v.executed_cnt := r.executed_cnt + 1;
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end if;
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if i_ebreak = '1' then
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v.breakpoint := '1';
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if r.trap_on_break = '0' then
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v.halt := '1';
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end if;
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end if;
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if CFG_STACK_TRACE_BUF_SIZE /= 0 then
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if i_e_call = '1' and r.stack_trace_cnt /= (CFG_STACK_TRACE_BUF_SIZE - 1) then
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w_stack_we <= '1';
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wb_stack_waddr <= conv_std_logic_vector(r.stack_trace_cnt, STACKTR_ADRSZ);
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wb_stack_wdata <= i_npc & i_pc;
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v.stack_trace_cnt := r.stack_trace_cnt + 1;
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elsif i_e_ret = '1' and r.stack_trace_cnt /= 0 then
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v.stack_trace_cnt := r.stack_trace_cnt - 1;
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end if;
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end if;
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if i_dport_valid = '1' then
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case i_dport_region is
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when "00" =>
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w_o_csr_ena := '1';
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wb_o_core_addr := i_dport_addr;
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wb_rdata := i_csr_rdata;
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if i_dport_write = '1' then
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w_o_csr_write := '1';
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wb_o_core_wdata := i_dport_wdata;
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end if;
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when "01" =>
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if wb_idx < 32 then
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w_o_ireg_ena := '1';
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wb_o_core_addr := i_dport_addr;
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wb_rdata := i_ireg_rdata;
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if i_dport_write = '1' then
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w_o_ireg_write := '1';
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wb_o_core_wdata := i_dport_wdata;
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end if;
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elsif wb_idx = 32 then
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--! Read only register
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wb_rdata(BUS_ADDR_WIDTH-1 downto 0) := i_pc;
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elsif wb_idx = 33 then
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wb_rdata(BUS_ADDR_WIDTH-1 downto 0) := i_npc;
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if i_dport_write = '1' then
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w_o_npc_write := '1';
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wb_o_core_wdata := i_dport_wdata;
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end if;
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elsif wb_idx = 34 then
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wb_rdata(STACKTR_ADRSZ-1 downto 0) :=
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conv_std_logic_vector(r.stack_trace_cnt, STACKTR_ADRSZ);
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if i_dport_write = '1' then
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v.stack_trace_cnt := conv_integer(i_dport_wdata);
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end if;
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elsif (wb_idx >= 128) and (wb_idx < (128 + 2 * CFG_STACK_TRACE_BUF_SIZE)) then
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v.rd_trbuf_ena := '1';
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v.rd_trbuf_addr0 := conv_std_logic_vector(wb_idx, 1)(0);
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wb_stack_raddr <= conv_std_logic_vector((wb_idx - 128) / 2, STACKTR_ADRSZ);
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elsif wb_idx = 256 then
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wb_rdata := i_instr_buf(63 downto 0);
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elsif wb_idx = 257 then
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wb_rdata := i_instr_buf(127 downto 64);
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elsif wb_idx = 258 then
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wb_rdata := i_instr_buf(191 downto 128);
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elsif wb_idx = 259 then
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wb_rdata := i_instr_buf(255 downto 192);
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end if;
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when "10" =>
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case wb_idx is
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when 0 =>
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wb_rdata(0) := r.halt;
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wb_rdata(2) := r.breakpoint;
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wb_rdata(33 downto 32) := i_istate;
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wb_rdata(37 downto 36) := i_dstate;
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wb_rdata(41 downto 40) := i_cstate;
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if i_dport_write = '1' then
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v.halt := i_dport_wdata(0);
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v.stepping_mode := i_dport_wdata(1);
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if i_dport_wdata(1) = '1' then
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v.stepping_mode_cnt := r.stepping_mode_steps;
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end if;
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end if;
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when 1 =>
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wb_rdata := r.stepping_mode_steps;
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if i_dport_write = '1' then
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v.stepping_mode_steps := i_dport_wdata;
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end if;
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when 2 =>
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wb_rdata := r.clock_cnt;
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when 3 =>
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wb_rdata := r.executed_cnt;
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when 4 =>
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--! Trap on instruction:
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--! 0 = Halt pipeline on ECALL instruction
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--! 1 = Generate trap on ECALL instruction
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wb_rdata(0) := r.trap_on_break;
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if i_dport_write = '1' then
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v.trap_on_break := i_dport_wdata(0);
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end if;
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when 5 =>
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-- todo: add hardware breakpoint
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when 6 =>
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-- todo: remove hardware breakpoint
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when 7 =>
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wb_rdata(BUS_ADDR_WIDTH-1 downto 0) := r.br_address_fetch;
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if i_dport_write = '1' then
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v.br_address_fetch := i_dport_wdata(BUS_ADDR_WIDTH-1 downto 0);
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end if;
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when 8 =>
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wb_rdata(31 downto 0) := r.br_instr_fetch;
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if i_dport_write = '1' then
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v.br_fetch_valid := '1';
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v.breakpoint := '0';
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v.br_instr_fetch := i_dport_wdata(31 downto 0);
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|
end if;
|
298 |
|
|
when others =>
|
299 |
|
|
end case;
|
300 |
|
|
when others =>
|
301 |
|
|
end case;
|
302 |
|
|
end if;
|
303 |
|
|
v.rdata := wb_rdata;
|
304 |
|
|
if r.rd_trbuf_ena = '1' then
|
305 |
|
|
if r.rd_trbuf_addr0 = '0' then
|
306 |
|
|
wb_o_rdata(BUS_ADDR_WIDTH-1 downto 0) :=
|
307 |
|
|
wb_stack_rdata(BUS_ADDR_WIDTH-1 downto 0);
|
308 |
|
|
else
|
309 |
|
|
wb_o_rdata(BUS_ADDR_WIDTH-1 downto 0) :=
|
310 |
|
|
wb_stack_rdata(2*BUS_ADDR_WIDTH-1 downto BUS_ADDR_WIDTH);
|
311 |
|
|
end if;
|
312 |
|
|
else
|
313 |
|
|
wb_o_rdata := r.rdata;
|
314 |
|
|
end if;
|
315 |
|
|
|
316 |
|
|
|
317 |
|
|
if i_nrst = '0' then
|
318 |
|
|
v.ready := '0';
|
319 |
|
|
v.halt := '0';
|
320 |
|
|
v.breakpoint := '0';
|
321 |
|
|
v.stepping_mode := '0';
|
322 |
|
|
v.rdata := (others => '0');
|
323 |
|
|
v.stepping_mode_cnt := (others => '0');
|
324 |
|
|
v.stepping_mode_steps := (others => '0');
|
325 |
|
|
v.clock_cnt := (others => '0');
|
326 |
|
|
v.executed_cnt := (others => '0');
|
327 |
|
|
v.trap_on_break := '0';
|
328 |
|
|
v.br_address_fetch := (others => '0');
|
329 |
|
|
v.br_instr_fetch := (others => '0');
|
330 |
|
|
v.br_fetch_valid := '0';
|
331 |
|
|
v.stack_trace_cnt := 0;
|
332 |
|
|
v.rd_trbuf_ena := '0';
|
333 |
|
|
v.rd_trbuf_addr0 := '0';
|
334 |
|
|
end if;
|
335 |
|
|
|
336 |
|
|
rin <= v;
|
337 |
|
|
|
338 |
|
|
o_core_addr <= wb_o_core_addr;
|
339 |
|
|
o_core_wdata <= wb_o_core_wdata;
|
340 |
|
|
o_csr_ena <= w_o_csr_ena;
|
341 |
|
|
o_csr_write <= w_o_csr_write;
|
342 |
|
|
o_ireg_ena <= w_o_ireg_ena;
|
343 |
|
|
o_ireg_write <= w_o_ireg_write;
|
344 |
|
|
o_npc_write <= w_o_npc_write;
|
345 |
|
|
o_clock_cnt <= r.clock_cnt;
|
346 |
|
|
o_executed_cnt <= r.executed_cnt;
|
347 |
|
|
o_halt <= r.halt or w_cur_halt;
|
348 |
|
|
o_break_mode <= r.trap_on_break;
|
349 |
|
|
o_br_fetch_valid <= r.br_fetch_valid;
|
350 |
|
|
o_br_address_fetch <= r.br_address_fetch;
|
351 |
|
|
o_br_instr_fetch <= r.br_instr_fetch;
|
352 |
|
|
|
353 |
|
|
o_dport_ready <= r.ready;
|
354 |
|
|
o_dport_rdata <= wb_o_rdata;
|
355 |
|
|
end process;
|
356 |
|
|
|
357 |
|
|
|
358 |
|
|
-- registers:
|
359 |
|
|
regs : process(i_clk)
|
360 |
|
|
begin
|
361 |
|
|
if rising_edge(i_clk) then
|
362 |
|
|
r <= rin;
|
363 |
|
|
end if;
|
364 |
|
|
end process;
|
365 |
|
|
|
366 |
|
|
end;
|