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sergeykhbr |
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--! @file
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--! @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
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--! @author Sergey Khabarov - sergeykhbr@gmail.com
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--! @brief "River" CPU Top level.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library commonlib;
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use commonlib.types_common.all;
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--! RIVER CPU specific library.
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library riverlib;
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--! RIVER CPU configuration constants.
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use riverlib.river_cfg.all;
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entity RiverTop is
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port (
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i_clk : in std_logic; -- CPU clock
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i_nrst : in std_logic; -- Reset. Active LOW.
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-- Memory interface:
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i_req_mem_ready : in std_logic; -- AXI request was accepted
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o_req_mem_valid : out std_logic; -- AXI memory request is valid
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o_req_mem_write : out std_logic; -- AXI memory request is write type
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o_req_mem_addr : out std_logic_vector(BUS_ADDR_WIDTH-1 downto 0); -- AXI memory request address
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o_req_mem_strob : out std_logic_vector(BUS_DATA_BYTES-1 downto 0);-- Writing strob. 1 bit per Byte
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o_req_mem_data : out std_logic_vector(BUS_DATA_WIDTH-1 downto 0); -- Writing data
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i_resp_mem_data_valid : in std_logic; -- AXI response is valid
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i_resp_mem_data : in std_logic_vector(BUS_DATA_WIDTH-1 downto 0); -- Read data
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-- Interrupt line from external interrupts controller (PLIC).
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i_ext_irq : in std_logic;
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o_time : out std_logic_vector(63 downto 0); -- Timer. Clock counter except halt state.
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-- Debug interface:
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i_dport_valid : in std_logic; -- Debug access from DSU is valid
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i_dport_write : in std_logic; -- Write command flag
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i_dport_region : in std_logic_vector(1 downto 0); -- Registers region ID: 0=CSR; 1=IREGS; 2=Control
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i_dport_addr : in std_logic_vector(11 downto 0); -- Register idx
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i_dport_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Write value
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o_dport_ready : out std_logic; -- Response is ready
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o_dport_rdata : out std_logic_vector(RISCV_ARCH-1 downto 0) -- Response value
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);
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end;
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architecture arch_RiverTop of RiverTop is
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-- Control path:
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signal w_req_ctrl_ready : std_logic;
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signal w_req_ctrl_valid : std_logic;
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signal wb_req_ctrl_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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signal w_resp_ctrl_valid : std_logic;
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signal wb_resp_ctrl_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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signal wb_resp_ctrl_data : std_logic_vector(31 downto 0);
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signal w_resp_ctrl_ready : std_logic;
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-- Data path:
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signal w_req_data_ready : std_logic;
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signal w_req_data_valid : std_logic;
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signal w_req_data_write : std_logic;
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signal wb_req_data_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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signal wb_req_data_size : std_logic_vector(1 downto 0);
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signal wb_req_data_data : std_logic_vector(RISCV_ARCH-1 downto 0);
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signal w_resp_data_valid : std_logic;
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signal wb_resp_data_addr : std_logic_vector(BUS_ADDR_WIDTH-1 downto 0);
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signal wb_resp_data_data : std_logic_vector(RISCV_ARCH-1 downto 0);
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signal w_resp_data_ready : std_logic;
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signal wb_istate : std_logic_vector(1 downto 0);
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signal wb_dstate : std_logic_vector(1 downto 0);
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signal wb_cstate : std_logic_vector(1 downto 0);
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begin
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proc0 : Processor port map (
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i_clk => i_clk,
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i_nrst => i_nrst,
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i_req_ctrl_ready => w_req_ctrl_ready,
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o_req_ctrl_valid => w_req_ctrl_valid,
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o_req_ctrl_addr => wb_req_ctrl_addr,
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i_resp_ctrl_valid => w_resp_ctrl_valid,
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i_resp_ctrl_addr => wb_resp_ctrl_addr,
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i_resp_ctrl_data => wb_resp_ctrl_data,
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o_resp_ctrl_ready => w_resp_ctrl_ready,
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i_req_data_ready => w_req_data_ready,
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o_req_data_valid => w_req_data_valid,
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o_req_data_write => w_req_data_write,
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o_req_data_addr => wb_req_data_addr,
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o_req_data_size => wb_req_data_size,
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o_req_data_data => wb_req_data_data,
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i_resp_data_valid => w_resp_data_valid,
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i_resp_data_addr => wb_resp_data_addr,
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i_resp_data_data => wb_resp_data_data,
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o_resp_data_ready => w_resp_data_ready,
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i_ext_irq => i_ext_irq,
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o_time => o_time,
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i_dport_valid => i_dport_valid,
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i_dport_write => i_dport_write,
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i_dport_region => i_dport_region,
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i_dport_addr => i_dport_addr,
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i_dport_wdata => i_dport_wdata,
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o_dport_ready => o_dport_ready,
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o_dport_rdata => o_dport_rdata,
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i_istate => wb_istate,
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i_dstate => wb_dstate,
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i_cstate => wb_cstate);
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cache0 : CacheTop port map (
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i_clk => i_clk,
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i_nrst => i_nrst,
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i_req_ctrl_valid => w_req_ctrl_valid,
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i_req_ctrl_addr => wb_req_ctrl_addr,
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o_req_ctrl_ready => w_req_ctrl_ready,
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o_resp_ctrl_valid => w_resp_ctrl_valid,
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o_resp_ctrl_addr => wb_resp_ctrl_addr,
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o_resp_ctrl_data => wb_resp_ctrl_data,
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i_resp_ctrl_ready => w_resp_ctrl_ready,
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i_req_data_valid => w_req_data_valid,
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i_req_data_write => w_req_data_write,
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i_req_data_addr => wb_req_data_addr,
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i_req_data_size => wb_req_data_size,
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i_req_data_data => wb_req_data_data,
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o_req_data_ready => w_req_data_ready,
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o_resp_data_valid => w_resp_data_valid,
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o_resp_data_addr => wb_resp_data_addr,
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o_resp_data_data => wb_resp_data_data,
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i_resp_data_ready => w_resp_data_ready,
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i_req_mem_ready => i_req_mem_ready,
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o_req_mem_valid => o_req_mem_valid,
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o_req_mem_write => o_req_mem_write,
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o_req_mem_addr => o_req_mem_addr,
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o_req_mem_strob => o_req_mem_strob,
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o_req_mem_data => o_req_mem_data,
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i_resp_mem_data_valid => i_resp_mem_data_valid,
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i_resp_mem_data => i_resp_mem_data,
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o_istate => wb_istate,
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o_dstate => wb_dstate,
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o_cstate => wb_cstate);
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end;
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