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sergeykhbr |
----------------------------------------------------------------------------
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--! @file
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--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
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--! @author Sergey Khabarov
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--! @brief Declaration types_mem package components.
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------------------------------------------------------------------------------
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--! Standard library
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library ieee;
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use ieee.std_logic_1164.all;
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--! Provide common generic log() function
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library commonlib;
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use commonlib.types_common.all;
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--! AMBA system bus specific library.
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library ambalib;
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--! AXI4 configuration constants.
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use ambalib.types_amba4.all;
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--! @brief Declaration of 'virtual' Memory components.
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package types_mem is
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--! @brief Declaration of the "virtual" BootROM component.
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--! @details BootRom start address must implements address matching to the
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--! CPU reset vector (0x200) and all processing after power-on is
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--! using this memory block. BootRom size depends of the configuration
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--! and size of the generated hex file.
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--! Component implements one-clock access to the
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--! ROM without wait-staits. Datawidth depends of the AXI4 bus
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--! configuration.
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--! @param[in] tech Generic technology selector.
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--! @param[in] hex_filename Generic argument defining hex-file location.
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--! @param[in] clk System bus clock.
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--! @param[in] address Input address.
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--! @param[out] data Output data value.
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component BootRom_tech is
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generic (
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memtech : integer := 0;
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sim_hexfile : string
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);
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port (
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clk : in std_logic;
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address : in global_addr_array_type;
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data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
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);
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end component;
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--! @brief Declaration of the "virtual" RomImage component.
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--! @details This module stores pre-built firmware image that is coping
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--! into internal SRAM during Boot stage without any modificaiton.
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--! RomImage size is limited by global configuration parameter and
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--! it cannot be more than internal SRAM size. Component implements
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--! one-clock access to the ROM without wait-staits.
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--! Datawidth depends of the AXI4 bus configuration.
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--! @param[in] tech Generic technology selector.
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--! @param[in] sim_hexfile Generic argument defining hex-file location.
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--! @param[in] clk System bus clock.
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--! @param[in] address Input address.
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--! @param[out] data Output data value.
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component RomImage_tech is
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generic (
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memtech : integer := 0;
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sim_hexfile : string
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);
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port (
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clk : in std_logic;
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address : in global_addr_array_type;
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data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
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);
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end component;
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------------------------------------------------------------------------------
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--! @brief Galileo PRN codes ROM storage:
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--! @details This ROM is used in FSE Engine to form reference E1 reference
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--! signals. HEX-file isn't used for this ROM because 'inferred'
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--! module was built using "case when" operators.
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component RomPrn_tech is
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generic (
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generic_tech : integer := 0
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);
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port (
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i_clk : in std_logic;
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i_address : in std_logic_vector(12 downto 0);
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o_data : out std_logic_vector(31 downto 0)
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);
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end component;
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--! @brief Declaration of the "virtual" SRAM component with unaligned access.
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--! @details This module implements internal SRAM and support unaligned access
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--! without wait-states. For example it allows to read 4 bytes from
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--! address 0x3 for one clock.
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--! Component implements one-clock access without wait-staits.
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--! Datawidth depends of the AXI4 bus configuration.
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--! @param[in] memtech Generic technology selector.
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--! @param[in] abits Generic argument defining SRAM size as 2**abits.
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--! @param[in] clk System bus clock.
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--! @param[in] raddr Read address.
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--! @param[out] rdata Output data value.
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--! @param[in] waddr Write address.
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--! @param[in] we Write enable.
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--! @param[in] wstrb Byte selector to form write only for the specified bytes.
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--! @param[in] wdata Write data.
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component srambytes_tech is
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generic (
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memtech : integer := 0;
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abits : integer := 16;
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init_file : string := ""
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);
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port (
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clk : in std_logic;
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raddr : in global_addr_array_type;
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rdata : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
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waddr : in global_addr_array_type;
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we : in std_logic;
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wstrb : in std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
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wdata : in std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
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);
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end component;
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--! @brief Virtual SRAM block with fixed 32-bits data width.
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--! @details This module doesn't support byte access and always implements
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--! 4-bytes alignment.
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component Ram32_tech
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generic (
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generic_tech : integer := 0;
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generic_abits : integer := 10
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);
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port (
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i_clk : in std_logic;
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i_address : in std_logic_vector(generic_abits-1 downto 0);
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i_wr_ena : in std_logic;
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i_data : in std_logic_vector(31 downto 0);
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o_data : out std_logic_vector(31 downto 0)
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);
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end component;
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--! @brief Virtual SRAM block with fixed 64-bits data width.
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--! @details This module doesn't support byte access and always implements
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--! 4-bytes alignment.
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component Ram32x2_tech
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generic (
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generic_tech : integer := 0;
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generic_kWords : integer := 1
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);
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port (
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i_clk : in std_logic;
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i_address : in std_logic_vector(10+log2(generic_kWords)-1 downto 0);
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i_wr_ena : in std_logic_vector(1 downto 0);
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i_data : in std_logic_vector(63 downto 0);
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o_data : out std_logic_vector(63 downto 0)
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);
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end component;
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--! @brief Virtual SRAM block with fixed 64-bits data width.
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--! @details This module doesn't support byte access and always implements
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--! 8-bytes alignment.
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component Ram64_tech
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generic (
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generic_tech : integer := 0;
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generic_abits : integer := 4
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);
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port (
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i_clk : in std_logic;
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i_address : in std_logic_vector(generic_abits-1 downto 0);
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i_wr_ena : in std_logic;
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i_data : in std_logic_vector(63 downto 0);
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o_data : out std_logic_vector(63 downto 0)
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);
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end component;
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--! @brief dual-port RAM declaration.
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component syncram_2p_tech is
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generic (
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tech : integer := 0;
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abits : integer := 6;
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dbits : integer := 8;
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sepclk : integer := 0;
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wrfst : integer := 0;
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testen : integer := 0;
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words : integer := 0;
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custombits : integer := 1
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);
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port (
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rclk : in std_ulogic;
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renable : in std_ulogic;
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raddress : in std_logic_vector((abits -1) downto 0);
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dataout : out std_logic_vector((dbits -1) downto 0);
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wclk : in std_ulogic;
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write : in std_ulogic;
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waddress : in std_logic_vector((abits -1) downto 0);
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datain : in std_logic_vector((dbits -1) downto 0)
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);
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end component;
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end;
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