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--

------------------------------------------------------------------------------

-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"

-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"

------------------------------------------------------------------------------

-- CLK_OUT1____70.000

--

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

entity SysPLL_micron180 is

port

 (

  CLK_IN            : in     std_logic;

  -- Clock out ports

  CLK_OUT1          : out    std_logic;

  CLK_OUT2          : out    std_logic;

  -- Status and control signals

  RESET             : in     std_logic;

  LOCKED            : out    std_logic

 );

end SysPLL_micron180;

architecture rtl of SysPLL_micron180 is

begin

  CLK_OUT1 <= CLK_IN;

  LOCKED <= not RESET;

end rtl;