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-----------------------------------------------------------------------------

--! @file

--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.

--! @author    Sergey Khabarov - sergeykhbr@gmail.com

--! @brief     Testbench file for the TAP via UART

------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

library std;

use std.textio.all;

library commonlib;

use commonlib.types_common.all;

use commonlib.types_util.all;

--! Technology definition library.

library techmap;

--! Technology constants definition.

use techmap.gencomp.all;

--! AMBA system bus specific library

library ambalib;

--! AXI4 configuration constants.

use ambalib.types_amba4.all;

--! Rocket-chip specific library

library misclib;

--! SOC top-level component declaration.

use misclib.types_misc.all;

 --! Top-level implementaion library

library work;

--! Target dependable configuration: RTL, FPGA or ASIC.

use work.config_target.all;

--! Target independable configuration.

use work.config_common.all;

entity tap_uart_tb is

  constant INCR_TIME : time := 3571 ps;--100 ns;--3571 ps;

end tap_uart_tb;

architecture behavior of tap_uart_tb is

  constant UART_BIN_SIZE : integer := 24;

  -- input/output signals:

  signal i_rst : std_logic := '1';

  signal i_nrst : std_logic;

  signal i_clk : std_logic;

  signal i_uart1_ctsn : std_logic := '0';

  signal i_uart1_rd : std_logic := '1';

  signal o_uart1_td : std_logic;

  signal o_uart1_rtsn : std_logic;

  signal uart_wr_str : std_logic;

  signal uart_instr : string(1 to 256);

  signal uart_busy : std_logic;

  signal uart_bin_data : std_logic_vector(8*UART_BIN_SIZE-1 downto 0);

  signal uart_bin_bytes_sz : integer;

  signal aximi   : nasti_master_in_vector;

  signal aximo   : nasti_master_out_vector;

  signal axisi   : nasti_slave_in_vector;

  signal axiso   : nasti_slaves_out_vector;

  signal slv_cfg : nasti_slave_cfg_vector;

  signal uarti   : uart_in_type;

  signal uarto   : uart_out_type;

  signal clk_cur: std_logic := '1';

  signal check_clk_bus : std_logic := '0';

  signal iClkCnt : integer := 0;

  signal iErrCnt : integer := 0;

  signal iErrCheckedCnt : integer := 0;

  component uart_sim is

  generic (

    clock_rate : integer := 10;

    binary_bytes_max : integer := 8;

    use_binary : boolean := false

  );

  port (

    rst : in std_logic;

    clk : in std_logic;

    wr_str : in std_logic;

    instr : in string;

    bin_data : in std_logic_vector(8*binary_bytes_max-1 downto 0);

    bin_bytes_sz : in integer;

    td  : in std_logic;

    rtsn : in std_logic;

    rd  : out std_logic;

    ctsn : out std_logic;

    busy : out std_logic

  );

  end component;

begin

  clk_cur <= not clk_cur after 12.5 ns;

  -- Process of reading

--  procReadingFile : process

--    variable clk_next: std_logic;

--  begin

--    wait for INCR_TIME;

--    while true loop

--      clk_next := not clk_cur;

--      if (clk_next = '1' and clk_cur = '0') then

--        check_clk_bus <= '1';

--      end if;

--      wait for 1 ps;

--      check_clk_bus <= '0';

--      clk_cur <= clk_next;

--      wait for INCR_TIME;

--      if clk_cur = '1' then

--        iClkCnt <= iClkCnt + 1;

--      end if;

--    end loop;

--    report "Total clocks checked: " & tost(iErrCheckedCnt) & " Errors: " & tost(iErrCnt);

--    wait for 1 sec;

--  end process procReadingFile;

  i_clk <= clk_cur;

  procSignal : process (i_clk, iClkCnt)

  begin

    if rising_edge(i_clk) then

      --! @note to make sync. reset  of the logic that are clocked by

      --!       htif_clk which is clock/512 by default.

      if iClkCnt = 15 then

        i_rst <= '0';

      end if;

    end if;

  end process procSignal;

  i_nrst <= not i_rst;

  udatagen0 : process (i_clk, iClkCnt)

  begin

    -- 0x31 - magic number at the beginning of packet

    if falling_edge(i_clk) then

        uart_wr_str <= '0';

        if iClkCnt = 82000 then

           -- initialize baudrate detector

           uart_wr_str <= '1';

           uart_bin_data(8*UART_BIN_SIZE-1 downto 8*(UART_BIN_SIZE-3)) <= X"555555";

           uart_bin_bytes_sz <= 3;

        elsif iClkCnt = 108000 then

           uart_wr_str <= '1';

           -- read 4 bytes at address: 0x00000000.10000004 => 04 00 00 10.00 00 00 00

           uart_bin_data(8*UART_BIN_SIZE-1 downto 8*(UART_BIN_SIZE-10)) <= X"31_80_0400001000000000";

           uart_bin_bytes_sz <= 10;

        elsif iClkCnt = 168000 then

           uart_wr_str <= '1';

           -- read 16 bytes at address: 0x00000000.10000020 => 20 00 00 10.00 00 00 00

           uart_bin_data(8*UART_BIN_SIZE-1 downto 8*(UART_BIN_SIZE-10)) <= X"31_83_2000001000000000";

           uart_bin_bytes_sz <= 10;

        elsif iClkCnt = 288000 then

           uart_wr_str <= '1';

           -- write 4 bytes at address: 0x00000000.10000024 => 31_24 00 00 10.00 00 00 00

           --               wdata : 0xfeedface => ce fa ed fe

           uart_bin_data(8*UART_BIN_SIZE-1 downto 8*(UART_BIN_SIZE-14)) <= X"31_c0_2400001000000000_cefaedfe";

           uart_bin_bytes_sz <= 14;

        elsif iClkCnt = 348000 then

           uart_wr_str <= '1';

           -- write 8 bytes at address: 0x00000000.10000104 => 04 01 00 10.00 00 00 00

           --               wdata : [0xfeedface, 0xdeadbeef] => ce fa ed fe.ef be ad de

           uart_bin_data(8*UART_BIN_SIZE-1 downto 8*(UART_BIN_SIZE-18)) <= X"31_c1_0401001000000000_cefaedfeefbeadde";

           uart_bin_bytes_sz <= 18;

        end if;

    end if;

  end process;

  uart0 : uart_sim generic map (

    clock_rate => (40000000/115200),

    binary_bytes_max => UART_BIN_SIZE,

    use_binary => true

  ) port map (

    rst => i_rst,

    clk => i_clk,

    wr_str => uart_wr_str,

    instr => uart_instr,

    bin_data => uart_bin_data,

    bin_bytes_sz => uart_bin_bytes_sz,

    td  => o_uart1_td,

    rtsn => o_uart1_rtsn,

    rd  => i_uart1_rd,

    ctsn => i_uart1_ctsn,

    busy => uart_busy

  );

  aximo(CFG_NASTI_MASTER_UNCACHED) <= nasti_master_out_none;

  aximo(CFG_NASTI_MASTER_ETHMAC) <= nasti_master_out_none;

  aximo(CFG_NASTI_MASTER_MSTUART) <= nasti_master_out_none;

  axiso(CFG_NASTI_SLAVE_BOOTROM) <= nasti_slave_out_none;

  axiso(CFG_NASTI_SLAVE_ROMIMAGE) <= nasti_slave_out_none;

  --axiso(CFG_NASTI_SLAVE_SRAM) <= nasti_slave_out_none;

  axiso(CFG_NASTI_SLAVE_UART1) <= nasti_slave_out_none;

  axiso(CFG_NASTI_SLAVE_GPIO) <= nasti_slave_out_none;

  axiso(CFG_NASTI_SLAVE_IRQCTRL) <= nasti_slave_out_none;

  axiso(CFG_NASTI_SLAVE_SPI_FLASH) <= nasti_slave_out_none;

  axiso(CFG_NASTI_SLAVE_ETHMAC) <= nasti_slave_out_none;

  axiso(CFG_NASTI_SLAVE_DSU) <= nasti_slave_out_none;

  axiso(CFG_NASTI_SLAVE_GPTIMERS) <= nasti_slave_out_none;

  axiso(CFG_NASTI_SLAVE_PNP) <= nasti_slave_out_none;

  slv_cfg(CFG_NASTI_SLAVE_BOOTROM) <= nasti_slave_config_none;

  slv_cfg(CFG_NASTI_SLAVE_ROMIMAGE) <= nasti_slave_config_none;

  --slv_cfg(CFG_NASTI_SLAVE_SRAM) <= nasti_slave_config_none;

  slv_cfg(CFG_NASTI_SLAVE_UART1) <= nasti_slave_config_none;

  slv_cfg(CFG_NASTI_SLAVE_GPIO) <= nasti_slave_config_none;

  slv_cfg(CFG_NASTI_SLAVE_IRQCTRL) <= nasti_slave_config_none;

  slv_cfg(CFG_NASTI_SLAVE_SPI_FLASH) <= nasti_slave_config_none;

  slv_cfg(CFG_NASTI_SLAVE_ETHMAC) <= nasti_slave_config_none;

  slv_cfg(CFG_NASTI_SLAVE_DSU) <= nasti_slave_config_none;

  slv_cfg(CFG_NASTI_SLAVE_GPTIMERS) <= nasti_slave_config_none;

  slv_cfg(CFG_NASTI_SLAVE_PNP) <= nasti_slave_config_none;

  ctrl0 : axictrl generic map (

    watchdog_memop => 0

  ) port map (

    i_clk    => i_clk,

    i_nrst   => i_nrst,

    i_slvcfg => slv_cfg,

    i_slvo   => axiso,

    i_msto   => aximo,

    o_slvi   => axisi,

    o_msti   => aximi,

    o_miss_irq  => open,

    o_miss_addr => open,

    o_bus_util_w => open,

    o_bus_util_r => open

  );

  -- signal parsment and assignment

  uarti.cts <= not i_uart1_ctsn;

  uarti.rd <= i_uart1_rd;

  tt : uart_tap port map (

    nrst     => i_nrst,

    clk      => i_clk,

    i_uart   => uarti,

    o_uart   => uarto,

    i_msti   => aximi(CFG_NASTI_MASTER_CACHED),

    o_msto   => aximo(CFG_NASTI_MASTER_CACHED),

    o_mstcfg => open

  );

  o_uart1_td <= uarto.td;

  o_uart1_rtsn <= not uarto.rts;

  sram0 : nasti_sram generic map (

    memtech  => 0,

    xaddr    => 16#10000#,

    xmask    => 16#fff80#,            -- 512 KB mask

    abits    => (10 + log2(512)),     -- 512 KB address

    init_file => CFG_SIM_FWIMAGE_HEX  -- Used only for inferred

  ) port map (

    clk  => i_clk,

    nrst => i_nrst,

    cfg  => slv_cfg(CFG_NASTI_SLAVE_SRAM),

    i    => axisi(CFG_NASTI_SLAVE_SRAM),

    o    => axiso(CFG_NASTI_SLAVE_SRAM)

  );

  procCheck : process (i_rst, clk_cur)

  begin

    if rising_edge(clk_cur) then

        iClkCnt <= iClkCnt + 1;

    end if;

  end process procCheck;

end;