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URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [simulation/] [global.do] - Blame information for rev 48

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Line No. Rev Author Line
1 48 cwalter
onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -divider {Global Signals}
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add wave -noupdate -format Logic /tb_rise_vhd/reset
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add wave -noupdate -format Logic /tb_rise_vhd/clk
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add wave -noupdate -divider {Instruction Fetch Unit}
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add wave -noupdate -format Literal -radix hexadecimal /tb_rise_vhd/uut/if_stage_unit/pc
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add wave -noupdate -format Literal -expand /tb_rise_vhd/uut/if_stage_unit/if_id_register
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add wave -noupdate -format Logic /tb_rise_vhd/uut/if_stage_unit/clear_in
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add wave -noupdate -format Logic /tb_rise_vhd/uut/if_stage_unit/stall_in
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add wave -noupdate -divider {Instruction Decode Unit}
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add wave -noupdate -format Literal -expand /tb_rise_vhd/uut/id_stage_unit/id_ex_register
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add wave -noupdate -format Logic /tb_rise_vhd/uut/id_stage_unit/clear_in
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add wave -noupdate -format Logic /tb_rise_vhd/uut/id_stage_unit/stall_in
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add wave -noupdate -format Logic /tb_rise_vhd/uut/id_stage_unit/stall_out
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add wave -noupdate -divider {Execute Unit}
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add wave -noupdate -format Literal -expand /tb_rise_vhd/uut/ex_stage_unit/id_ex_register
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add wave -noupdate -divider {Memory Unit}
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add wave -noupdate -format Literal /tb_rise_vhd/uut/mem_stage_unit/ex_mem_register
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add wave -noupdate -format Logic /tb_rise_vhd/uut/mem_stage_unit/dmem_wr_enable
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add wave -noupdate -format Literal -radix hexadecimal /tb_rise_vhd/uut/mem_stage_unit/dmem_data_out
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add wave -noupdate -format Literal -radix hexadecimal /tb_rise_vhd/uut/mem_stage_unit/dmem_data_in
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add wave -noupdate -format Literal -radix hexadecimal /tb_rise_vhd/uut/mem_stage_unit/dmem_addr
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add wave -noupdate -divider {Write Back Unit}
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add wave -noupdate -format Literal /tb_rise_vhd/uut/mem_stage_unit/mem_wb_register
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add wave -noupdate -format Logic /tb_rise_vhd/uut/wb_stage_unit/dreg_enable
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add wave -noupdate -format Literal -radix decimal /tb_rise_vhd/uut/wb_stage_unit/dreg_addr
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add wave -noupdate -format Literal /tb_rise_vhd/uut/wb_stage_unit/dreg
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add wave -noupdate -divider Registers
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add wave -noupdate -format Literal -expand /tb_rise_vhd/uut/register_file_unit/regs
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {83205 ps} 0}
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configure wave -namecolwidth 302
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configure wave -valuecolwidth 155
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configure wave -justifyvalue left
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configure wave -signalnamewidth 0
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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update
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WaveRestoreZoom {0 ps} {100385 ps}

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