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cwalter |
;
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; Copyright Model Technology, a Mentor Graphics
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; Corporation company 2006, - All rights reserved.
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;
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[Library]
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std = $MODEL_TECH/../std
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ieee = $MODEL_TECH/../ieee
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verilog = $MODEL_TECH/../verilog
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vital2000 = $MODEL_TECH/../vital2000
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std_developerskit = $MODEL_TECH/../std_developerskit
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synopsys = $MODEL_TECH/../synopsys
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modelsim_lib = $MODEL_TECH/../modelsim_lib
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; VHDL Section
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unisim = $MODEL_TECH/../xilinx/vhdl/unisim
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simprim = $MODEL_TECH/../xilinx/vhdl/simprim
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xilinxcorelib = $MODEL_TECH/../xilinx/vhdl/xilinxcorelib
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aim = $MODEL_TECH/../xilinx/vhdl/aim
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pls = $MODEL_TECH/../xilinx/vhdl/pls
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cpld = $MODEL_TECH/../xilinx/vhdl/cpld
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; Verilog Section
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unisims_ver = $MODEL_TECH/../xilinx/verilog/unisims_ver
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uni9000_ver = $MODEL_TECH/../xilinx/verilog/uni9000_ver
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simprims_ver = $MODEL_TECH/../xilinx/verilog/simprims_ver
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xilinxcorelib_ver = $MODEL_TECH/../xilinx/verilog/xilinxcorelib_ver
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aim_ver = $MODEL_TECH/../xilinx/verilog/aim_ver
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cpld_ver = $MODEL_TECH/../xilinx/verilog/cpld_ver
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work = work
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[vcom]
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; Turn on VHDL-1993 as the default. Normally is off.
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VHDL93 = 1
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; Show source line containing error. Default is off.
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; Show_source = 1
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; Turn off unbound-component warnings. Default is on.
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; Show_Warning1 = 0
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; Turn off process-without-a-wait-statement warnings. Default is on.
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; Show_Warning2 = 0
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; Turn off null-range warnings. Default is on.
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; Show_Warning3 = 0
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; Turn off no-space-in-time-literal warnings. Default is on.
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; Show_Warning4 = 0
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; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
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; Show_Warning5 = 0
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; Turn off optimization for IEEE std_logic_1164 package. Default is on.
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; Optimize_1164 = 0
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; Turn on resolving of ambiguous function overloading in favor of the
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; "explicit" function declaration (not the one automatically created by
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; the compiler for each type declaration). Default is off.
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Explicit = 1
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; Turn off VITAL compliance checking. Default is checking on.
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; NoVitalCheck = 1
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; Ignore VITAL compliance checking errors. Default is to not ignore.
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; IgnoreVitalErrors = 1
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; Turn off VITAL compliance checking warnings. Default is to show warnings.
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; Show_VitalChecksWarnings = false
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; Turn off "loading..." messages. Default is messages on.
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; Quiet = 1
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; Turn on some limited synthesis rule compliance checking. Checks only:
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; -- signals used (read) by a process must be in the sensitivity list
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; CheckSynthesis = 1
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[vlog]
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; Turn off "loading..." messages. Default is messages on.
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; Quiet = 1
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; Turn on Verilog hazard checking (order-dependent accessing of global vars).
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; Default is off.
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; Hazard = 1
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; Turn on converting regular Verilog identifiers to uppercase. Allows case
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; insensitivity for module names. Default is no conversion.
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; UpCase = 1
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; Turns on incremental compilation of modules
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; Incremental = 1
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[vsim]
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; Simulator resolution
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; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
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jlechner |
resolution = 1ns
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cwalter |
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; User time unit for run commands
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; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
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; unit specified for Resolution. For example, if Resolution is 100ps,
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; then UserTimeUnit defaults to ps.
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UserTimeUnit = default
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; Default run length
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cwalter |
RunLength = 200 ns
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cwalter |
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; Maximum iterations that can be run without advancing simulation time
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cwalter |
IterationLimit = 1000
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cwalter |
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; Directive to license manager:
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; vhdl Immediately reserve a VHDL license
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; vlog Immediately reserve a Verilog license
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; plus Immediately reserve a VHDL and Verilog license
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; nomgc Do not look for Mentor Graphics Licenses
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; nomti Do not look for Model Technology Licenses
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; noqueue Do not wait in the license queue when a license isn't available
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; License = plus
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; Stop the simulator after an assertion message
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; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
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jlechner |
BreakOnAssertion = 4
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cwalter |
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; Assertion Message Format
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; %S - Severity Level
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; %R - Report Message
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; %T - Time of assertion
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; %D - Delta
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; %I - Instance or Region pathname (if available)
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; %% - print '%' character
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; AssertionFormat = "** %S: %R\n Timf: %T Iteration: %D%I\n"
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; Assertion File - alternate file for storing assertion messages
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; AssertFile = assert.log
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; Default radix for all windows and commands...
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; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
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DefaultRadix = symbolic
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; VSIM Startup command
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; Startup = do startup.do
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; File for saving command transcript
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TranscriptFile = transcript
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; File for saving command history
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;CommandHistory = cmdhist.log
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; Specify whether paths in simulator commands should be described
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; in VHDL or Verilog format. For VHDL, PathSeparator = /
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; for Verilog, PathSeparator = .
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PathSeparator = /
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; Specify the dataset separator for fully rooted contexts.
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; The default is ':'. For example, sim:/top
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; Must not be the same character as PathSeparator.
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DatasetSeparator = :
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; Disable assertion messages
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; IgnoreNote = 1
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; IgnoreWarning = 1
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; IgnoreError = 1
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; IgnoreFailure = 1
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; Default force kind. May be freeze, drive, or deposit
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; or in other terms, fixed, wired or charged.
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; DefaultForceKind = freeze
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; If zero, open files when elaborated
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; else open files on first read or write
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; DelayFileOpen = 0
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; Control VHDL files opened for write
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; 0 = Buffered, 1 = Unbuffered
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UnbufferedOutput = 0
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; Control number of VHDL files open concurrently
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; This number should always be less then the
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; current ulimit setting for max file descriptors
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; 0 = unlimited
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ConcurrentFileLimit = 40
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; This controls the number of hierarchical regions displayed as
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; part of a signal name shown in the waveform window. The default
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; value or a value of zero tells VSIM to display the full name.
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; WaveSignalNameWidth = 0
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; Turn off warnings from the std_logic_arith, std_logic_unsigned
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; and std_logic_signed packages.
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; StdArithNoWarnings = 1
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; Turn off warnings from the IEEE numeric_std and numeric_bit
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; packages.
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; NumericStdNoWarnings = 1
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; Control the format of a generate statement label. Don't quote it.
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; GenerateFormat = %s__%d
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; Specify whether checkpoint files should be compressed.
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; The default is to be compressed.
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; CheckpointCompressMode = 0
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; List of dynamically loaded objects for Verilog PLI applications
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; Veriuser = veriuser.sl
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206 |
64 |
jlechner |
DelayFileOpen = 1
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48 |
cwalter |
[lmc]
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[Project]
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Project_Version = 6
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Project_DefaultLib = work
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Project_SortMethod = unused
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103 |
cwalter |
Project_Files_Count = 16
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81 |
cwalter |
Project_File_0 = C:/Projects/RISE/vhdl/barrel.vhd
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103 |
cwalter |
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168773985 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 93
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81 |
cwalter |
Project_File_1 = C:/Projects/RISE/vhdl/tb_rise.vhd
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108 |
cwalter |
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168985980 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 93
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81 |
cwalter |
Project_File_2 = C:/Projects/rise/vhdl/rise_pack_sim.vhd
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103 |
cwalter |
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168772314 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 93
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81 |
cwalter |
Project_File_3 = C:/Projects/RISE/vhdl/rlu.vhd
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220 |
103 |
cwalter |
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168792249 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 93
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221 |
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Project_File_4 = C:/Projects/RISE/vhdl/idmem.vhd
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222 |
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Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168792283 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 93
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223 |
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Project_File_5 = C:/Projects/RISE/vhdl/wb_stage.vhd
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224 |
108 |
cwalter |
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168989804 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
225 |
103 |
cwalter |
Project_File_6 = C:/Projects/RISE/vhdl/register_file.vhd
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226 |
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Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168772314 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 93
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227 |
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Project_File_7 = C:/Projects/rise/vhdl/rise_const_pack.vhd
|
228 |
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Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168772314 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
229 |
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Project_File_8 = C:/Projects/RISE/vhdl/ex_stage.vhd
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230 |
108 |
cwalter |
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168987085 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
231 |
103 |
cwalter |
Project_File_9 = C:/Projects/RISE/vhdl/id_stage.vhd
|
232 |
108 |
cwalter |
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168989788 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 13 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
233 |
103 |
cwalter |
Project_File_10 = C:/Projects/RISE/vhdl/imem.vhd
|
234 |
108 |
cwalter |
Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168985980 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
235 |
103 |
cwalter |
Project_File_11 = C:/Projects/RISE/vhdl/rise_pack.vhd
|
236 |
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Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168772314 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_vopt 0 vhdl_showsource 0 vhdl_warn2 1 vhdl_explicit 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 1 compile_to work compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 93
|
237 |
108 |
cwalter |
Project_File_12 = C:/Projects/RISE/vhdl/if_stage.vhd
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238 |
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Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168987162 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 93
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239 |
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Project_File_13 = C:/Projects/RISE/vhdl/mem_stage.vhd
|
240 |
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Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168985586 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
241 |
|
|
Project_File_14 = C:/Projects/RISE/vhdl/dmem.vhd
|
242 |
|
|
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168985980 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
243 |
|
|
Project_File_15 = C:/Projects/RISE/vhdl/rise.vhd
|
244 |
|
|
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1168985980 vhdl_disableopt 0 vhdl_vital 0 vhdl_vopt 0 vhdl_warn1 1 vhdl_explicit 1 vhdl_warn2 1 vhdl_showsource 0 vhdl_warn3 1 vhdl_0InOptions {} vhdl_warn4 1 vhdl_options {} vhdl_warn5 1 ood 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 93
|
245 |
48 |
cwalter |
Project_Sim_Count = 1
|
246 |
|
|
Project_Sim_0 = RISE TB
|
247 |
|
|
Project_Sim_P_0 = Generics {} timing default -std_output {} -nopsl 0 +notimingchecks 0 -L {} selected_du {} -hazards 0 -sdf {} ok 1 folder {Top Level} -0in 0 -nosva 0 -absentisempty 0 +pulse_r {} -multisource_delay {} OtherArgs {} +pulse_e {} -t default -vital2.2b 0 +plusarg {} -sdfnoerror 0 -coverage 0 vopt_env 0 is_vopt_flow 0 -memprof 0 additional_dus work.tb_rise_vhd -nofileshare 0 -noglitch 0 +no_pulse_msg 0 -assertdebug 0 -wlf {} -std_input {} -Lf {} -sdfnowarn 0 -assertfile {} -0in_options {}
|
248 |
|
|
Project_Folder_Count = 0
|
249 |
|
|
Echo_Compile_Output = 0
|
250 |
|
|
Save_Compile_Report = 1
|
251 |
|
|
Project_Opt_Count = 0
|
252 |
|
|
ForceSoftPaths = 0
|
253 |
|
|
ReOpenSourceFiles = 1
|
254 |
|
|
VERILOG_DoubleClick = Edit
|
255 |
|
|
VERILOG_CustomDoubleClick =
|
256 |
|
|
VHDL_DoubleClick = Edit
|
257 |
|
|
VHDL_CustomDoubleClick =
|
258 |
|
|
PSL_DoubleClick = Edit
|
259 |
|
|
PSL_CustomDoubleClick =
|
260 |
|
|
TEXT_DoubleClick = Edit
|
261 |
|
|
TEXT_CustomDoubleClick =
|
262 |
|
|
SYSTEMC_DoubleClick = Edit
|
263 |
|
|
SYSTEMC_CustomDoubleClick =
|
264 |
|
|
TCL_DoubleClick = Edit
|
265 |
|
|
TCL_CustomDoubleClick =
|
266 |
|
|
MACRO_DoubleClick = Edit
|
267 |
|
|
MACRO_CustomDoubleClick =
|
268 |
|
|
VCD_DoubleClick = Edit
|
269 |
|
|
VCD_CustomDoubleClick =
|
270 |
|
|
SDF_DoubleClick = Edit
|
271 |
|
|
SDF_CustomDoubleClick =
|
272 |
|
|
XML_DoubleClick = Edit
|
273 |
|
|
XML_CustomDoubleClick =
|
274 |
|
|
LOGFILE_DoubleClick = Edit
|
275 |
|
|
LOGFILE_CustomDoubleClick =
|
276 |
103 |
cwalter |
EditorState = {tabbed horizontal 1} {C:/Projects/RISE/vhdl/mem_stage.vhd 0 1} {C:/Projects/RISE/vhdl/rise.vhd 0 0} {C:/Projects/RISE/vhdl/id_stage.vhd 0 0} {C:/Projects/RISE/vhdl/dmem.vhd 0 0} {C:/Projects/RISE/vhdl/wb_stage.vhd 0 0} {C:/Projects/RISE/vhdl/ex_stage.vhd 0 0} {C:/Projects/RISE/vhdl/tb_rise.vhd 0 0} {C:/Projects/RISE/vhdl/if_stage.vhd 0 0} {C:/Projects/RISE/vhdl/barrel.vhd 0 0} {C:/Projects/RISE/vhdl/idmem.vhd 0 0}
|
277 |
48 |
cwalter |
Project_Major_Version = 6
|
278 |
|
|
Project_Minor_Version = 1
|